A7 B7 2808twf.doc/005A7 B7 2808twf.doc / 005
-S-S£-4-jL 五、發明説明（ί ) 本發明是有關於一種自動對準金屬矽化物（Self-Aligned SUicide) 之製造方法， 且特別是有關於一種在閘極 形成自動對準金屬矽化物之製造方法。 當金氧半導體（MetaLOxide-Semiconductor ; MOS)元件 之積集度(Integrity)增加，使得MOS元件的汲極與源極的 電阻，逐漸上升到與MOS通道（Channel)的電阻相當時， 爲降低汲極與源極的片電阻（Sheet Resistance)，並確保金 屬與MOS間的淺接面（Shallow Junction)，使用一種自動對 準金屬矽化物（Self Aligned Silicide)之製造方法，又稱 Salicide。 請參照第1A至1D圖，繪示習知之自動對準金屬矽化 物之製造方法。首先在第1A圖中，在一矽基底1上形成 閘極2，其中閘極2例如由多晶矽所構成，並以閘極2爲 罩幕，進行低濃度離子植入，在閘極2兩側之矽基底1內 部形成輕摻雜汲極區3。 接著，在第圖中，在閘極2兩側形成間隙壁4，並 以閛極2與間隙壁4爲罩幕，進行高濃度離子植入，形成 源/汲極5。 接著，請參考第1C圖，形成一金屬矽化物於閘極2 與源/汲極5上，例如以厚度在200A到1000A之金屬鈦 (Ti)，使用磁控直流濺鍍的方式，沈積在整個晶片表面上， 利用高溫之快速加熱製程（Rapid Thermal Processing; RTP)，使得沈積的鈦與源/汲極5之矽和閘極2之多晶矽， 反應產生矽化鈦6(TiSi2)，再將未參與反應與反應後所剩 3 -^1-1 ^^1 —-^1 1^1 I -: —i - ^II ϋ (請先閱讀背面之注意事項再填寫本頁) 訂 本紙fil尺度速用中國國家標準（CNS > Α4規格（2!0Χ297公釐） A7 B7 2808twf.doc/005 厶6 66 1 3 五、發明説明（> ) 的鈦去除，留下閘極2與源/汲極5之矽化鈦6。 袈------訂 {#先閱讀背面之注意事項再填寫本頁) 接著，在第1D圖中，沈積一氧化層8於矽化鈦6上， 例如使用高密度電發化學氣相沈積（High-density plasma-CVD)。 其中，自動對準金屬矽化物之製程中，不需要使用到 微影（Photolithography)之步驟，所以在源/汲極之砂和閘極 之多晶矽製作低阻値之金屬矽化物(TiSi2)，能夠很快的得 到具有較低之RC時間延遲之MOS元件的開關頻率 (Switching Frequency)，適用於一般快速切換之邏輯（Logic) 元件。相較於使用多晶矽化金屬(Polycide)之記憶體元件， 如SRAM、DRAM，在閘極上所形成矽化鎢(WSix)，具有較 高的阻値，造成較高的時間延遲。而且對多晶矽化金 屬（Polycide)中，使用埋入通道(Buried channel)之PMOS電 晶體，在關鍵距離（Critical Dimension ; CD)減少時’會使 得截止電流(Ioff)提高，加上導通電流(Ion)也比較小’使得 記憶體元件不易判斷，產生錯誤動作。 雖然自動對準金屬矽化物之製程具有上述優點’但是 在製程中仍會有下列缺點： 經來‘部中决枒準局員T,消费合竹社印^. 1. 使用快速加熱製程RTP產生矽化鈦時’在源/汲極 與矽基底間的接面，會因受熱產生劣化情形’在實際使用 時，會有接面漏電流發生。 2. 在將未參與反應與反應後所剩的鈦去除後’在閘極 上所產生之矽化鈦’會造成側部延伸(Lateral extension)現 象，即矽化鈦覆蓋到間隙壁部分，當在製做金屬內連線 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 2808twf , do4 6 66 1 3 c/005 A7 B7 好濟部十决椋埤局負T,消贽合竹社印^' 五、發明説明（今） (Metal Interconnects)之插塞（Plug)時，很容易使得閛極與源/ 極間，發生短路情形。 因此本發明的目的就是在提供一種自動對準金屬矽化 物之製造方法。應用在以多晶矽化金屬（Polycide)之記憶 體，不但可以有效降低矽化鎢(WSix)之高電阻値，使得RC 時間延遲降低。並使得PMOS電晶體以使用表面通道 (surface channel)之自動對準金屬矽化物之製造方法，避免 因關鏈距離降低，使得截止電流(I〇ff)提高情狀’而影響記 億體元件運作。 本發明之另一目的在提供一種自動對準金屬矽化物之 製造方法，在源/汲極部分不形成金屬矽化物(TiSi2) ’所以 能夠有效降低接面漏電流，並且在閘極上事先形成介電 層，最後再去除該介電層後，在此處形成金屬矽化物’利 用間隙壁之距離作隔離，所以更能避免閘極與源/汲極產生 短路情況。 根據本發明的目的，提出一種自動對準金屬较化物之 方法，包括： 首先在矽基底上，定義並形成閘極區，接著在聞極區 上形成介電層，然後在閘極區兩側之矽基底內部’形成輕 摻雜汲極區。接著閘極兩側形成間隙嬖’再對間隙壁兩側 之該矽基底內部，形成一源/汲極區，然後在源/汲極區與 介電層上，沈積氧化層。接著去除氧化層直到介電層上’ 再去除介電層，最後在去除之該介電餍的位置上’形成一 金屬矽化物。 5 本紙張尺度適用中國國家標率（CNS ) A4規格{ 210X297公釐） I衣------訂------r (請先閲讀背面之注意事項再填寫本頁) 2808twf.doc/005 A7 4 6 66 1 3 B7 五、發明説明（Lf ) 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1A至1D圖繪示習知的自動對準金屬矽化物之製造 方法圖形；以及 第2A至2E圖繪示依照本發明一較佳實施例的自動對 準金屬矽化物之製造方法圖形。 ^ 標號之簡單說明： 1，11:政基底 2,12:聞極 3，14:輕摻雜汲極區 4，15:間隙壁 5,16:源/汲極 6,18:矽化鈦 8,17:氧化層 13:介電層 實施例 請參照第2A至2E圖，繪示依照本發明一較佳實施例 的自動對準金屬矽化物之製造方法圖形。 首先，在第2A圖中，提供一矽基底11，接著定義並 形成一閘極區12，其中閘極部分例如由多晶矽所構成。然 後在閘極區12上面再形成一介電層13，該介電層13例如 由氮化矽構成。最後，於閘極區兩側之矽基底內部，進行 6-SS £ -4-jL 5. Description of the Invention The invention relates to a method for manufacturing self-aligned metal suicide (Self-Aligned SUicide), and more particularly to a method for forming self-aligned metal on a gate electrode. Manufacturing method of silicide. When the metal-oxide-semiconductor (MetaLOxide-Semiconductor; MOS) device's integration (Integrity) increases, the resistance of the drain and source of the MOS device gradually rises to be equivalent to the resistance of the MOS channel. The sheet resistance of the electrode and the source, and to ensure the shallow junction between the metal and the MOS (Shallow Junction), a manufacturing method of self-aligned metal silicide (Self Aligned Silicide), also known as Salicide. Please refer to FIGS. 1A to 1D to illustrate a conventional method for manufacturing a self-aligned metal silicide. First, in FIG. 1A, a gate 2 is formed on a silicon substrate 1. The gate 2 is made of, for example, polycrystalline silicon, and the gate 2 is used as a screen for low-concentration ion implantation. A lightly doped drain region 3 is formed inside the silicon substrate 1. Next, in the figure, a gap wall 4 is formed on both sides of the gate electrode 2, and a high-concentration ion implantation is performed with the hafnium electrode 2 and the gap wall 4 as a mask to form a source / drain electrode 5. Next, referring to Figure 1C, a metal silicide is formed on gate 2 and source / drain 5, for example, metal titanium (Ti) with a thickness of 200A to 1000A is deposited on the magnetron DC sputtering method. On the entire surface of the wafer, a rapid thermal processing (RTP) process is used to cause the deposited titanium to react with the source / drain 5 silicon and gate 2 polycrystalline silicon to generate titanium silicide 6 (TiSi2). Participate in the reaction and the remaining 3-^ 1-1 ^^ 1 —- ^ 1 1 ^ 1 I-: —i-^ II ϋ (Please read the precautions on the back before filling this page) Using Chinese National Standard (CNS > A4 Specification (2! 0 × 297mm) A7 B7 2808twf.doc / 005 厶 6 66 1 3 V. Description of the Invention (>) Titanium Removal, leaving Gate 2 and Source / Drain Titanium silicide 6 for pole 5. 袈 ------ Order {#Read the precautions on the back before filling this page) Then, in Figure 1D, deposit an oxide layer 8 on the titanium silicide 6, such as using high High-density plasma-CVD. Among them, the process of automatically aligning metal silicide does not require the use of photolithography, so the low-resistance metal silicide (TiSi2) can be produced in the source / drain sand and gate polysilicon. The switching frequency of the MOS device with a lower RC time delay is quickly obtained, which is suitable for general fast switching logic devices. Compared with polycide memory elements, such as SRAM and DRAM, tungsten silicide (WSix) formed on the gate has a higher resistance and causes a higher time delay. In polycide, the use of a buried channel PMOS transistor will reduce the critical distance (Critical Dimension (CD)) and increase the off current (Ioff) and the on current (Ion). ) Is also relatively small, which makes it difficult to judge the memory elements, and produces erroneous actions. Although the process of automatically aligning metal silicides has the above advantages, but there are still the following disadvantages in the process: The Ministry of Commerce, the Prospective Administrator T, Consumption of Hezhusha ^. 1. Use rapid heating process RTP to generate silicidation In the case of titanium, the junction between the source / drain and the silicon substrate will be deteriorated due to heat. In actual use, a junction leakage current will occur. 2. After removing the titanium that is not involved in the reaction and the reaction, the "silicon titanium produced on the gate" will cause a lateral extension phenomenon, that is, the titanium silicide covers the gap wall part, and it will be produced when Metal interconnects 4 This paper is sized for Chinese National Standards (CNS) A4 (210X297 mm) 2808twf, do4 6 66 1 3 c / 005 A7 B7 The Ministry of Health's Tenth Decision Bureau lost T Imprint ^ '5. When the plug of the invention (present) (Metal Interconnects) plug, it is easy to make a short circuit between the source and the electrode. It is therefore an object of the present invention to provide a method for automatically aligning a metal silicide. Application in polycide memory can not only effectively reduce the high resistance of tungsten silicide (WSix), but also reduce the RC time delay. And make PMOS transistor use surface channel (surface channel) to automatically align metal silicide manufacturing method, to avoid the cut-off distance, which makes the cut-off current (I0ff) to improve the situation ’and affect the operation of the device. Another object of the present invention is to provide a method for automatically aligning a metal silicide, which does not form a metal silicide (TiSi2) at the source / drain portion, so it can effectively reduce junction leakage current, and form a dielectric on the gate in advance. The electrical layer, and finally after removing the dielectric layer, a metal silicide is formed here using the distance of the barrier wall for isolation, so that a short circuit between the gate and the source / drain can be avoided. According to the purpose of the present invention, a method for automatically aligning metal comparators is provided, which includes: firstly defining and forming a gate region on a silicon substrate, then forming a dielectric layer on the scent region, and then on both sides of the gate region A lightly doped drain region is formed inside the silicon substrate. Next, a gap 嬖 'is formed on both sides of the gate electrode, and a source / drain region is formed inside the silicon substrate on both sides of the gap wall, and then an oxide layer is deposited on the source / drain region and the dielectric layer. Then, the oxide layer is removed until the dielectric layer is removed, and then the dielectric layer is removed. Finally, a metal silicide is formed at the position where the dielectric rhenium is removed. 5 This paper size applies to China's National Standards (CNS) A4 specification {210X297 mm) I clothing --- order --- r (Please read the precautions on the back before filling this page) 2808twf. doc / 005 A7 4 6 66 1 3 B7 V. Description of the Invention (Lf) In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy to understand, a preferred embodiment is given below, in conjunction with the accompanying drawings The detailed description is as follows: A brief description of the drawings: Figures 1A to 1D show the conventional manufacturing method of self-aligned metal silicide; and Figures 2A to 2E show a method according to a preferred embodiment of the present invention. Automatic alignment pattern of metal silicide manufacturing method. ^ Brief description of the numbers: 1, 11: political substrate 2, 12: smell electrode 3, 14: lightly doped drain region 4, 15: spacer wall 5, 16: source / drain electrode 6, 18: titanium silicide 8, 17: Oxidation layer 13: Dielectric layer embodiment Please refer to FIGS. 2A to 2E for a diagram of a method for manufacturing an automatic alignment metal silicide according to a preferred embodiment of the present invention. First, in FIG. 2A, a silicon substrate 11 is provided, and then a gate region 12 is defined and formed, wherein the gate portion is made of, for example, polycrystalline silicon. Then, a dielectric layer 13 is formed on the gate region 12, and the dielectric layer 13 is made of, for example, silicon nitride. Finally, inside the silicon substrate on both sides of the gate region,
Jii I -I I ϋ^— - - = I J - - I I - n^i ml n — (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 A7 經來部屮次樣卑局負T,消先合竹社印衆 ____ B7 五、發明説明（7) 低濃度離子植入，形成輕摻雜汲極區14。 接著，請參考第2B圖，於矽基底上之該閘極兩側， 形成一間隙壁15。然後，於間隙壁兩側之矽基底內部，進 行高濃度離子植入，形成源/汲極區16。接著，在第2C圖 中，在源/汲極區16與介電層13上，沈積形成一氧化層17， 其中沈積之氧化層，例如使用高密度電漿化學氣相沈積， 在鬧極部分會產生削角現象。 接著，在第2D圖中，使用化學機械研@法，去除氧 化層直到介電層中爲止。最後在第2E圖中，去除介電層， 例如使用一磷酸蝕刻。然後在去除之介電層的位置上，形 成一金屬矽化物，例如使用快速加熱製程將鈦金屬與多晶 矽，在高溫下產生矽化鈦。 由上述的步驟中，以本發明的自動對準金屬矽化物之 方法，不需要經微影過程，只要先在多晶矽之閘極上， 形成一介電層，在最後將介電層去除，然後塡入鈦金屬’ 就可以不經微影過程，在閘極上得到低電阻値之金屬矽 化物(TiSi2)，並且避免多晶矽化金屬（Polycide)中’使用埋 入通道之PMOS電晶體’會造成記憶體誤判動作情形’而 以本發明之自動對準金屬矽化物中’使用表面通道之PMOS 電晶體，所以不會有上述情形發生。 此外，本發明的自動對準金屬矽化物之方法，在源/汲 極上沒有形成金屬矽化物(TiSi2) ’所以對於接面漏電流產 生情形可以大幅降低’並且事先在閘極上形成介電層，最 後再去除該介電層後’然後在此處形成金屬砂化物，利用 7 -i ---I *^1 n - - » tn - n n n —— T (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4 6 6s68^w3· doc/〇〇5 A7 B7 五、發明説明（έ ) 間隙壁之距離作隔離，所以更能避免閘極與源/汲極產生短 路情況。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 經淖部中戎#卑局貝J消合作=fl印家 本紙張尺度適用中國國家標率{ CNS) A4規格{ 210X297公楚）Jii I -II ϋ ^ —--= IJ--II-n ^ i ml n — (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) ) A7 A7 The negative and negative results of the Ministry of Foreign Affairs are negative T, eliminate the joint of the Bamboo Society and India ____ B7 V. Description of the invention (7) Low concentration ion implantation, forming a lightly doped drain region 14 Next, referring to FIG. 2B, a gap 15 is formed on both sides of the gate on the silicon substrate. Then, a high concentration ion implantation is performed inside the silicon substrate on both sides of the gap wall to form a source / drain region 16. Next, in FIG. 2C, an oxide layer 17 is deposited on the source / drain region 16 and the dielectric layer 13, and the deposited oxide layer is, for example, a high-density plasma chemical vapor deposition. Beveled. Next, in FIG. 2D, the chemical mechanical research method is used to remove the oxide layer until it is in the dielectric layer. Finally, in FIG. 2E, the dielectric layer is removed, for example, using a phosphoric acid etch. Then, a metal silicide is formed at the position of the removed dielectric layer. For example, titanium metal and polycrystalline silicon are formed using a rapid heating process to generate titanium silicide at a high temperature. From the above steps, the method for automatically aligning metal silicide of the present invention does not need to go through a lithography process, as long as a dielectric layer is formed on the gate of polycrystalline silicon, the dielectric layer is removed at the end, and then By inserting titanium metal, low-resistance plutonium metal silicide (TiSi2) can be obtained on the gate without lithographic process, and the use of a PMOS transistor with a buried channel in the polycide is avoided. Misjudging the operation situation 'and using the automatic alignment metal silicide of the present invention' uses a PMOS transistor with a surface channel, so the above situation does not occur. In addition, in the method for automatically aligning metal silicide of the present invention, no metal silicide (TiSi2) is formed on the source / drain electrode, so the occurrence of junction leakage current can be greatly reduced, and a dielectric layer is formed on the gate in advance. Finally, after removing the dielectric layer ', then a metal sand is formed here, using 7 -i --- I * ^ 1 n--»tn-nnn —— T (Please read the precautions on the back before filling in this Page) This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 mm) 4 6 6s68 ^ w3 · doc / 〇〇5 A7 B7 V. Description of the invention (Stroke) The distance between the partition walls is isolated, so it can be avoided more The gate is shorted to the source / drain. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page.) Binding. Order Warranty Department Zhongrong # 贝 局 贝 J 消 合作 = fl 印 家 This paper size applies to China's national standard {CNS) A4 specifications {210X297 Gongchu)