經濟部中央梂準局負工消费合作社印装 4470 1 7 at B7 五、發明説明（） 發明領域： 本發明係有關於一種半導體元件之製造方法，特別 是有關於一種具有凹陷之自行對準的金屬矽化物接點及 延伸源没極接面（extended source/drain junctions)之金氧 半場效電晶艘（Metal Oxide Semiconductor Field Effect Transistor; MOSFET)的製造方法 * 發明背棄： 自從第一個積體電路於西元1960年首先發明以來， 半導體製程中單一晶片上的元件數目，即以爆炸性的速 度快速成長，隨著現階段的半導艘製程技術已邁入超大 型積艘電路（ultra Urge scale integration; ULSI)、甚至更 高密度的時代，單一晶片上的元件數目也由以往的數千 個元件，增加至數百萬個元件，甚至可達到單一晶片上 製作數千萬個或是更多個元件的程度。 單一晶片上元件數目的大幅增加，形成對半導艘製 程技術的一大挑戰’每一個半導艘元件皆必須在不彩審 其功能的前提下，進一步縮減其尺寸或占用的面積，而 在更高的積集度（packing density)之下，整體元件或電路 之功能仍須維持不變、甚至必須具有更好的可靠度、工 作壽命、並同時加入低功率消耗及低發熱率的特性。因 此半導體製程中的製程技術，諸如微彩、蝕刻、沈積、 離子佈植等等的主要製程技術，必須同時的研究與發 本紙法尺度遍用中國®家揉準《CNS > A4祝格（210X297公釐） ---------Μ------IT------it (請先鬩讀背面之注意事項再填寫本頁) 4470 A7 B7 經濟部中央樣準局貝工消費合作社印裝 五、發明説明（ 展’以達成下一代積體電路的發展目標。 在—般的積趙電路中，最常被應用的元件之一即是 具有控制特性的電晶體，尤其是所謂的金氧半場效電晶 體（MOSFET)，隨著元件尺寸的日益縮減，次微来尺寸的 金氧半场效電晶體同時面臨更多的挑戰。當積體電路令 每一個金氧半場效電晶體所占的長度舆寬度縮小時，電 晶體的通道長度亦隨之縮減，而導致如墜穿效應、洩漏 電流、接觸電阻等問題的加重，因而降低了半導體製程 的良率及元件的可靠度。 為了發展来來高速度的超大型積想電路（ULSI)、未 來的金氧半場效電晶體’必須使用如自行對準矽化金屬 接觸、以及極液的延伸源沒極接面（extende(j ultrashallow s〇Urce/drain juncti〇n)等技術 ，以 提供更 為提昇 的元件特性》在超大型積體電路（ULSI)或是大型積體電 路（VLSI)的電晶體元件中，自行對準的矽化金屬技術， 是用以提昇微米尺寸元件操作速度的關鍵，但相對來 說’使用自行對準的矽化金屬技術也必須面臨許多的挑 戰* 一般而言，自行對準矽化金屬的技術會導致金屬入 侵半導艘基材的現象，而產生接面處洩漏電流的問題； 而於自行對準矽化金屬的過程中，往往會有未完全去除 的金屬層殘餘於閘極兩側的第一間隙壁上，而導致鄰近 區域間橋接（bridging)或短路（short)等的效應。有關使用 自行對準矽化金屬的技術上負面的效應，可參考C.Y. Lu -··--—— ._3_ 本紙張又度逋用中®國家梂準（CNS ) A4祝格（2HT〆297公釐） ^------1T------^ (請先閲讀背面之注r事項再填寫本頁) 4470 1 7 A7 B7_ 五、發明説明（） 等人所發表的研究結果 （“Process Limitation and Device Design Tradeoffs of Self-Aligned TiSi2 Junction Formation in Submicrometer CMOS Devices,,; IEEE Trans. Electron Devices, vol. ED-38, No. 2，1991)，其中提出在 應用自行對準矽化金屬技術與淺接面技術兩者間，在設 計上所需面臨的取捨。 在目前的製程技術之中，自行對準的矽化金屬已應 用於次微米以下的元件中，以增加積體電路的積集度， 並減少内部連接時的電阻，改進其操作速度。上述技術 之相關文獻之一，可參閱由 K. Fujii等人所發表之’’A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM”（ 1 996, IEEE，IEDM 96-45 1)，在此 文獻中，發現自行對準的矽化金屬製程中，若使用鎢原 子佔原子百分率約5 %的Ti W合金作為金屬材料，則對於 閘極t度為0.18徽米的元件而言，於熱回火溫度高達攝 氏800度時，片電阻仍相當低。 至於因為元件尺寸變得越來越小所導致的「短通道 效應」（short channel effect)，可以藉著形成一極淺的延 伸源汲極接面（extended ultra-shallow source/drain junctions)’而得到改善，有關此部分技術之相關文獻， 可參閱由A. Ho ri等人所提出之” A 0.05 μιη-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5Kev Ion Implantation and Rapid Thermal Annealing” (1994, IEEE, IEDM 94-485) » 本紙ft尺度逋用中國國家榇率（CNS ) A4il格（210X297公釐） ---------1------ir------^ (請先閱讀背面之;i意事項再填寫本頁) 經濟部中央標準局具工消费合作社印製 經濟部中央橾準局負工消费合作杜印製 447〇17 A7 _______B7 五、發明説明（） 發明目的及概述： 本發明的主要目的為提供一種形成電晶饉之方法。 本發明的另一目的為提供一種形成金氧半場效電晶 體（MOSFETs)的製造方法，以形成具有凹陷之自行對準的 矽化金屬接點及延伸源汲極接面。 本發明的再一目的為提供一種之金氧半場效電晶體 (MOSFETs)的製造方法’以提昇電晶體的操作速度，並改 善次微米及更小尺寸元件中短通道效應的問題。 本發明中形成具有凹陷之自行對準的金屬矽化物接 點及延伸涿汲極接面之金氣半場效電晶體的方法，可包 含以下步驟：首先形成隔離區域於基材之上；並形成閘 極絕緣層於基材上；再形成第一導體層於閘極絕緣層 上；接著形成第一介電層於第一導體層上：並去除部分 之第一介電層，第一導體層、及閘極絕緣層’以定義閘 極結構；然後形成第一熱氡化層於基材上及第一導體層 之側壁上：再形成第一間陈壁於閘極結構之側壁上；接 著去除未被第一間隙壁復蓋之第一熱氡化層：之後形成 第二熱氧化層於基材之曝露區域之上；旅去除第一介電 層及第一間隊壁；再進行離子植入以形成延伸源汲極接 面、於基材内第—熱氧化層下方之區域處；然後形成第 二間隙壁於閘極結構之側壁上；並去除第二熱氧化層以 形成凹陷區域於基材表面上；接著形成第一金屬層於基 材上；再進行源極/汲極/閘極之離子植入，·之後進行熱製 程，以將位於凹陷區域及第一導效層上方之第一金屬層 本紙張又度逋用中围國家橾準（CNS ) A4現格（210X297公釐） ----------t------tr------線 (請先聞讀背面之注k意事項再填寫本頁) 44^0 J 7 A7 B7 經濟部中央標準局貝工消费合作社印製 五、發明说明（） 反 應 為 矽 化 金 屬 層 I 並 去 除 此 之 外 T 並 可 進 一 一 層 以 上 的 元 件 間 連 線 結 之 部 分 去 除 之 後 J 形 成 一 材 進 行 — 回 火 製 程 t 並 去 觸 洞 於 其 内 t 之 後 形 成 第 電 層 上 » 最 後 去 除 部 分 之 圈 式 簡 單 說 明 * 第 圖 顯 示 本 發 明 中 形 之 裁 面 示 意 圖 〇 第 二 圊 顯 示 本 發 明 中 形 以 及 第 — 介 電 層 構 之 裁 面 示 意 圖 第 二 圖 顯 示 本 發 明 中 形 一 導 體 層 之 側 壁 第 四 圄 顯 示 本 發 明 中 形 壁 上 並 去 除 未 化 層 之 裁 面 示 意 第 五 圖 顯 示 本 發 明 中 形 區 域 之 上 的 截 面 第 六 圖 顯 示 本 發 明 中 去 再 進 行 離 子 植 入 内 第 一 熱 氧 化 層 除第一金屬層未反應之部分。 步加入後續製程，以形成至少 構，首先於第一金屬層未反應 第二介電層於基材上；再對基 除部分之第二介電層以形成接 二金屬層於接觸洞内及第二介 第二金屬層以定義内連線。 成隔離區域於半導體基材之上 成閘極絕緣層、第一導體層、 ，並去除其部分以定義閘極結 〇 成第一熱氧化層於基材上及第 上之截面示意圖。 成第一間隙壁於閘極結構之側 被第一間隙壁覆蓋之第一熱氧 圊。 成第二熱氧化層於基材之曝露 示意圖。 除第一介電層及第一間隙壁、 以形成延伸源汲極接面於基材 下方之區域處的截面示意圖。 6 本紙浪尺度逋用中國國家標準（CNS ) A4規洛（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 線 4 4 70^7 A7 B7 經濟部中央揉準局貝工消費合作社印家 五、發明説明（） 第七圖顯示本發明中形成第二間陈壁、去除第二熱氡 化層、形成第一金屬層、並進行源極及極/閘極 之離子植入之截面示意圖。 第八圖顯示本發明中進行矽化金屬反應後之截面示意 圖。 第九圖顯示本發明中定義内連線於第二介電層内之載 面示意圖。 發明詳細說明： 本發明提供一種具有凹陷之自行對準的矽化金屬接 點及延伸源汲極接面之金氧半場效電晶艘（M0SFETs)的 製造方法，藉由矽化金屬接點的應用，配合具矽化金屬 接點的閘極*可使電晶艎的操作速度進一步提昇：而延 伸源及極接面的結構，可改善傳統結構中短通道效應的 問題；而以本發明中之方法所形成之元件，可進一步應 用於更高積集度的製程之中，以增加元件的密度及效 能》 在不限制本發明的精神及應用範圍下，以下即以一 半導體製程中，形成一 N通道之金氧半場效電晶艘 (NMOS)的製程為例，介紹本發明之實施，而熟悉此領域 技藝者，可利相近之方法，以形成一P通道之金軋半場 效電晶體（PMOS)，其變化之細節即不做赘述。參見第一 圖所示，首先提供一半導艘基材2,半導想基材2可為一 矽材質、晶向為<100>之半導體基材，並形成一氧化矽層 本紙張尺J免逋用中國國家橾準（CNS ) A4規格（210X 297公釐） ---------^------1T------漆 (請先閱讀背面之注意事項再填寫本頁) 4470 1 7 A7 B7 五、發明説明（） 4於半導體基材2上，如圖中所示，氡化矽層4係於一含 氧環境中’由半導體基材2加熱氧化成長而成；之後形 成一氤化矽層6於氧化矽層4上，以本實施例而言’氣 化矽層6之形成可使用沈積方式達成’例如使用化學氣 相沈積法等。 接著可利用微影及蝕刻製程以去除部分的氣化碎層 6及氧化矽層4，以定義所需形成隔離區域的範圍，再接 著形成隔離區域，如圖中所示的場氧化區（field oxide region; FOX)8，以提供基材2上各元件間的所需隔離作 用。 經濟部令夬橾準局貝工消费合作社印製 (請先閱讀背面之注意事項再填寫本頁) 參見第二圖所示，接著利用溼蝕刻法去除二氧化碎 層4及氮化矽層6，再形成閘極絕緣層1〇於基材2上’ 本例中可利用熱氧化法形成二氧化矽層於基材2上’作 為閘極的氡化層。然後形成第一導體層12於基材2上 方、也就是閘極絕緣層10與場氡化區8上方’在較佳實 施例中，可利用低壓化學氣相沈積法（Low Pressure Chemical Vapor Deposition，LPCVD)形成摻雜的多晶梦 作為第一導體層12;接著即形成第一介電層14於第一導 體層12之上，本例中第一介電層14可使用氮化矽層’ 其可於後續的微影製程宁做為抗反射層之用，並可利用 化學氣相沈積方式加以形成：此外，第一介電層14亦可 使用氧化矽層，並利用化學氣相沈積方式加以形成° 在10,12及14三個不同膜層相4的結構形成之後’ 即可藉由微影及蝕刻製程的應用，蝕去部分之第一介電 本紙張尺度適用中圉國家梂準（CNS ) A4洗格（2丨0X297公釐） 秦 ^470 j 7 A7 ___^B7___ 五、發明説明（） (請先聞讀背面之注意事項再填寫本頁) 層14、第一導體層12、以及閘極絕緣層10，以定義出電 晶體之閘極結構1 6。依據本發明中較佳之實施例，第一 導體層12係為摻有雜質之多晶矽層、其厚度約為 到5 000埃（angstroms)之間，第一介電層14可為上述以 沈積方式形成的氮化矽層、或是利用四乙基矽酸鹽 (tetra-ethy丨-ortho-silicate; TEOS)作為反應氣艘所形成之 氧化矽層，其厚度約為100至1500埃之間。 參見第三圖所示，接著即分別形成第一熱氧化層18 及20於矽基材2的裸露區域上、以及第一導體層12之 側壁上，藉由第一熱氧化層1 8的形成’可恢復先前矽基 材2因蝕刻製程所造成的表面破壞或缺陷》依據本發明 之一較佳實施例，第一熱氧化層18及20可於N20或NO 的環境中，利用熱氧化製程，分別於矽基材2、以及第一 導體層12側面，藉由與矽的氧化反應而形成，而第一熱 氡化層18的厚度約為20到150埃之間；第一熱氧化層 20的厚度約為40到250埃之間。 經濟部中央橾準局貝工消费合作社印裂 參閱第四圈，之後形成第一間陈壁22於閘極結構16 的側壁上，以較佳實施例而言，第一問隙壁22可藉由沈 積並回蝕氮化矽層加以形成，其方法即是先沈積氮化矽 層於第一熱軋化層18及閘極結構16上*再以回蝕方式 去除部分之氮化矽層，即留下第一間隙壁22;在回蝕製 程中，未被第一間隙壁22所復蓋部分之第一熱氧化層18 亦會同時被去除。依據本發明之一實施例，氮化矽層之 厚度約為500至2000埃之間，而其沈積的方法可利用低 本紙張尺度適用中國國家標车（CMS ) A4祝格（2l〇X297公着） 經濟部中央揉準局負工消费合作社印製 447017 A7 B7_ 五、發明説明（) 壓化學氣相沈積法（Low Pressure Chemical Vapor Deposition; LPCVD)或電漿增強式化學氣相沈積法 (Plasma Enhanced Chemical Vapor Deposition; PECVD)等 方式。 參閱第五圊所示’之後即形成第二熱氧化層24於基 材2之曝露區域之上，本例中之第二熱軋化層24可利用 基材2曝露區域的熱氡化反應成長而成，其熱氧化製程 的溫度可約為7 5 01至11 0 01之間，在較佳實施例之中， 其成長的厚度約為300至2000埃之間· 參見第六圖所示’接著去除第一介電層及第一問 隙壁22,以使用氮化矽層做為第一介電層14及使用氮化 矽間隙壁的例子而言，第一介電層14及第一間陈壁22 可利用熱磷酸以溼蝕刻的方式加以去除*並接著去除第 二熱氧化層24’以形成凹陷區域於基材2的表面上。 然後進行離子楂入的製程，以形成延伸泺汲極接面 25、其係形成於基材2之内、第一熱氧化層18下方的區 域處：以形成N型金氧半場效電晶雔為例，可使用含砷 的離子或是含磷的離子；在較佳實施中，所使用的植入 能量約為0.5Kev至30KeV之間，以產生約為5E13至2E15 atoms/cm2之間的離子漢度。 參見第七圖所示’之後形成第二間味壁22a於閘極 結構1 6之側壁上’本例中之第二間隙壁22a可使用氮化 矽間隙壁或是氡化矽間隙壁，並同樣使用沈積及回蝕的 製程加以形成。 本紙張尺度逍用中國國家橾丰（CNS ) Μ規格（210 X 297公簸） ---------g------，玎------^ (請先閱讀背面之注意事項再填寫本頁) 鯉濟部中央梂準局—工消费合作社印装 4〇01 7 A7 -—_____B7 五、發明説明（） 捿著形成第一金屑層26於基材2上，如第七圖所 不’並進行源極/汲極/閘極之離子植入。以一般的製程應 而。’第一金屬屠26可為如欽、鎮、姑、銘、錄及路 等的材料，以於後續製程之中與矽反應形成矽化金屬 廣’本例中其厚度約為50至1 〇〇〇埃之間，其沈積方法 可應用為化學氣相沈積法（CVD)或是濺鍍等的物理氣相 沈積法（PVD) « 而源極/汲極/閘極區域的離子植入，以形成N型金氧 半場效電晶想為例，可使用含神的離子或是含破的離 子；在較佳實施中，所使用的植入能量約為1〇到12〇 KeV，以產生約為5E14至5E16 atoms/cm2之間的離子漢 度’形成凹陷區域下方的澉極與汲極區域27，並進一步 增加閘極結構1 6中多晶矽材料的摻雜濃度。 接著參見第八圈’進行以加熱製程將金屬藉由高溫 的反應而矽化的製程，以將部分的第一金屬層26經由舆 矽的反應形成矽化金屬層28，其中位於場氧化區域8 上、以及在氮化矽第二間隙壁22a上方與侧邊之第一金 屬層26，由於未與矽表面接觸，因此並不參與反應。 之後並去除未反應的殘餘第一金屬層26，以留下够· 化金屬28。依據本發明之一較佳實施例，矽化金屬形成 之熱製程所使用的溫度約為350到700 eC之間，在高沮製 程的作用之下，源極與汲極區域27内的離子會進一步擴 散及活化（activate) ’如第八圖所示；而殘餘第一金屬層 26之去除方法係為習知用以去除金屬的濕蝕刻法β 本紙伕尺度適用中國®家樑準（CNS ) A4祝格（210X297公釐） t------.玎------0 (請先閲讀背面之注意事項再填寫本頁) 44701 7 五、發明説明（ A7 B7 經濟部中央樣隼局貝工消费合作社印製 因此’藉由上谈 延之製程，即可形成如圖中所示的， 具有凹陷之自行對茧认^ 接面的金氣丰诺 的矽化金屬接點、以及延伸源汲極 接面的金氧+場效電晶難。 除了上述的製葙 m s w ^ ^取程之外’可進一步加入一系列的後續 掣程，以形成一S、士 Λ 東S笛士 ®路- 或通常是多廣的元件間連線結構’ 參見第九圖所不，甘Α 无形成第二介電層32於基材2之 上，本例中可利用仆尊s i .^ a _ b學氣相沈積法沈積氧化矽層做為第 二介電層32»並垃^ 铁著進行回火製程，以使氧化矽層32 的材料變得較為密竇,β „ :礼 ^ J2 貫，提昇其隔絕特性，並使矽化金屬 層28經由回火的虛 ** ,^ ^ 恿理進入較為穩定的狀態丨接著去除部 分之第二介電層3 2，w a * & Π ^ ^ ^ ^ * 以疋義接觸洞於其内’一般可使用 達成之。然後再形成第二金屬 ：— 層32、並填入於接觸洞内《最後可配合 微影製程及蝕刻製箱χ — 眾程的使用*除去部分之第二金屬層 34以疋義内連線a依據本發明之較佳實施例回火製 程的處理溫度約為7〇〇到95〇ΐ之間，而第二金屬層W 可為如鋁、銅、鈦、鎢、鈷、鉑、鎳及#等的材料β 因此’藉由本發明中之方法，可形成具有凹陷之自 行對準的矽化金屬接點、以及延伸源汲極接面的金氧半 場效電晶體，並提供良好的操作速度，同時抑制傳統製 程與元件所產生的短通道效應，而進一步提昇積體電路 的運作特性及元件積集度。 本發明僅以較佳實施例說明如上，並非用以限定本 發明之申請範圍；凡熟習該項技藝人士，在未脫離本發 12 本紙張尺度適用申囷國家標準（CNS ) Α4殊格（210X297公嫠} ----------徒-- f請先聞請背面之注意事項再填寫本頁} 訂 線 44701 A7 B7 五、發明説明（ 圍 範 護 保 利 專 其 飾 。 修内 或圍 變範 改利 許專 些請 作申 可之 當述 ，下 下在 神含 精包 之應 明均 ---------ά------IT------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部t央橾隼局員工消費合作社印袈 本紙張尺度適用中國國家標半（CNS > A4私格（210XW7公釐}Printed on 4470 1 7 at B7 by the Central Laboratories Bureau of the Ministry of Economic Affairs. V. INTRODUCTION TO THE INVENTION Field of the Invention: The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a self-aligning device having a recess. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) manufacturing method for metal silicide contacts and extended source / drain junctions * Invention defect: Since the first integrated body Since the circuit was first invented in 1960, the number of components on a single wafer in the semiconductor process has grown rapidly at an explosive rate. With the current stage of semi-conductor process technology, ultra-large scale integration circuits have been introduced. ULSI), and even higher density era, the number of components on a single chip has increased from thousands of components in the past to millions of components, and even tens of millions or more can be produced on a single chip The degree of the component. The large increase in the number of components on a single wafer has formed a major challenge to the semi-conductor process technology. 'Each semi-conductor component must further reduce its size or occupied area without prejudging its function. With a higher packing density, the function of the overall component or circuit must still remain the same, and it must even have better reliability, working life, and at the same time add characteristics of low power consumption and low heating rate. Therefore, the process technology in the semiconductor process, such as microcolor, etching, deposition, ion implantation, etc., must be studied and published at the same time. The paper method is widely used in China. "CNS > A4 Zhuge ( 210X297 mm) --------- M ------ IT ------ it (Please read the notes on the back before filling this page) 4470 A7 B7 Central Ministry of Economy Printed by the local co-operative consumer cooperative. 5. Description of the invention (exhibited to achieve the development goals of the next-generation integrated circuit. In the general product-zhao circuit, one of the most commonly used components is a transistor with control characteristics. , Especially the so-called metal-oxide-semiconductor field-effect transistor (MOSFET), with the shrinking of the element size, the second-smaller-size metal-oxide-semiconductor field-effect transistor faces more challenges at the same time. When the integrated circuit makes every gold When the width of the oxygen half field effect transistor is reduced, the channel length of the transistor is also reduced, causing problems such as the fall-through effect, leakage current, contact resistance, etc., thereby reducing the yield and Component reliability. Speed ultra-large-scale integrated circuit (ULSI), future metal-oxide-semiconductor half-effect transistor 'must use, for example, self-aligned metal silicide contacts, and extended source electrode junctions of polar fluid (extende (j ultrashallow s〇Urce / drain juncti〇n) and other technologies to provide improved device characteristics. "In the ultra large integrated circuit (ULSI) or large integrated circuit (VLSI) transistor components, self-aligned silicided metal technology is used The key to increasing the operating speed of micron-sized components, but relatively speaking, 'the use of self-aligned silicided metal technology must also face many challenges. * Generally speaking, self-aligned metal silicide technology will cause metal to invade the semi-conductor substrate And the problem of leakage current at the interface; in the process of self-aligning the silicide metal, the metal layer that is not completely removed often remains on the first gap on both sides of the gate, resulting in the adjacent area Effects such as bridging or shorting. For technical negative effects of using self-aligned silicide metal, please refer to CY Lu-·· --—— ._3_ This Zhang Youdu (Chinese National Standard) (CNS) A4 (2HT〆297mm) ^ ------ 1T ------ ^ (Please read the note r on the back before filling in this Page) 4470 1 7 A7 B7_ 5. Research results published by Inventor () and others ("Process Limitation and Device Design Tradeoffs of Self-Aligned TiSi2 Junction Formation in Submicrometer CMOS Devices ,,; IEEE Trans. Electron Devices, vol. ED-38, No. 2, 1991), which proposes the trade-offs in design between the application of self-aligned metal silicide technology and shallow junction technology. In the current process technology, self-aligned silicided metal has been applied to sub-micron components to increase the integration of integrated circuits, reduce the resistance during internal connection, and improve its operating speed. For one of the related literatures on the above technologies, please refer to "A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM" (1 996, IEEE, IEDM 96-45 1) published by K. Fujii et al., In this document, it was found that in the self-aligned silicidation metal process, if a Ti W alloy with tungsten atoms accounting for about 5% of the atomic percentage is used as the metal material, for components with a gate t of 0.18 micrometers, the thermal When the tempering temperature is as high as 800 degrees Celsius, the sheet resistance is still quite low. As for the "short channel effect" caused by the smaller and smaller component sizes, it can be drawn by forming a very shallow extension source. Pole junctions (extended ultra-shallow source / drain junctions') have been improved. For related literature on this part of technology, please refer to "A. Hori et al." A 0.05 μηη-CMOS with Ultra Shallow Source / Drain Junctions Fabricated by 5Kev Ion Implantation and Rapid Thermal Annealing "(1994, IEEE, IEDM 94-485)» This paper ft scale uses China's national rate (CNS) A4il grid (210X297 mm) ------- --1 ------ ir ------ ^ (Please read the back of the page first; i-notes before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs Industrial and consumer cooperation Du printed 447〇17 A7 _______B7 V. Description of the invention () Purpose and summary of the invention: The main purpose of the present invention is to provide a method for forming an electric crystal. Another object of the present invention is to provide a manufacturing method for forming metal-oxide-semiconductor field-effect transistors (MOSFETs) to form self-aligned silicided metal contacts with recesses and extended source drain contacts. Yet another object of the present invention is to provide a method for manufacturing metal-oxide-semiconductor field-effect transistors (MOSFETs) to increase the operating speed of the transistors and improve the problem of short channel effects in sub-micron and smaller-sized devices. The method for forming a self-aligned metal silicide contact with a recess and a gold gas half-field-effect transistor extending the drain-drain junction in the present invention may include the following steps: first forming an isolation region on a substrate; and forming The gate insulating layer is on the substrate; then a first conductor layer is formed on the gate insulating layer; then a first dielectric layer is formed on the first conductor layer: and part of the first dielectric layer and the first conductor layer are removed And gate insulation layer 'to define the gate structure; then form a first thermally-cured layer on the substrate and the side wall of the first conductor layer: and then form a first old wall on the side wall of the gate structure; then Removal of the first thermally oxidized layer not covered by the first gap wall: forming a second thermal oxide layer on the exposed area of the substrate; removing the first dielectric layer and the first interlayer wall; and performing ionization Implanted to form an extended source drain junction at the area under the first thermal oxide layer in the substrate; then a second gap wall is formed on the sidewall of the gate structure; and the second thermal oxide layer is removed to form a recessed area On the surface of the substrate; then forming the first gold The metal layer is on the substrate; then source / drain / gate ion implantation is performed, and then a thermal process is performed to restore the first metal layer of the paper above the first conductive layer and the recessed area. Use Zhongwei National Standard (CNS) A4 (210X297 mm) ---------- t ------ tr ------ line (please read the note on the back first) (please fill in this page if necessary)) 44 ^ 0 J 7 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () The reaction is silicidated metal layer I and other T can be entered and more than one layer can be entered. After the part of the connection between the components is removed, J is formed into a single material—the tempering process t and the hole is formed in t. The electrical layer is formed »A brief description of the ring type of the last removed part * The figure shows the shape of the invention Schematic diagram of the cut surface. The second figure shows the schematic diagram of the medium and the first layer of the dielectric layer structure of the present invention. Figure 4 shows the cut surface on the shaped wall of the present invention and the unchemicalized layer is removed. Figure 5 shows the cross section above the shaped area of the present invention. Figure 6 shows the first thermal oxidation layer in the present invention for ion implantation. Except the unreacted part of the first metal layer. A subsequent process is added step by step to form at least a structure. First, a second dielectric layer is not reacted on the substrate on the first metal layer; and then a second dielectric layer is formed on the substrate to form a second metal layer in the contact hole and A second metal layer is defined by a second metal layer. An isolation region is formed on the semiconductor substrate. A gate insulation layer, a first conductor layer, and a portion thereof are removed to define a gate junction. A first thermal oxidation layer is formed on the substrate and a cross-sectional schematic diagram on the substrate. A first thermal barrier is formed on the side of the gate structure and is covered by the first thermal barrier. Schematic illustration of the exposure of the second thermal oxidation layer to the substrate. A schematic cross-sectional view of the first dielectric layer and the first spacer to form an extended source-drain junction area under the substrate. 6 This paper uses the Chinese National Standard (CNS) A4 gauge (210X297 mm) (Please read the precautions on the back before filling out this page) Line 4 4 70 ^ 7 A7 B7 Consumption Cooperative, India 5. Explanation of the Invention (7) The figure 7 shows the formation of a second sintered wall, the removal of the second thermally induced layer, the formation of the first metal layer, and the ion implantation of the source and gate / gate electrodes in the present invention. Into the schematic cross-section. The eighth diagram is a schematic cross-sectional view of a metal silicide reaction in the present invention. The ninth figure is a schematic diagram of a carrier surface defined in the present invention as being interconnected in the second dielectric layer. Detailed description of the invention: The present invention provides a method for manufacturing self-aligned silicided metal contacts with recesses and extended source-drain junction metal oxide semiconductor field-effect transistors (MOSFETs). With the application of silicided metal contacts, In conjunction with a gate electrode with silicided metal contacts *, the operating speed of the transistor can be further improved: the structure of the extended source and the electrode interface can improve the problem of short channel effects in the traditional structure; The formed element can be further applied to processes with higher accumulation to increase the density and efficiency of the element. "Without limiting the spirit and scope of the present invention, the following will form an N channel in a semiconductor process The metal-oxygen half-field-effect transistor (NMOS) process is taken as an example to introduce the implementation of the present invention. Those skilled in the art can use similar methods to form a P-channel gold-rolled half-field-effect transistor (PMOS). The details of the changes will not be repeated here. As shown in the first figure, firstly, a half guide substrate 2 is provided. The semiconducting substrate 2 may be a silicon substrate with a crystal orientation of < 100 >, and a silicon oxide layer is formed. Free from China National Standard (CNS) A4 specification (210X 297 mm) --------- ^ ------ 1T ------ Paint (Please read the precautions on the back first (Fill in this page again) 4470 1 7 A7 B7 V. Description of the invention (4) On the semiconductor substrate 2, as shown in the figure, the tritiated silicon layer 4 is in an oxygen-containing environment 'heated and oxidized by the semiconductor substrate 2 After being grown, a siliconized silicon layer 6 is formed on the silicon oxide layer 4. According to this embodiment, 'the formation of the vaporized silicon layer 6 can be achieved using a deposition method', such as using a chemical vapor deposition method. Then, a lithography and etching process can be used to remove a part of the gasification debris layer 6 and the silicon oxide layer 4 to define the range of the isolation region to be formed, and then an isolation region is formed, as shown in the field oxide region (field) oxide region; FOX) 8 to provide the required isolation between components on the substrate 2. Printed by the Order Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative (please read the precautions on the back before filling this page) See the second figure, and then use wet etching to remove the shards of silicon dioxide 4 and silicon nitride 6 Then, a gate insulating layer 10 is formed on the substrate 2 'in this example, a silicon dioxide layer can be formed on the substrate 2 by using a thermal oxidation method' as a gated layer. Then, a first conductor layer 12 is formed over the substrate 2, that is, above the gate insulating layer 10 and the field polarization region 8. In a preferred embodiment, a low pressure chemical vapor deposition method (Low Pressure Chemical Vapor Deposition, LPCVD) to form a doped polycrystalline dream as the first conductor layer 12; then a first dielectric layer 14 is formed on the first conductor layer 12. In this example, a silicon nitride layer can be used as the first dielectric layer 14 ' It can be used as an anti-reflection layer in subsequent lithography processes, and can be formed by chemical vapor deposition: In addition, the first dielectric layer 14 can also be a silicon oxide layer, and can be formed by chemical vapor deposition. Forming ° After the formation of the structure of three different film layers and phases 4 of 10, 12, and 14 ', part of the first dielectric can be etched by the application of photolithography and etching processes. (CNS) A4 wash grid (2 丨 0X297 mm) Qin ^ 470 j 7 A7 ___ ^ B7___ 5. Description of the invention () (Please read the precautions on the back before filling this page) Layer 14, First Conductor Layer 12 And a gate insulating layer 10 to define the gate structure 16 of the transistor. According to a preferred embodiment of the present invention, the first conductor layer 12 is a polycrystalline silicon layer doped with impurities, and its thickness is between about 5,000 angstroms. The first dielectric layer 14 may be formed by the deposition method described above. The thickness of the silicon nitride layer is about 100 to 1500 angstroms, or the silicon oxide layer formed using tetra-ethy 丨 -ortho-silicate (TEOS) as a reaction gas vessel. Referring to the third figure, first thermal oxide layers 18 and 20 are respectively formed on the exposed area of the silicon substrate 2 and the sidewalls of the first conductor layer 12 by the formation of the first thermal oxide layer 18 "Restoring the previous surface damage or defect of the silicon substrate 2 caused by the etching process" According to a preferred embodiment of the present invention, the first thermal oxidation layers 18 and 20 can be used in the environment of N20 or NO, using the thermal oxidation process Are formed on the silicon substrate 2 and the side of the first conductor layer 12 by oxidation reaction with silicon, and the thickness of the first thermally-annealed layer 18 is about 20 to 150 angstroms; The thickness of 20 is between about 40 and 250 Angstroms. The print of the shellfish consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs refers to the fourth circle, and then a first Chen wall 22 is formed on the side wall of the gate structure 16. In a preferred embodiment, the first gap wall 22 can be borrowed It is formed by depositing and etching back a silicon nitride layer. The method is to first deposit a silicon nitride layer on the first hot-rolled layer 18 and the gate structure 16 * and then remove a part of the silicon nitride layer by etchback. That is, the first spacer wall 22 is left; in the etch-back process, the first thermal oxide layer 18 that is not covered by the first spacer wall 22 is also removed at the same time. According to an embodiment of the present invention, the thickness of the silicon nitride layer is between about 500 and 2000 angstroms, and the method of depositing the silicon nitride layer can be adapted to the Chinese National Standard Vehicle (CMS) A4 Zhuge (21 × 297 mm) using a low paper size. (Author) Printed by 447017 A7 B7_, Cooperative Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs. 5. Description of the invention () Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (Plasma Enhanced Chemical Vapor Deposition; PECVD). After referring to the fifth illustration, a second thermal oxide layer 24 is formed on the exposed area of the substrate 2. The second hot rolled layer 24 in this example can be grown by using the thermal annealing reaction of the exposed area of the substrate 2. The temperature of the thermal oxidation process can be between about 7 50 01 and 11 0 01. In a preferred embodiment, the thickness of the grown layer is about 300 to 2000 Angstroms. See the sixth figure. ' Next, the first dielectric layer and the first interstitial wall 22 are removed. Taking the example of using the silicon nitride layer as the first dielectric layer 14 and the example of using the silicon nitride spacer, the first dielectric layer 14 and the first The intermediate wall 22 can be removed by wet etching using thermal phosphoric acid *, and then the second thermal oxide layer 24 'is removed to form a recessed area on the surface of the substrate 2. Then, the ion halide process is performed to form an extended 泺 -drain junction 25 formed in the region of the substrate 2 and below the first thermal oxidation layer 18: to form an N-type metal-oxide half-field-effect transistor 效As an example, ions containing arsenic or ions containing phosphorus can be used; in a preferred implementation, the implantation energy used is between about 0.5 Kev to 30 KeV to generate about 5E13 to 2E15 atoms / cm2 Ionity. Referring to the seventh figure, 'the second odorant wall 22a is then formed on the side wall of the gate structure 16'. The second spacer 22a in this example may be a silicon nitride spacer or a silicon nitride spacer, and It is also formed using deposition and etch-back processes. The size of this paper is in accordance with China National Standards (CNS) M specifications (210 X 297 male dust) --------- g ------, 玎 ------ ^ (Please read first Note on the back, please fill in this page again) Printed by the Central Bureau of Standards of the Ministry of Civil Affairs and Industry and Consumer Cooperatives 4001 7 A7-_____B7 V. Description of the invention () The first gold chip layer 26 was formed on the substrate 2 As shown in the seventh figure, source / drain / gate ion implantation is performed. It responds to the general process. 'The first metal slaughter 26 can be materials such as Qin, Zhen, Gu, Ming, Lu and Road, etc., to react with silicon to form silicided metal in subsequent processes.' In this example, its thickness is about 50 to 100. Between 0 angstroms, the deposition method can be applied as a chemical vapor deposition (CVD) method or a physical vapor deposition method (PVD) such as sputtering «and ion implantation in the source / drain / gate regions The formation of an N-type metal-oxygen half field effect transistor is taken as an example. God-containing ions or ions containing ions can be used. In a preferred implementation, the implantation energy used is about 10 to 120 KeV to produce about To form the ion density between 5E14 and 5E16 atoms / cm2, the ytterbium and drain regions 27 below the recessed region are formed, and the doping concentration of the polycrystalline silicon material in the gate structure 16 is further increased. Next, referring to the eighth circle, a process of silicifying the metal by a high-temperature reaction in a heating process is performed to form a part of the first metal layer 26 through a reaction of silicon to form a silicided metal layer 28, which is located on the field oxidation region 8, And the first metal layer 26 above and to the side of the second silicon nitride spacer 22a does not contact the silicon surface, and therefore does not participate in the reaction. After that, the unreacted residual first metal layer 26 is removed to leave enough metal 28. According to a preferred embodiment of the present invention, the temperature used in the thermal process for forming silicided metal is about 350 to 700 eC. Under the action of the high temperature process, the ions in the source and drain regions 27 will further Diffusion and activation (shown in Fig. 8); and the method of removing the remaining first metal layer 26 is a conventional wet etching method for removing metal. The standard of this paper is China® Jialiang Standard (CNS) A4. Zhuge (210X297mm) t ------. 玎 ------ 0 (Please read the notes on the back before filling this page) 44701 7 V. Description of the invention (A7 B7 Central sample of the Ministry of Economic Affairs) Printed by the local shellfish consumer co-operative so that through the above-mentioned extension process, the self-identifying cocoon with a recessed jinfengfeng silicified metal contact as shown in the figure can be formed, and the extension The metal-oxide + field-effect transistor at the source-drain junction is difficult. In addition to the above-mentioned manufacturing process of msw ^ ^, a series of subsequent steps can be added to form an S, Shi Λ East S Flute® Circuit-or how wide is the connection structure between the components'. See Figure 9 for details. The dielectric layer 32 is on the substrate 2. In this example, a silicon oxide layer can be deposited as a second dielectric layer 32 using a vapor deposition method. Process to make the material of the silicon oxide layer 32 more dense sinus, β „: Li ^ J2, improve its isolation characteristics, and make the silicided metal layer 28 through the tempered virtual **, ^ ^ eggs into a more stable The state 丨 then remove part of the second dielectric layer 3 2, wa * & Π ^ ^ ^ ^ * * in the meaning of a contact hole in it 'usually can be achieved. Then form a second metal:-layer 32 And filled in the contact hole "Finally, it can be used with the lithography process and the etching box χ — the use of many processes * the part of the second metal layer 34 is removed, and the meaning is interconnected a according to the preferred embodiment of the present invention. The processing temperature of the fire process is about 700 to 95 ° F., and the second metal layer W may be a material β such as aluminum, copper, titanium, tungsten, cobalt, platinum, nickel, and #. Therefore, by the present invention, Method to form a self-aligned silicided metal contact with a recess and a metal-oxide half-field-effect transistor extending the source-drain interface. It also provides good operating speed, while suppressing the short-channel effect produced by traditional processes and components, and further improves the operating characteristics and component accumulation of integrated circuits. The present invention is described above only with a preferred embodiment, and is not intended to limit it. The scope of application of the present invention; those who are familiar with this skill can apply the national standard (CNS) Α4 special standard (210X297) for the paper size of this paper without departing from this issue. -f Please read the notes on the back before filling out this page} Order 44701 A7 B7 V. Description of the invention The internal or external change should be changed to apply for the statement of Shen Ke, and the following should be explained in the inclusive package of God --------- ά ------ IT --- --- ^ (Please read the notes on the back before filling this page) The printed paper size of the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs is applicable to the Chinese National Standard Half (CNS > A4Private (210XW7mm)