495852 A7 B7 五、發明説明（） ^495852 A7 B7 V. Description of the invention () ^
發明領域Z (請先閱讀背面之注意事項再填寫本頁) 本發明係有關於一種半導體元件之製造方法，特別 是有關於一種具有凹陷之自行對準的金屬矽化物接點及 延伸源沒極接面（extended source/drain junctions)之金氧 半場效電晶體（Metal Oxide Semiconductor Field Effect Transistor; MOSFET)的製造方法。 發明背景： 自從第一個積體電路於西元1960年首先發明以來， 半導體製程中單一晶片上的元件數目，即以爆炸性的速 度快速成長，隨著現階段的半導體製程技術已邁入超大 型積體電路（ultra large scale integration; ULSI)、甚至更 高密度的時代，單一晶片上的元件數目也由以往的數千 個元件，增加至數百萬個元件，甚至可達到單一晶片上 製作數千萬個或是更多個元件的程度。 經濟部中央標準局員工消費合作社印製 單一晶片上元件數目的大幅增加，形成對半導體製 程技術的一大挑戰，每一個半導體元件皆必須在不影響 其功能的前提下，進一步縮減其尺寸或占用的面積，而 在更高的積集度（packing density)之下，整體元件或電路 之功能仍須維持不變、甚至必須具有更好的可靠度、工 作壽命、並同時加入低功率消耗及低發熱率的特性。因 此半導體製程中的製程技術，諸如微影、蝕刻、沈積、 離子佈植等等的主要製程技術’必須同時的研究與發 本紙張尺度適用中國國家標準（CNS ) A料見格（210x297公釐） 經濟部中央標準局貝工消費合作社印製 495852 A7 __B7 五、發明説明（） ^ — 展，以達成下一代積體電路的發展目標。 在一般的積體電路中，最常被應用的元件之一即是 具有控制特性的電晶體’尤其是所謂的金氧半場效電曰 體（MOSFET)，隨著元件尺寸的日益縮減，次微米尺寸$ 金氧半場效電晶體同時面臨更多的挑戰。當積體電路中 母一個金氧半％效電晶體所占的長度與寬度縮小時，電 晶體的通道長度亦隨之縮減，而導致如墜穿效應、：戈、属 電流、接觸電阻等問題的加重，因而降低了半導體製程 的良率及元件的可靠度。 為了發展未來高速度的超大型積體電路（ULSI)、未 來的金氧半場效電晶體’必須使用如自行對準石夕化金屬 接觸、以及極淺的延伸源汲極接面（extended ultrashallow source/drain junction) 等技術 ，以 提供更 為提昇 的元件特性。在超大型積體電路（ULSI)或是大型積體電 路（VLSI)的電晶體元件中，自行對準的矽化金屬技術， 是用以提昇微米尺寸元件操作速度的關鍵，但相對來 說，使用自行對準的矽化金屬技術也必須面臨許多的挑 戰。 一般而言，自行對準矽化金屬的技術會導致金屬入 侵半導體基材的現象，而產生接面處洩漏電流的問題； 而於自行對準矽化金屬的過程中，往往會有未完全去除 的金屬層殘餘於閘極兩側的第一間隙壁上，而導致鄰近 區域間橋接（bridging)或短路（short)等的效應。有關使用 自行對準矽化金屬的技術上負面的效應，可參考C.Y. Lu 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) •裝. -訂 經濟部中央標準局員工消費合作社印裂 495852 A7 ___ B7 五、發明説明（） 等人所發表的研究結果 （“Process Limitation and Device Design Tradeoffs of Self-Aligned T i S12 JunctionField of invention Z (please read the precautions on the back before filling out this page) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a self-aligned metal silicide contact with a recess and an extended source electrode Method for manufacturing Metal Oxide Semiconductor Field Effect Transistor (MOSFET) of extended source / drain junctions. Background of the Invention: Since the first integrated circuit was first invented in 1960, the number of components on a single wafer in the semiconductor process has grown rapidly at an explosive rate. With the current stage of semiconductor process technology, ultra-large In the era of ultra large scale integration (ULSI) and even higher density, the number of components on a single chip has increased from thousands of components in the past to millions of components, and even thousands of components can be fabricated on a single chip 10,000 or more components. The substantial increase in the number of components printed on a single chip by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs has created a major challenge to semiconductor process technology. Each semiconductor component must be further reduced in size or occupation without affecting its function. Area, and under higher packing density, the function of the overall component or circuit must still remain unchanged, and it must even have better reliability, working life, and at the same time add low power consumption and low Heating rate characteristics. Therefore, the process technology in the semiconductor process, such as lithography, etching, deposition, ion implantation, etc., must be researched and published simultaneously. The paper size is applicable to the Chinese National Standard (CNS). ) Printed by 495852 A7 __B7, the Central Standards Bureau of the Ministry of Economic Affairs, Cooperate for Consumers. V. Description of Invention () ^ — Exhibition to achieve the development goals of the next generation of integrated circuits. In general integrated circuits, one of the most commonly used components is a transistor with control characteristics, especially the so-called metal-oxide-semiconductor field-effect transistor (MOSFET). As the size of components decreases, sub-microns At the same time, the size of the metal oxide half field effect transistor is facing more challenges. When the length and width occupied by a metal-oxygen half-efficiency transistor in the integrated circuit are reduced, the channel length of the transistor is also reduced, resulting in problems such as the fall-through effect, current, contact resistance, and other problems. This increases the yield of the semiconductor process and reduces the reliability of the device. In order to develop future high-speed ultra large integrated circuits (ULSI) and future metal-oxide-semiconductor half-effect transistors, such as self-aligned petrified metal contacts, and extremely shallow extended source drain junctions (extended ultrashallow source) / drain junction) to provide improved component characteristics. In ultra-large integrated circuit (ULSI) or large-scale integrated circuit (VLSI) transistor components, self-aligned metal silicide technology is the key to improve the operation speed of micron-sized components, but relatively speaking, the use of Self-aligned metal silicide technology must also face many challenges. Generally speaking, the technology of self-aligning metal silicide will cause the metal to invade the semiconductor substrate, which will cause the leakage current at the interface. In the process of self-aligning metal silicide, there will often be incompletely removed metal. Layers remain on the first gaps on both sides of the gate, causing bridging or shorting effects between adjacent areas. For the technical negative effects of using self-aligned silicide metal, please refer to CY Lu. This paper size applies the Chinese National Standard (CNS) A4 Zhuge (210X297 mm) (Please read the precautions on the back before filling out this page) • Installation.-Ordering of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 495852 A7 ___ B7 V. Research results published by () and others ("Process Limitation and Device Design Tradeoffs of Self-Aligned T i S12 Junction
Formation in Submicrometer CMOS Devices，，，IEEE Trans. Electron Devices，vol. ED-38，No. 2，1991)，其中提出在 應用自行對準矽化金屬技術與淺接面技術兩者間，在設 計上所需面臨的取捨。 在目前的製程技術之中，自行對準的矽化金屬已應 用於次微米以下的元件中，以增和積體電路的積集度， 並減少内部連接時的電阻，改進其操作速度。上述技術 之相關文獻之一，可參閱由 K· Fujii等人所發表之”A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM”（1996, IEEE，IEDM 96-45 1 )，在此 文獻中，發現自行對準的矽化金屬製程中，若使用鎢原 子佔原子百分率約5%的TiW合金作為金屬材料，則對於 閘極寬度為0.18微米的元件而言，於熱回火溫度高達攝 氏800度時，片電阻仍相當低。 至於因為元件尺寸變得越來越小所導致的「短通道 效應」（short channel effect)，可以藉著形成一極淺的延 伸源没極接面（extended ultra-shallow source/drain junctions)，而得到改善，有關此部分技術之相關文獻， 可參閱由A. Hori等人所提出之” A 0.05pm-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5Kev Ion Implantation and Rapid Thermal Annealing” （1 994, IEEE，IEDM 94-485) 〇 本紙張尺度適用中國國家標準（CNS )八4祝格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) •裝_ 訂 發明説明（ 發明曰的及概述： 本發明的主要目的為提供一種形成電晶體之方法。 本發明的另一目的為提供一種形成金氧半場效電晶 體（MOSFETs)的製造方法’以形成具有凹陷之自行對準的 矽化金屬接點及延伸源汲極接面。 本發明的再一目的為提供一種之金氧半場效電晶體 (MOSFETs)的製造方法，以提昇電.晶體的操作速度，Z改 善次微米及更小尺寸元件中短通道效應的問題。 經濟部中央標準局員工消費合作社印製 本發明中形成具有凹陷之自行對準的金屬矽化物接 點及延伸源汲極接面之金氧半場效電晶體的方法，可包 含以下步驟：首先形成隔離區域於基材之上；並形成閉 極絕緣層於基材上；再形成第一導體層於閘極絕緣層 上’接著形成第一介電層於第一導體層上；並去除部分 之第一介電層、第一導體層、及閘極絕緣層，以定義閉 極結構；然後形成第一熱氧化層於基材上及第一導艘層 之側壁上；再形成第一間隙壁於閘極結構之側壁上；接 著去除未被第一間隙壁覆蓋之第一熱氧化層；之後形成 第二熱氧化層於基材之曝露區域之上；並去除第一介電 層及第一間隙壁；再進行離子植入至位於基材表面上之 第一熱氧化層内；然後形成第二間隙壁於閘極結構之側 壁上；並去除第二熱氧化層以形成凹陷區域於基材表面 上；接著形成第一金屬層於基材上；再進行源極及極/ 閘極之離子植入；之後進行熱製程，以將位於凹陷區域 及第一導體層上方之第一金屬層反應為矽化金屬層，並 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐） 495852 A7 B7 五、發明説明（ 將基材表面上之第一熱氧化層内所摻雜的離子，驅入第 一熱氧化層下方的基材之内，以形成延伸源汲極接面； 並去除第一金屬層未反應之部分。 除此之外，並可進一步加入後續製程，以形成至少 一層以上的元件間連線結構，首先於第一金屬層未反應 之部分去除之後，形成一第二介電層於基材上；再對基 材進行一回火製程；並去除部分之第二介電層以形成接 觸洞於其内；之後形成第二金屬層於接觸洞内及第二介 電層上；最後去除部分之第二金屬層以定義内連線。 圖式簡單說明： 請 先 閱 讀 背 面， 之 注 意” 事 項 再 填 寫 本 頁 經濟部中央標準局員工消費合作社印製 上 、結 第 側氧 露 、 之 層極 及 之熱 曝 壁 材 體閘 上 構一 之 隙 基 導義 材 結第 材 間 體 一定基 極之基 一 導 第以 於。閘蓋 於 第 半 、分 層圊於覆 層 及 於 層部 化意壁壁 化 層 域 緣其 氧示隙隙 氧 電 區 絕除 熱面間間 熱。介 離 極去 一 截一一 二圖一 隔 閘並 第之第第。第意第 成 成，。成上成被圖成示除 形。形層圖形壁形未意形面去 中圖中電意中側中除示中截中 明意明介示明之明去面明的明 發示發一面發層發並截發上發 本面本第截本體本，之本之本 示截示及之示導示上層示域示 顯之顯以構顯 一 顯壁化顯區顯 圖 圖 圖圖 圖圖 一 二 三四 五六 第第 第第 第第 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐） 495852 A7 B7 五、發明説明（ 第七圖 第八圖 第九圖 再進行離子植入以形成延伸源汲極接面於基材 内第一熱氧化層下方之區域處的截面示意圖。 顯示本發明中形成第二間隙壁、去除第二熱氧 化層、形成第一金屬層、並進行源極/汲極/閘極 之離子植入之截面示意圖。 顯示本發明中進行矽化金屬反應後之截面示意 圖。 顯示本發明中定義内連線於第二介電層内之截 面示意囷。 經濟部中央標準局員工消費合作社印製 發明詳細說明： 本發明提供一種具有凹陷之自行對準的矽化金屬接 點及延伸源汲極接面之金氧半場效電晶體（m〇sfeTs)的 製造方法’藉由矽化金屬接點的應用，配合具矽化金屬 接點的閘極，可使電晶體的操作速度進_步提昇；而延 伸源没極接面的結構，可改善傳統結構中短通道效應的 問題，而以本發明中之方法所形成 〜取 < 兀件，可進一步應 用於更高積集度的製程之中，以择知；从^ ^ 以增加疋件的密度及效 能。 在不限制本發明的精神及應用範圍下，以下即以一 半導體製程中，形成一 N通道之金惫坐 P % 玉虱半場效電晶艚 (NMOS)的製程為例，介紹本發明之實 从益土 貝他而熟悉此領域 技藝者，可利相近之方法，以形成一 p ^通道之金氧半場 效電晶體（PMOS)，其變化之細節即不做眷 天处。參見第一 (請先閱讀背面之注意事項再填寫本頁) -裝. 訂 495852 A 7 B7 五、發明説明（） 圖所示，首先提供一半導體基材2，半導體基材2可為一 矽材質、晶向為<1 00>之半導體基材，並形成一氧化矽層 4於半導體基材2上，如圖中所示，氧化石夕層4係於一含 氧環境中，由半導體基材2加熱氧化成長而成；之後形 成一氮化矽層6於氧化矽層4上，以本實施例而言，氮 化矽層6之形成可使用沈積方式達成，例如使用化學氣 相沈積法等。 接著可利用微影及蝕刻製程以去除部分的氮化石夕層 6及氧化矽層4，以定義所需形成隔離區域的範圍，再接 著形成隔離區域，如圖中所示的場氧化區（field oxide region; F0X)8，以提供基材2上各元件間的所需隔離作 用。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 參見第二圖所示’接者利用渔姓刻法去除二氧化石夕 層4及氮化矽層6，再形成閘極絕緣層1 〇於基材2上， 本例中可利用熱氧化法形成二氧化矽層於基材2上，作 為閘極的氧化層。然後形成第一導體層12於基材2上 方、也就是閘極絕緣層1 〇與場氧化區8上方，在較佳實 施例中’可利用低壓化學氣相沈積法（Low Pressure Chemical Vapor Deposition，LPCVD)形成摻雜的多晶石夕 作為第一導體層12;接著即形成第一介電層i4於第一導 體層12之上，本例中第一介電層14可使用氮化矽層， 其可於後續的微影製程中做為抗反射層之用，並可利用 化學氣相沈積方式加以形成；此外，第一介電層14亦可 使用氧化矽層，並利用化學氣相沈積方式加以形成。 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐） 經濟部中央標準局貝工消費合作社印製 495852 A7 _ _B7___ 五、發明説明（） 在10,12及14三個不同膜層相疊的結構形成之後， 即可藉由微影及蝕刻製程的應用，姓去部分之第一介電 層14、第一導體層12、以及閘極絕緣層10,以定義出電 晶體之閘極結構1 6。依據本發明中較佳之實施例，第一 導體層12係為摻有雜質之多晶矽層、其厚度約為500到 7000埃（angstroms)之間，第一介電層14可為上述以沈積 方式形成的氮化石夕層、或是利用四乙基石夕酸鹽（tetra-ethyl-ortho-silicate; TE0S)作為反應氣體所形成之氧化 矽層，其厚度約為300至1 500埃之間。 參見第三圖所示，接著即分別形成第一熱氧化層18 及20於矽基材2的裸露區域上、以及第一導體層12之 側壁上，藉由第一熱氧化層1 8的形成，可恢復先前矽基 材2因蝕刻製程所造成的表面破壞或缺陷。依據本發明 之一較佳實施例，第一熱氧化層18及20可於N2〇或NO 的環境中，利用熱氧化製程，分別於矽基材2、以及第一 導體層12側面，藉由與矽的氧化反應而形成，而第一熱 氧化層18的厚度約為50到300埃之間；第一熱氧化層 20的厚度約為100到400埃之間。 參閱第四圊，之後形成第一間隙壁22於閘極結構16 的側壁上，以較佳實施例而言，第一間隙壁2 2可藉由沈 積並回蝕氮化矽層加以形成，其方法即是先沈積氮化矽 層於第一熱氧化層18及閘極結構16上，再以回蝕方式 去除部分之氮化矽層，即留下第一間隙壁22;在回蝕製 程中，未被第一間隙壁22所覆蓋部分之第一熱氧化層1 8 本紙張尺度適用中國國家標準（CNS ) A4取格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝· 訂- 495852 A7 B7____ 五、發明説明（） 亦會同時被去除。依據本發明之一實施例，氮化矽層之 厚度約為5 0 0至2 0 0 0埃之間，而其沈積的方法可利用低 壓化學氣相沈積法（Low Pressure Chemical Vapor Deposition; LPCVD)或電漿增強式化學氣相沈積法 (Plasma Enhanced Chemical Vapor Deposition; PECVD)等 方式。 參閱第五圖所示，之後即形成第二熱氧化層24於基 材2之曝露區域之上，本例中之第二熱氧化層24可利用 基材2曝露區域的熱氧化反應成長而成，其熱氧化製程 的溫度可約為750°C至1 10(TC之間，在較佳實施例之中， 其成長的厚度約為300至2000埃之間。 參見第六圖所示’接著去除第一介電層14及第一間 隙壁2 2 ’以使用氮化矽層做為第一介電層1 4及使用氮化 矽間隙壁的例子而言，第一介電層14及第一間隙壁2 2 可利用熱磷酸以溼蝕刻的方式加以去除。 經濟部中央標準局員工消費合作社印家 然後進行離子植入的製程，以將欲摻雜的離子植入 至位於基材表面上之第一熱氧化層内，以於後續的製程 中驅入基材、以形成延伸源汲極接面；以形成N型金氧 半場效電晶體為例，可使用含砷的離子或是含碌的離 子；在較佳實施中，所使用的植入能量約為〇 〇5Kev至 5KeV之間。在離子製程中，通常會使用如光阻等的罩 幕，來覆蓋不進行離子植入的區域，而在某些元件的區 域中，即可藉由第二熱氧化層24的覆蓋，而避免具污染 性的光阻材料或其他罩幕材質因直接接觸而污染矽基材 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐） 495852 A7 _____B7_____ 五、發明説明（） 2的表面。 參見第七圖所示，之後形成第二間隙壁2 2 a於閘極 結構1 6之側壁上，本例中之第二間隙壁22a可使用氮化 石夕間隙壁或是氧化矽間隙壁，並同樣使用沈積及回蝕的 製程加以形成；在形成間隙壁的回蝕步驟中，第二熱氧 化層24亦會因而被去除，以形成凹陷區域於基材2的表 面上。 接著形成第一金屬層26於基材2上，如第七圖所 不，並進行源極/汲極/閘極之離子植入。以一般的製程應 用而言，第一金屬層26可為如鈦、鎢、鈷、鉑、鎳及鉻 等的材料，以於後續製程之中與矽反應形成矽化金屬 層’本例中其厚度約為100至1〇〇〇埃之間，其沈積方法 可應用為化學氣相沈積法（CVD)或是濺鍍等的物理氣相 沈積法（PVD)。 而源極/汲極/閘極區域的離子植入，以形成N型金氧 半％效電晶體為例，可使用含碎的離子或是含破的離 子；在較佳實施中，所使用的植入能量約為1〇到12〇 KeV，以產生約為5E14至5E16 atoms/cm2之間的離子濃 度，形成凹陷區域下方的源極與没極區域並進一步 增加閘極結構1 6中多晶矽材料的摻雜濃度。 經濟部中央標準局員工消費合作社印製 接著參見第八圖，進行以加熱製程將金屬藉由高溫 的反應而矽化的製程，以將部分的第一金屬層26經由與 石夕的反應形成石夕化金屬層28，其中位於場氧化區域8 上、以及在氣化矽第二間隙壁22a上方與側邊之第一金 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐） 495852 經濟部中央榡準局貝工消費合作社印製 、發明説明（） 屬層26,由於未與矽表面接觸，因此並不參與反應。 之後並去除未反應的殘餘第一金屬層26，γ · 化金屬28。依據本發明之一較佳實施例，矽化：：：： 之熱製程所使用的溫度約為35〇到7〇(rc之間，:^二 程的作用之下，源極與汲極區域27内的離 製Formation in Submicrometer CMOS Devices ,, IEEE Trans. Electron Devices, vol. ED-38, No. 2, 1991), which proposed the application of both self-aligned metal silicide technology and shallow junction technology in design. The trade-offs to be faced. In the current process technology, self-aligned silicided metal has been applied to sub-micron components to increase the integration of integrated circuits, reduce the resistance during internal connection, and improve its operating speed. For one of the related documents of the above technology, please refer to "A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM" (1996, IEEE, IEDM 96-45 1) published by K. Fujii et al., Here In the literature, it was found that in the process of self-aligned silicided metal, if a TiW alloy with tungsten atoms accounting for about 5% of the atomic percentage is used as the metal material, for components with a gate width of 0.18 microns, the thermal tempering temperature can reach At 800 degrees, the sheet resistance is still quite low. As for the "short channel effect" caused by the component size becoming smaller and smaller, it can be achieved by forming an extended ultra-shallow source / drain junctions, and It has been improved. For related literature on this part of technology, please refer to "A 0.05pm-CMOS with Ultra Shallow Source / Drain Junctions Fabricated by 5Kev Ion Implantation and Rapid Thermal Annealing" proposed by A. Hori et al. (1 994, IEEE , IEDM 94-485) 〇 This paper size applies to Chinese National Standard (CNS) 8 4 Zhuge (210X297 mm) (Please read the notes on the back before filling this page) • _ Order the invention description (invented and Summary: The main object of the present invention is to provide a method for forming a transistor. Another object of the present invention is to provide a manufacturing method for forming metal-oxide-semiconductor field-effect transistors (MOSFETs) to form a self-aligned silicided metal with a recess Contact and extended source drain interface. Another object of the present invention is to provide a method for manufacturing metal oxide half field effect transistors (MOSFETs) to improve The operating speed of the crystal, Z improves the problem of short channel effects in sub-micron and smaller size components. Printed by the Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, forming self-aligned metal silicide contacts with depressions and extensions in the present invention The method of a metal-oxygen half field effect transistor at the source-drain junction can include the following steps: first forming an isolation region on the substrate; and forming a closed-pole insulating layer on the substrate; and then forming a first conductor layer on the gate A first dielectric layer is then formed on the first conductor layer on the insulating layer; a portion of the first dielectric layer, the first conductor layer, and the gate insulating layer are removed to define a closed-pole structure; and then a first thermal layer is formed An oxide layer is formed on the substrate and the side wall of the first guide ship layer; a first gap wall is formed on the side wall of the gate structure; a first thermal oxide layer not covered by the first gap wall is removed; and a second The thermal oxidation layer is on the exposed area of the substrate; the first dielectric layer and the first spacer are removed; ion implantation is performed into the first thermal oxidation layer on the surface of the substrate; and then a second spacer is formed Yuzha On the sidewall of the structure; and removing the second thermal oxidation layer to form a recessed area on the surface of the substrate; then forming a first metal layer on the substrate; and then performing ion implantation of the source and the gate / gate; The process is to react the first metal layer located above the recessed area and the first conductor layer to a silicided metal layer, and this paper size applies the Chinese National Standard (CNS) A4 Zhuge (210X297 mm) 495852 A7 B7 V. Description of the invention (Doping ions doped in the first thermal oxidation layer on the substrate surface into the substrate below the first thermal oxidation layer to form an extended source drain junction; and removing the first metal layer without reaction Part of it. In addition, a subsequent process can be further added to form at least one layer of inter-element connection structure. First, after the unreacted portion of the first metal layer is removed, a second dielectric layer is formed on the substrate; A tempering process is performed on the substrate; a portion of the second dielectric layer is removed to form a contact hole therein; a second metal layer is then formed in the contact hole and the second dielectric layer; and finally a portion of the second dielectric layer is removed. Metal layer to define interconnects. Brief description of the diagram: Please read the back first, pay attention to the “Items” and then fill in this page. Printed on the page of the Ministry of Economic Affairs, Central Bureau of Standards, Consumer Cooperatives, printed on the side of the oxygen dew, layered and heat-exposed wall material. The gap base leads to the base of a certain base. The gate cover is in the second half, stratified by the cladding and the edge of the wall. The gap oxygen electric zone eliminates the heat between the hot surfaces. The cut-off pole is cut off one by one, two, one, and the first. The first is formed, the upper is formed, and the shape is removed. The graphic wall shape is not in the shape of the picture. In the figure, the middle of the picture is shown in the middle. In the middle of the show, the clear is clearly introduced. The clear is shown. The ontology, the essence, the essence of the display, and the instruction of the display of the upper display of the display to construct a wall display area map map map map map chart one two three four five six first second This paper size applies Chinese National Standard (CNS) A4 Zhuge (210X297 mm) 495852 A7 B7 Explanation of the invention (Seventh figure, eighth figure, ninth figure, and then ion implantation to form an extended source drain junction at a region under the first thermal oxidation layer in the substrate. A cross-sectional view showing the formation of the second in the present invention A schematic cross-sectional view of a partition wall, removing a second thermal oxide layer, forming a first metal layer, and performing source / drain / gate ion implantation. Shows a schematic cross-sectional view of a silicided metal reaction in the present invention. Shows the present invention The definition of the cross-section of the inner wiring defined in the second dielectric layer is shown in the figure. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economics. Manufacturing method of metal oxide half field effect transistors (MOSFs) with pole junctions' Through the application of silicided metal contacts and gates with silicided metal contacts, the operation speed of the transistor can be further increased; The structure of the extended source electrode interface can improve the problem of the short channel effect in the traditional structure. The method formed by the method of the present invention can be further applied to In the high-accumulation process, choose to know; from ^ ^ to increase the density and efficiency of the software. Without limiting the spirit and scope of the invention, the following is a semiconductor process to form an N channel Jin Fei sits on the P% jade lice half field effect electric crystal cricket (NMOS) manufacturing process as an example to introduce the practicality of the present invention and benefit to those skilled in the art, which can be similar methods to form a p ^ channel. Metal Oxide Half-Field-Effect Transistors (PMOS), the details of their changes are not relevant. See the first (please read the precautions on the back before filling out this page)-equipment. Order 495852 A 7 B7 V. Description of the invention ( As shown in the figure, a semiconductor substrate 2 is first provided. The semiconductor substrate 2 may be a silicon substrate with a crystal orientation of < 1 00 >, and a silicon oxide layer 4 is formed on the semiconductor substrate 2. As shown in the figure, the oxidized stone layer 4 is formed in an oxygen-containing environment, and is grown by heating and oxidizing the semiconductor substrate 2. Then, a silicon nitride layer 6 is formed on the silicon oxide layer 4. According to this embodiment, In other words, the formation of the silicon nitride layer 6 can be achieved by a deposition method, such as using a chemical gas. Phase deposition and so on. Then, a lithography and etching process can be used to remove a part of the nitride nitride layer 6 and the silicon oxide layer 4 to define the range of the isolation region to be formed, and then an isolation region is formed, as shown in the field oxide region (field) oxide region; F0X) 8 to provide the required isolation between the various components on the substrate 2. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Then, a gate insulating layer 10 is formed on the substrate 2. In this example, a silicon dioxide layer can be formed on the substrate 2 by using a thermal oxidation method as an oxide layer of the gate. A first conductor layer 12 is then formed over the substrate 2, that is, above the gate insulating layer 10 and the field oxidation region 8. In a preferred embodiment, 'Low Pressure Chemical Vapor Deposition, LPCVD) to form a doped polycrystalline stone as the first conductor layer 12; then a first dielectric layer i4 is formed on the first conductor layer 12. In this example, a silicon nitride layer can be used as the first dielectric layer 14. It can be used as an anti-reflection layer in the subsequent lithography process and can be formed by chemical vapor deposition. In addition, a silicon oxide layer can also be used as the first dielectric layer 14 and chemical vapor deposition can be used. Way to form. This paper size is applicable to Chinese National Standard (CNS) A4 Zhuge (210X297 mm) Printed by the Shelling Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 495852 A7 _ _B7___ 5. Description of the invention () In 10, 12 and 14 three different film layers After the stacked structures are formed, the first dielectric layer 14, the first conductor layer 12, and the gate insulating layer 10 can be removed by the application of the lithography and etching processes to define the gate of the transistor.极 结构 1 6. According to a preferred embodiment of the present invention, the first conductor layer 12 is a polycrystalline silicon layer doped with impurities and has a thickness of about 500 to 7000 angstroms. The first dielectric layer 14 may be formed by the deposition method described above. Or a silicon oxide layer formed by using tetra-ethyl-ortho-silicate (TEOS) as a reactive gas, the thickness of which is between 300 and 1,500 angstroms. Referring to the third figure, first thermal oxide layers 18 and 20 are respectively formed on the exposed area of the silicon substrate 2 and the sidewalls of the first conductor layer 12 by the formation of the first thermal oxide layer 18 , Can recover the previous silicon substrate 2 surface damage or defect caused by the etching process. According to a preferred embodiment of the present invention, the first thermal oxidation layers 18 and 20 can be thermally oxidized on the side of the silicon substrate 2 and the first conductor layer 12 in a N2O or NO environment by using a thermal oxidation process. It is formed by an oxidation reaction with silicon, and the thickness of the first thermal oxidation layer 18 is between 50 and 300 angstroms; the thickness of the first thermal oxidation layer 20 is between 100 and 400 angstroms. Referring to the fourth step, a first spacer wall 22 is then formed on the sidewall of the gate structure 16. In a preferred embodiment, the first spacer wall 22 can be formed by depositing and etching back a silicon nitride layer. The method is to first deposit a silicon nitride layer on the first thermal oxide layer 18 and the gate structure 16, and then remove a part of the silicon nitride layer by etchback, leaving the first spacer 22; in the etchback process, ， The first thermal oxide layer that is not covered by the first spacer 22 1 8 This paper size applies the Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page) -Binding · Order-495852 A7 B7____ 5. The description of the invention () will also be removed at the same time. According to an embodiment of the present invention, the thickness of the silicon nitride layer is between 500 and 2000 angstroms, and the method for depositing the silicon nitride layer can be a Low Pressure Chemical Vapor Deposition (LPCVD) method. Or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition; PECVD). Referring to the fifth figure, a second thermal oxidation layer 24 is then formed on the exposed area of the substrate 2. The second thermal oxidation layer 24 in this example can be grown by using the thermal oxidation reaction of the exposed area of the substrate 2. The temperature of the thermal oxidation process may be between about 750 ° C and 110 ° C. In a preferred embodiment, the thickness of its growth is between about 300 and 2000 Angstroms. See FIG. For the example of removing the first dielectric layer 14 and the first spacers 2 2 ′, using the silicon nitride layer as the first dielectric layer 14, and using the silicon nitride spacers, the first dielectric layer 14 and the first spacer 14 A partition wall 2 2 can be removed by wet etching using hot phosphoric acid. The staff of the Central Standards Bureau of the Ministry of Economic Affairs, the Consumer Cooperative, and the Inner House then perform an ion implantation process to implant the ions to be doped on the surface of the substrate. In the first thermal oxidation layer, the substrate is driven in a subsequent process to form an extended source drain junction. Taking the formation of an N-type metal-oxygen half field effect transistor as an example, arsenic-containing ions or Ions; in a preferred implementation, the implantation energy used is about 0.05 KeV to 5 KeV In the ion manufacturing process, a mask such as a photoresist is usually used to cover the area where the ion implantation is not performed, and in the area of some components, it can be covered by the second thermal oxide layer 24. And to avoid contaminating photoresist materials or other screen materials from contaminating the silicon substrate due to direct contact. The paper size applies the Chinese National Standard (CNS) A4 Zhuge (210X297 mm) 495852 A7 _____B7_____ V. Description of the invention () 2 As shown in the seventh figure, a second spacer wall 2 2 a is formed on the side wall of the gate structure 16. The second spacer wall 22 a in this example can be a nitride spacer or a silicon oxide spacer. The wall is also formed using the process of deposition and etchback; in the etchback step of forming the gap wall, the second thermal oxide layer 24 is also removed to form a recessed area on the surface of the substrate 2. Next, The first metal layer 26 is on the substrate 2, as shown in the seventh figure, and source / drain / gate ion implantation is performed. In general process applications, the first metal layer 26 may be, for example, titanium , Tungsten, cobalt, platinum, nickel and chromium Material to react with silicon to form a silicided metal layer in subsequent processes. In this example, the thickness is about 100 to 1000 angstroms. The deposition method can be applied by chemical vapor deposition (CVD) or sputtering. Physical vapor deposition (PVD) methods such as plating. For ion implantation in the source / drain / gate regions, for example, to form an N-type metal-oxygen half-efficiency transistor, you can use fragmented ions or Broken ions; in a preferred implementation, the implantation energy used is about 10 to 120 KeV to generate an ion concentration between about 5E14 and 5E16 atoms / cm2, forming a source and a sink below the recessed area. And further increase the doping concentration of the polycrystalline silicon material in the gate structure 16. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, and then referring to Figure 8, a process of silicifying the metal by a high temperature reaction using a heating process is performed to form a part of the first metal layer 26 through a reaction with Shi Xi. The metallized layer 28 is located on the field oxidation region 8 and the first gold paper size above and to the side of the second spacer 22a of the vaporized silicon is in accordance with the Chinese National Standard (CNS) A4 Zhuge (210X297 mm) 495852 Printed by the Central Laboratories Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, and description of the invention () Layer 26, because it is not in contact with the silicon surface, so it does not participate in the reaction. Thereafter, the unreacted residual first metal layer 26 and the γ · metal 28 are removed. According to a preferred embodiment of the present invention, the temperature of the silicidation :::: used in the thermal process is about 350-700 (rc, between the source and the drain region 27 under the effect of the second pass). Internal disengagement
Mr u I進一步擴 =及活化(activate)，…圖所示，以形成延伸源没極 接面25,並同時將基材2表面上之第一熱氧化層18内所 摻雜的離子，驅入第一熱氧化層18下方的基材2之内， 以形成延伸源汲極接面3 0於第一熱氧化層丨8下方的區 域處，以較佳實施例而言，所形成之延伸源汲極接面3〇 的摻雜濃度約為1E14至3E15 atoms/cm2之間。在熱製程 的反應處理之後，殘餘的第一金屬層26即以習知用以去 除金屬的濕蝕刻法加以去除。因此即可形成如圖中所示 的’具有凹陷之自行對準的矽化金屬接點、以及延伸源 沒極接面的金氧半場效電晶體。 除了上述的製程之外，可進一步加入一系列的後續 製程，以形成一層、或通常是多層的元件間連線結構， 參見第九圖所示，首先形成第二介電層32於基材2之 上’本例中可利用化學氣相沈積法沈積氧化矽層做為第 二介電層32。並接著進行回火製程，以使氧化矽層32 的材料變得較為密實，提昇其隔絕特性，並使矽化金屬 層28經由回火的處理進入較為穩定的狀態；接著去除部 分之第二介電層32，以定義接觸洞於其内，一般可使用 微影製程及蝕刻製程加以達成之。然後再形成第二金屬 12 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 • A7 ^一---_______ B7___ i、發明説明（） 層34於第二介電層32 '並填入於接觸洞内。最後可配合 微影製程及姓刻製程的使用，除去部分之第二金屬層 3 4 ’以定義内連線。依據本發明之較佳實施例，回火製 程的處理溫度約為7〇〇到95〇〇c之間，而第二金屬層34 可為如鋁、銅、鈦、鎢、鈷、鉑、鎳及鉻等的材料。 因此’藉由本發明中之方法，可形成具有凹陷之自 行對準的矽化金屬接點 '以及延伸源汲極接面的金氧半 場效電晶體，並提供良好的操作速度，同時抑制傳統製 程與元件所產生的短通道效應，而進一步提昇積體電路 的運作特性及元件積集度。 本發月僅以較佳實施例說明如上，並非用以限定本 發明之申請範圍；凡熟習該項技藝人士，在未脫離本發 明之精神下，當可作些許改變或修飾，其專利保護範圍 均應包含在下述之申請專利範圍内。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Mr u I further expands and activates, as shown in the figure, to form the extended source electrode contact surface 25, and at the same time, the ions doped in the first thermal oxidation layer 18 on the surface of the substrate 2 are driven. Into the substrate 2 under the first thermal oxidation layer 18 to form an extension source drain junction 30 at a region under the first thermal oxidation layer 丨 8, in the preferred embodiment, the formed extension The doping concentration of the source-drain junction 30 is about 1E14 to 3E15 atoms / cm2. After the thermal processing reaction process, the remaining first metal layer 26 is removed by a conventional wet etching method for removing metal. As a result, a self-aligned silicided metal contact with a recess and a metal-oxide half-field-effect transistor with an extended source terminal can be formed as shown in the figure. In addition to the above-mentioned processes, a series of subsequent processes can be further added to form a single layer, or usually a multilayer connection structure between components. Referring to FIG. 9, a second dielectric layer 32 is first formed on the substrate 2. Above 'In this example, a silicon oxide layer can be deposited as the second dielectric layer 32 by a chemical vapor deposition method. Then, a tempering process is performed to make the material of the silicon oxide layer 32 denser, improve its insulation characteristics, and make the silicided metal layer 28 enter a more stable state through the tempering treatment; then remove part of the second dielectric The layer 32 is used to define a contact hole therein, which can generally be achieved using a lithography process and an etching process. Then form the second metal 12 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) Binding · A7 ^ 一 ---_______ B7___ i. Description of the invention () The layer 34 is filled in the contact hole in the second dielectric layer 32 '. Finally, it can be used with the lithography process and the last name engraving process to remove a portion of the second metal layer 3 4 ′ to define the interconnection. According to a preferred embodiment of the present invention, the processing temperature of the tempering process is between about 700 and 9500c, and the second metal layer 34 may be, for example, aluminum, copper, titanium, tungsten, cobalt, platinum, nickel And chromium and other materials. Therefore, by the method of the present invention, a self-aligned silicided metal contact with a recess can be formed and a gold-oxygen half field-effect transistor extending the source-drain interface, and provide a good operating speed, while suppressing traditional processes and The short-channel effect produced by the component further improves the operating characteristics of the integrated circuit and the degree of component accumulation. This post only uses the preferred embodiments to explain the above. It is not intended to limit the scope of application of the invention. Those skilled in the art can make some changes or modifications without departing from the spirit of the invention. The scope of patent protection All should be included in the scope of patent application described below. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs This paper is sized for China National Standard (CNS) A4 (210X297 mm)