JP2000269496A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture of a semiconductor device, which can cope with micronization by enabling a thin oxide film to be formed on the surface of a silicon substrate by the same thermal oxidation process before ion implantation process for formation of source and drain diffused layers, and enabling an oxide film of sufficient thickness to secure reliability to be formed at the sidewall of a gate electrode, and the end of a gate. SOLUTION: A silicon oxide film 20 as a gate insulating film is made on a silicon semiconductor substrate 2, and a gate electrode 22 is made on the gate insulating film. Furthermore, element to delay the oxidation of silicon is introduced into the semiconductor substrate 2 on both sides of the gate electrode 22, and after this introduction, the thermal oxidation is performed to form a silicon oxide film 26a on the semiconductor substrate 2, and to form a silicon oxide film 26b which is thicker than the silicon oxide film 26a on the sidewall of the electrode 22, at the same time. Furthermore, an n- layer 28 and a p- layer 30 for serving as a source and a drain, respectively, are made within the semiconductor substrate 2 on both sides of the gate electrode 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a source / drain diffusion layer in a MOSFET.

[0002]

2. Description of the Related Art In a CMOS LSI of a 0.1 μm generation or later in a semiconductor device, the depth of a diffusion layer in a source / drain portion is required to be smaller with the progress of miniaturization of a gate length of a MOSFET. For example, 200
It is expected that the gate length of a MOSFET used for a CMOS LSI that is expected to be mass-produced around five years will be reduced to about 0.05 μm. In order to normally operate such a miniaturized MOSFET without increasing the parasitic resistance, it is necessary to form a diffusion layer having a depth of about 250 ° and a sheet resistance of about 500Ω / □. is there.

Usually, a diffusion layer of a MOSFET of a CMOS LSI is formed by performing an activation heat treatment after introducing impurities by ion implantation. Shallow diffusion layer (shallow junction)
It is necessary to lower the acceleration voltage of ion implantation and shorten the time of heat treatment in order to form the ion implantation. For the former, the ion implantation energy is reduced, and for the latter, the activation time is shortened. Is required.

In particular, regarding the acceleration voltage for ion implantation,
For example, in order to reduce the depth of the shallow diffusion layer from about 500 ° to about 250 ° in the related art, it is necessary to perform ion implantation under the following conditions. n-channel MOSFE
As for arsenic (As) used for forming a T diffusion layer, an acceleration voltage of about 10 [keV] is changed to 3 [ke].
V]. Also,
Even for boron (B) used for forming a diffusion layer of a p-channel MOSFET, it is necessary to lower the acceleration voltage to about 300 [eV].

[0005]

In the process of manufacturing a MOSFET, it is necessary to perform a post-oxidation process after forming a gate electrode before an ion implantation process for forming a shallow diffusion layer. A thermal oxide film is formed on the surface of the silicon substrate. Here, it is assumed that a post-oxidation step forms a thermal oxide film having a thickness of 40 ° required as an insulating film. In this case, the acceleration voltage at the time of ion implantation is reduced to about 3 [keV] for As, and 300 [eV] for B.
When it is reduced to a degree, as can be seen from the relationship between the acceleration voltage and the average range shown in FIGS. 34A and 34B, the thermal oxide film having a thickness of 40 ° exists on the silicon substrate. ,
Impurities introduced into the silicon substrate are substantially reduced,
There is a problem that the doping concentration is reduced.

On the other hand, if the amount of oxidation in the post-oxidation step is reduced to reduce the thickness of the thermal oxide film, the oxide film formed at the gate edge, that is, the so-called gate bird's peak, becomes thin. For this reason, there arises a problem that the overlap capacitance increases and leads to an increase in the gate load capacitance, and that the insulation withstand voltage decreases and reliability cannot be ensured. FIG.
FIG. 4 is a cross-sectional view showing a structure after post-oxidation in a MOSFET manufacturing process. Gate electrode 1 made of polysilicon
In the case where 00 is formed and post-oxidation is performed, this polysilicon is oxidized together with the silicon substrate, and the oxide film thickness at the edge of the gate increases. This oxide film at the edge of the gate is referred to as a gate bird's peak 102. As described above, when the amount of post-oxidation is reduced, the gate bird's peak 102 becomes as thin as the thickness of the oxide film (post-oxide film) 104 on the silicon substrate. Therefore, there is a strong demand for a process capable of securing an oxide film thickness at the gate bird's peak and reducing the thickness of an oxide film formed on the silicon substrate surface.

Further, as the gate oxide film becomes thinner to 15 ° or less with the progress of miniaturization, the direct tunnel current increases. In order to suppress the increase in the direct tunnel current, it is expected that a nitride film is used as a gate insulating film instead of the oxide film. When a nitride film is used as a gate insulating film, after the gate processing,
Removing the silicon nitride film formed on the silicon substrate,
Thereafter, a post-oxidation step needs to be performed. In this case, since the post-oxidation is performed after the silicon nitride film is stripped, it is necessary to increase the thickness of the gate bird's peak oxide film from the viewpoint of ensuring reliability.

On the other hand, in order to realize a shallow diffusion layer,
As described above, it is necessary to reduce the thickness of the screen oxide film when performing ion implantation. Therefore, even in such a case, although the oxide film (gate bird's peak) formed at the edge of the gate is made thicker, the oxidation rate on the surface of the silicon substrate is suppressed as much as possible, and the formed oxide film is made thinner. It becomes important.

Therefore, the present invention has been made in view of the above-mentioned problem, and a thin oxide film is formed on the surface of a silicon substrate by the same thermal oxidation process before an ion implantation process for forming a source / drain diffusion layer. It is another object of the present invention to provide a method for manufacturing a semiconductor device which can cope with miniaturization because an oxide film having a thickness sufficient to secure reliability can be formed on the side wall of the gate electrode and the edge of the gate electrode.

[0010]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate insulating film on a silicon semiconductor substrate, and a step of forming a gate on the gate insulating film. A step of forming an electrode, a step of introducing an element that delays oxidation of silicon into the semiconductor substrate on both sides of the gate electrode, and a step of introducing the element. Forming a first silicon oxide film and simultaneously forming a second silicon oxide film on the side wall of the gate electrode, the second silicon oxide film being thicker than the first silicon oxide film; Forming a diffusion layer serving as a source or a drain therein.

Further, according to a method of manufacturing a semiconductor device of the present invention, there is provided a step of forming a gate insulating film in which a silicon oxide film and a silicon nitride film are laminated in this order on a silicon semiconductor substrate; A step of forming a gate electrode; a step of removing the silicon nitride film formed on the semiconductor substrate on both sides of the gate electrode; and an element for delaying oxidation of silicon in the semiconductor substrate on both sides of the gate electrode. After the step of introducing and the step of introducing the element, thermal oxidation is performed to form a first silicon oxide film on the semiconductor substrate, and at the same time, a first silicon oxide film is formed on a side wall of the gate electrode from the first silicon oxide film. Forming a thick second silicon oxide film; and forming a diffusion layer serving as a source or a drain in the semiconductor substrate on both sides of the gate electrode. To.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a gate insulating film on a silicon semiconductor substrate; forming a gate electrode on the gate insulating film; After the step of introducing an element that delays the oxidation of silicon into the semiconductor substrate and the step of introducing the element, thermal oxidation is performed to form a first silicon oxide film on the semiconductor substrate, and at the same time, forming the gate. Forming a second silicon oxide film having a thickness greater than that of the first silicon oxide film on the side wall of the electrode; removing the first silicon oxide film on the semiconductor substrate; A step of leaving the second silicon oxide film on a side wall; and a step of forming a diffusion layer serving as a source or a drain in the semiconductor substrate on both sides of the gate electrode. .

Further, the method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a silicon semiconductor substrate; a step of forming a gate electrode made of silicon on the gate insulating film; A step of introducing an element that delays the oxidation of silicon in the semiconductor substrate on both sides of the electrode, and the upper part of the gate electrode, and after the step of introducing the element, thermal oxidation is performed, on the semiconductor substrate, and on the gate electrode. Forming a first silicon oxide film on the upper portion, and simultaneously forming a second silicon oxide film thicker than the first silicon oxide film on a side wall of the gate electrode; After a step of forming a first diffusion layer serving as a source or a drain in the semiconductor substrate and a step of forming the first diffusion layer, an insulating film is deposited and the gate electrode is formed. Forming a gate sidewall film by leaving the insulating film only on the sidewall, and a second diffusion layer deeper than the first diffusion layer serving as a source or a drain in the semiconductor substrate on both sides of the gate sidewall film Forming the first diffusion layer, removing the first silicon oxide film on the second diffusion layer and the gate electrode, and forming a high melting point metal film on the second diffusion layer and the gate electrode. And forming a metal silicide film on the second diffusion layer and the gate electrode by silicidizing the refractory metal.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an element isolation region for dividing an element region in a silicon semiconductor substrate; A step of forming a well region, a step of forming a gate insulating film on the element region, a step of forming a gate electrode made of silicon on the gate insulating film, and a step of forming a gate electrode in the p-well region on both sides of the gate electrode. And a step of introducing an element that delays the oxidation of silicon into the upper part of the gate electrode in the n-well area, and after the step of introducing the element, thermal oxidation is performed, so that the p-well area, the n-well area, and Forming a first silicon oxide film on the gate electrode, and simultaneously forming a second silicon oxide film thicker than the first silicon oxide film on a side wall of the gate electrode; Forming a shallow diffusion layer serving as a source or a drain in the p-well region and the n-well region on both sides of the gate electrode; and forming an insulating film after the step of forming the shallow diffusion layer. Forming a gate sidewall film by leaving the insulating film only on the sidewall of the gate electrode; and deep diffusion serving as a source or a drain in the p-well region and the n-well region on both sides of the gate sidewall film. Forming a layer, removing the first silicon oxide film on the deep diffusion layer and the gate electrode, and forming a high melting point metal film on the deep diffusion layer and the gate electrode; Forming the metal silicide film on the deep diffusion layer and the gate electrode by silicidizing the high melting point metal.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate insulating film on a silicon semiconductor substrate; a step of forming a gate electrode on the gate insulating film; A step of introducing carbon into the semiconductor substrate, and a step of performing a heat treatment after the step of introducing carbon to form a silicon carbide layer on the semiconductor substrate, and a step of forming the silicon carbide layer. Thereafter, thermal oxidation is performed to form a first silicon oxide film on the semiconductor substrate, and at the same time, a second silicon oxide film thicker than the first silicon oxide film on a side wall of the gate electrode. Forming a diffusion layer as a source or a drain in the semiconductor substrate on both sides of the gate electrode.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A case where the present invention is applied to a method for manufacturing a CMOS circuit will be described below with reference to the drawings.

First, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. 1 to 12
FIG. 3 is a cross-sectional view of the semiconductor device in each step showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

First, an element isolation region is formed on a semiconductor substrate by using a commonly used method. For example, the element isolation region may be formed by a post-selection oxidation method in which oxidation is performed in a state where the element region is covered with a silicon nitride film in advance, and a silicon oxide film is formed only in the element isolation region. Alternatively, reactive ion etching (RIE)
Alternatively, a shallow trench isolation method may be used in which a silicon groove is formed only in an element isolation region by using a method, and an insulating film is buried in the silicon groove to form an element isolation region. Here, a shallow trench isolation method is used. Note that the semiconductor substrate may be of either p-type or n-type conductivity.

As shown in FIG. 1, a p-type silicon semiconductor substrate 2 having a resistivity of 1 to 5 [Ωcm] formed by the CZ method.
A silicon oxide film (thermal oxide film) 4 having a thickness of about 20 to 200 ° is formed thereon by a thermal oxidation method. On this silicon oxide film 4, a silicon nitride film 6 is formed to a thickness of about 1000 ° by LPCVD.

Subsequently, a resist film is applied on the silicon nitride film 6 by photolithography to form a resist pattern 8 from which the resist film on the element isolation region is removed as shown in FIG. Using the resist pattern 8 as a mask, the silicon nitride film 6 and the silicon oxide film 4 are etched by a reactive ion etching method, and then the resist pattern 8 is removed.

Then, as shown in FIG. 3, using the silicon nitride film 6 remaining only on the element region as a mask, a silicon groove 10 having a depth of about 3000 ° is formed by reactive ion etching. The depth of the silicon groove 10 is set to be about 1 to 2 times the design rule. For example,
In the LSI of the 0.15 μm rule, the depth of the silicon groove 10 is about 1500 to 3000 °.

After forming the silicon groove 10 in this manner,
To fill the inside of the silicon groove 10 with an insulating film, LP
A silicon oxide film is deposited using a CVD method. The thickness of the silicon oxide film deposited here is set to a thickness that is approximately equal to the depth of the silicon groove 10 and the thickness of the mask material (silicon nitride film 6). This silicon oxide film deposition method includes H
A DP method (a method of depositing an insulating film using high-density plasma) may be used. Before burying the inside of the silicon groove 10 with a silicon oxide film, thermal oxidation may be performed in an oxygen atmosphere at about 1000 ° C. to form a silicon oxide film on the inner wall of the silicon groove 10 with a thickness of about 50 to 150 °. . Further, this silicon oxide film may be formed using a method other than the thermal oxidation method. Subsequently, the deposited silicon oxide film is polished and flattened by a chemical mechanical polishing method (CMP method) to form an element isolation region 12. FIG. 4 shows the structure of the semiconductor substrate after the steps up to here.

Then, after performing an NHF process for adjusting the height between the element isolation region 12 (field oxide film) and the silicon surface (active region) of the semiconductor substrate 2, the silicon nitride film covering the element region is formed. 6 is removed using, for example, hot phosphoric acid. Further, as shown in FIG. 5, the silicon oxide film 4 covering the element region is removed with an NHF solution. FIG. 5 shows the structure of the semiconductor substrate after the steps described above.
Shown in

Subsequently, as shown in FIG.
The silicon surface is oxidized by a thermal oxidation method to a thickness of about 50 to
A 100 ° silicon oxide film 14 is formed. In addition,
P-well region in nMOSFET region by on-injection method
16 and an n-well region 18 in the pMOSFET region
I do. In the formation of the p-well region 16, boron (B) is
Using an acceleration voltage of 50 to 350 [keV], 5 × 10¹²
~ 2 × 10¹³[Cm^-2] At a dose of about
You. In forming the n-well region 18, phosphorous (P) is
Using an acceleration voltage of ~ 500 [keV], 5 x 10¹²~ 2
× 10¹³[Cm ^-2] At a dose of about].
Further, the threshold voltage of a transistor to be formed is controlled.
Therefore, the p-well region 16 and the n-well region
Necessary ion implantation is also performed on a region to be a channel. example
In this case, boron (B) is added to the p-well region 16 by 20 [ke].
V] and an acceleration voltage of 1 × 10¹²~ 1 × 10¹³[Cm
^-2] At a dose of about]. n-well region 1
8, an accelerating voltage of 100 [keV] is applied to arsenic (As).
Used, 1 × 10¹²~ 1 × 10¹³[Cm^-2] About dose
Ion implantation with volume.

Then, after the silicon oxide film 14 serving as the dummy gate insulating film is peeled off using a dilute HF solution, as shown in FIG. 7, a silicon oxide film serving as a gate insulating film is formed on the element region by a thermal oxidation method. 20 is formed to a thickness of about 10 to 40 °. In forming the silicon oxide film 20, it is possible to form a silicon oxide film of 50 ° or less in the element region by performing annealing in an oxygen atmosphere at about 750 ° C. using a normal vertical diffusion furnace. Alternatively, it may be formed in a high-temperature furnace (RTO apparatus) at a high temperature of about 1000 ° C. in an oxygen atmosphere. As the gate insulating film, a nitride film or a high dielectric film can be used in addition to the thermal oxide film of the silicon oxide film 20.

After the formation of the silicon oxide film 20, a film thickness of about 3 is formed on the silicon oxide film 20 by, for example, LPCVD.
A polysilicon film (or amorphous silicon film) 22a of 00 to 2000 ° is deposited. Then, a resist pattern 24 for processing the gate pattern is formed by photolithography or electron beam exposure. FIG. 7 shows a resist pattern 24 formed by a photolithography method.

Subsequently, using the resist pattern 24 as a mask, a gate pattern 22 is formed by a reactive ion etching method using a halide as an etching gas, as shown in FIG. At this time, the size of the formed gate pattern is about 0.05 to 0.25 μm.
Further, the silicon oxide film 20 on the p-well region 16 and the n-well region 18 is removed. After that, the resist pattern 24 is peeled off.

Next, as shown in FIG. 8, a nitrogen atom (mass number 14) or a nitrogen molecule (mass number 28) is selected as an ion source by ion implantation, and an acceleration voltage of about 10 keV is used. Ion implantation is performed at a dose of about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ [cm ⁻² ]. As described above, after nitrogen is introduced into the substrate 2 by the ion implantation method, under predetermined conditions,
In this case, 40 ° on a silicon substrate into which nitrogen has not been introduced.
Oxidation is performed under the condition that a silicon oxide film of a degree is formed. For example, when oxidation is performed in an oxygen atmosphere at about 900 ° C. using a diffusion furnace, as shown in FIG. 9, the surface of the semiconductor substrate 2 (the surfaces of the p-well region 16 and the n-well region 18),
A silicon oxide film 26a of about 20 ° is formed on the upper surface of the gate pattern 22 (polysilicon film 22a), and a silicon oxide film 26b of about 50 ° is formed on the side wall of the gate pattern 22 at the same time.

At this time, the gate bird's peak formed at the edge end of the gate pattern 22 has the same width as the side wall portion of the gate pattern 22 where nitrogen is not introduced.
A silicon oxide film of about Å is formed. FIG. 13A is a cross-sectional view of the edge end of the gate pattern 22 according to the first embodiment, and FIG. 13B is a cross-sectional view of the edge end of the gate pattern when nitrogen is not introduced. As can be seen from these figures, when nitrogen is introduced on the silicon surface of the semiconductor substrate 2, the oxidized shape is significantly different from that when nitrogen is not introduced, and the amount of oxidation on the silicon surface is greatly reduced. As described above, when thermal oxidation is performed after nitrogen is ion-implanted into the silicon layer, the oxidation of the silicon layer into which nitrogen has been implanted is delayed, so that the thickness of the implanted portion differs from that of the non-implanted portion. Of silicon oxide film can be formed. The reason why the thickness of the silicon oxide film 26b becomes about 50 ° instead of 40 ° is that polysilicon has a higher oxidation rate than single crystal silicon.

Thereafter, arsenic (A) is added to the nMOSFET region.
s), boron (B) is introduced into the pMOSFET region by an ion implantation method. Then, as shown in FIG.
Semiconductor substrate 2 immediately below the sidewall of gate pattern 22
An n ⁻ layer 28 and ap ⁻ layer 30 (shallow diffusion layer) serving as a source or a drain are formed therein, that is, in the semiconductor substrate 2 on both sides of the gate pattern 22. In the formation of the n ⁻ layer 28, As is ion-implanted with an acceleration voltage of about 1 to 15 [keV] and a dose of about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ [cm ⁻² ]. In the formation of the p ⁻ layer 30, BF 2 or B is ion-implanted with an acceleration voltage of about 50 to 500 [eV] and a dose of about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ [cm ⁻² ]. Furthermore, high-speed heating / heating method (RTA method)
The semiconductor substrate is subjected to a heat treatment in a nitrogen atmosphere at about 900 ° C. for 5 seconds.

Subsequently, a silicon oxide film or a silicon nitride film is deposited by LPCVD or plasma CVD to a thickness of about 600 to 1000. Then, as shown in FIG. 11, the silicon oxide film or the silicon nitride film is left only on the side wall portion of the gate pattern 22 by the reactive ion etching method, and the gate side wall film 32 is formed.

Further, As is applied to the nMOSFET region,
B is introduced into the pMOSFET region by ion implantation.
Then, as shown in FIG. 11, both sides of the gate side wall film 32 are formed.
N as a source or a drain in a semiconductor substrate of⁺layer
34 and p⁺A layer 36 (deep diffusion layer) is formed. n⁺layer
In forming 34, As is treated under commonly used conditions, for example,
Using an acceleration voltage of about 10 to 50 [keV], 1 × 10
¹⁵~ 7 × 10¹⁵[Cm^-2] Ion implantation with a dose of about
I do. At this time, the gate pattern (gate electrode) 22 is
In order to lower the resistance, As is also applied to the gate pattern 22.
Inject ON. p ⁺In the formation of the layer 36, B is 3 to 10
Using an acceleration voltage of about [keV], 1 × 10 ¹⁵~ 7 × 1
0¹⁵[Cm^-2] At a dose of about]. That
Later, in order to activate the introduced impurities, for example,
5 seconds at 1000 ° C using high-speed heating and high-temperature method (RTA method)
A degree of heat treatment is performed. This heat treatment allows the gate putter
At the same time, activation of the impurities introduced into the
Depletion of the electrode. Semiconductor that has gone through the steps up to this point
FIG. 11 shows the structure of the body substrate.

Next, a dilute HF process is performed to form an n ⁺ layer 34.
The silicon oxide film 26a on the top, the p ⁺ layer 36, and the gate pattern 22 is removed. Then, the following salicide process is performed. First, cobalt (Co) is formed to a thickness of about 70 ° on the n ⁺ layer 34, the p ⁺ layer 36, and the gate pattern 22 by a sputtering method. Then, 50
By performing a heat treatment in a nitrogen atmosphere at 0 ° C. for about 60 seconds, a silicidation reaction is caused, and as shown in FIG. 12, the n ⁺ layer 34, the p ⁺ layer 36, and the gate pattern 22 are formed. A cobalt monosilicide film 38 is formed. Thereafter, unreacted cobalt is removed by a mixed solution of a hydrogen peroxide solution and sulfuric acid. Further, by performing a heat treatment in a nitrogen atmosphere at 700 ° C. for 60 seconds, the cobalt monosilicide film 38 undergoes a phase transition to reduce the resistance. FIG. 12 shows the structure of the semiconductor substrate having undergone the above steps.
Shown in

Here, the results of comparison of the roughness between silicon and the cobalt silicide film 38 on the n ⁻ layer 28, the p ⁻ layer 30, and the gate pattern 22 are compared between when nitrogen is introduced and when nitrogen is not introduced. I found out the following.
In the evaluation method, after the cobalt silicide film is selectively removed, the silicon surface is measured using an atomic force microscope. Then, as shown in FIG. 14A, the average roughness size was smaller when nitrogen was introduced than when nitrogen was not introduced. Further, as shown in FIG. 14 (b), the maximum difference between the peaks and valleys on the silicon surface was smaller than that without nitrogen. That is, it has been found that when nitrogen ions are implanted, the interface between the cobalt silicide layer and the silicon layer becomes extremely flat due to nitrogen remaining in the silicon substrate 2. The nitrogen remaining up to the silicide process is
It was found that the silicidation reaction was delayed and the interface was flattened. It is considered that the remaining nitrogen was deposited at the silicon substrate interface.

Thereafter, a silicon oxide film serving as an interlayer insulating film is deposited by a commonly used method. Further, a wiring is formed in the MOSFET by using a commonly used method such as opening a contact hole in the interlayer insulating film and embedding a metal in the contact hole, thereby forming a CMOS.
An LSI is formed.

In such a method of manufacturing a semiconductor device, after forming the gate electrode of polysilicon, before performing post-oxidation, which is a step necessary to ensure the reliability of the gate insulating film, nitrogen is added to the semiconductor substrate. By ion implantation
The oxidation rate on the silicon substrate surface in the post-oxidation step is reduced. On the other hand, since nitrogen is not introduced into the side wall of the gate electrode by the ion implantation, the oxidation rate of the side wall does not decrease but is oxidized at a normal oxidation rate. Thereby, an oxidation process having anisotropy can be realized. Therefore, by the same oxidation process, the thickness of the oxide film formed on the surface of the silicon substrate can be reduced, and the thickness of the oxide film formed on the side wall of the gate electrode can be formed thicker than the oxide film on the surface of the silicon substrate. . This allows
A preferable structure in the ion implantation step required for forming the source and drain diffusion layers, that is, the oxide film on the surface of the semiconductor substrate has a small thickness, while the oxide film on the side wall of the gate electrode has a large thickness. It becomes possible. By using this manufacturing method, it is possible to cope with a shallow diffusion layer (shallow junction) which is essential for realizing a miniaturized CMOSFET.
In addition, a semiconductor device which can ensure reliability such as a withstand voltage of a gate insulating film can be formed.

As described above, according to the first embodiment, a thin oxide film is formed on the silicon substrate surface by the same thermal oxidation process before the ion implantation process for forming the source and drain diffusion layers. In addition, a method for manufacturing a semiconductor device which can cope with miniaturization can be provided because an oxide film having a thickness sufficient to secure reliability can be formed on the side wall of the gate electrode and the edge of the gate edge.

Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described.

FIGS. 1 to 6 and FIGS. 15 to 21 are sectional views of a semiconductor device in respective steps showing a method of manufacturing a semiconductor device according to the second embodiment.

1 to 6 as in the first embodiment.
After forming an element isolation region on a semiconductor substrate by using the process shown in (1), a p-well and an n-well are formed, and ions are implanted into a channel.

Thereafter, the silicon oxide film 14 as the dummy gate insulating film is peeled off using a dilute HF solution.
As shown in FIG. 5, a silicon oxide film 40a to be a part of the gate insulating film is formed to a thickness of about 5 ° on the element region by a thermal oxidation method. The formation of the silicon oxide film 40a is performed in an oxygen atmosphere at about 800 ° C. by using the RTA method. Further, a silicon nitride film 40b to be a part of the gate insulating film is formed on the silicon oxide film 40a by LPCVD or JVD (Jet Vapor Deposition) to a thickness of about 20 °. Normally, after the silicon nitride film 40b is formed, electron traps existing between the silicon nitride film 40b, or between the silicon nitride film 40b and the silicon oxide film 40a, and an interface state are reduced to 700 nm in a nitrogen (NO) gas. ~
Heat treatment is performed at a temperature of 900 ° C.

After the formation of the gate insulating film, a polysilicon film (or an amorphous silicon film) having a thickness of about 500 to 1000 ° is deposited by LPCVD. further,
A resist pattern for processing a gate pattern is formed by a photolithography method or an electron beam exposure method. Then, using the resist pattern as a mask, FIG.
As shown in FIG. 3, the gate pattern 4 is formed by a reactive ion etching method using a halide as an etching gas.
Form 2 At this time, the gate pattern 42 to be formed
Is about 0.05 to 0.25 μm. At this time, the etching condition of the gate pattern 42 is a condition having a selectivity with respect to the silicon nitride film 40 b, so that the silicon nitride film 40 b remains on the semiconductor substrate 2. Therefore, in order to remove the silicon nitride film 40b before performing the post-oxidation, as shown in FIG. 17, the silicon nitride film 4b on the semiconductor substrate 2 is heated using phosphoric acid (hot phosphoric acid).
0b is selectively removed. Further, the silicon oxide film 40a on the p-well region 16 and the n-well region 18 is removed. Thereafter, the resist pattern is stripped.

Next, as shown in FIG. 17, a nitrogen atom (mass number 14) or a nitrogen molecule (mass number 28) is selected as an ion source by an ion implantation method, and an acceleration voltage of about 10 keV is used. 1 × 10 ^{14 -1} × 10 ¹⁵ [cm ^-2 ]
Ion implantation is performed at a dose of about the same. As described above, after nitrogen is introduced into the substrate 2 by ion implantation, a predetermined condition, in this case, 4
Oxidation is performed under the condition that a silicon oxide film of about 0 ° is formed. For example, when oxidation is performed in an oxygen atmosphere at about 900 ° C. using a diffusion furnace, as shown in FIG. 18, the surface of the semiconductor substrate 2 (the surfaces of the p-well region 16 and the n-well region 18) and the gate pattern 42 A silicon oxide film 44a of about 20 ° is formed on the upper surface, and at the same time, a silicon oxide film 44 of about 50 ° is formed on the side wall of the gate pattern 42.
b is formed.

At this time, at the gate bird's peak formed at the edge end of the gate pattern 42, as in the case of the side wall portion of the gate pattern 22 into which nitrogen is not introduced, 50%.
A silicon oxide film of about Å is formed. FIG. 22A is a cross-sectional view of the edge end of the gate pattern 42 according to the second embodiment, and FIG. 22B is a cross-sectional view of the edge end of the gate pattern when nitrogen is not introduced. As can be seen from these figures, when nitrogen is introduced on the silicon surface of the semiconductor substrate 2, the oxidized shape is significantly different from that when nitrogen is not introduced, and the amount of oxidation on the silicon surface is greatly reduced. As described above, when thermal oxidation is performed after nitrogen is ion-implanted into the silicon layer, the oxidation of the silicon layer into which nitrogen has been implanted is delayed, so that the thickness of the implanted portion differs from that of the non-implanted portion. Of silicon oxide film can be formed. The reason why the thickness of the silicon oxide film 44b becomes about 50 ° instead of 40 ° is that polysilicon has a higher oxidation rate than single crystal silicon.

Thereafter, arsenic (A) is added to the nMOSFET region.
s), boron (B) is introduced into the pMOSFET region by an ion implantation method. And, as shown in FIG.
An n ⁻ layer 46 and ap ⁻ layer 48 (shallow diffusion layer) to be a source or a drain are formed in the semiconductor substrate 2 on both sides of the gate pattern 42. In forming the n ⁻ layer 46, As is
An acceleration voltage of about 1 to 15 [keV] is used and 1 × 10 ¹⁴
Ion implantation is performed at a dose of about 1 × 10 ¹⁵ [cm ⁻² ]. In forming the p ⁻ layer 48, BF 2 or B is
Using an acceleration voltage of about 500 [eV], 1 × 10 ¹⁴ to
Ion implantation is performed at a dose of about 1 × 10 ¹⁵ [cm ⁻² ]. Further, the semiconductor substrate is subjected to a heat treatment at 900 ° C. for 5 seconds by using a high-speed elevated temperature method (RTA method).

Then, a silicon oxide film or a silicon nitride film is deposited by LPCVD or plasma CVD to a thickness of about 600 to 1000. Then, as shown in FIG. 20, a silicon oxide film or a silicon nitride film is left only on the side wall portion of the gate pattern 42 by a reactive ion etching method, and a gate side wall film 50 is formed.

Further, As is applied to the nMOSFET region,
B is introduced into the pMOSFET region by ion implantation.
Then, as shown in FIG. 20, both sides of the gate side wall film 50 are formed.
N as a source or a drain in a semiconductor substrate of⁺layer
52 and p⁺A layer 54 (deep diffusion layer) is formed. n⁺layer
In the formation of 52, As is converted to a condition usually used, for example,
Using an acceleration voltage of about 10 to 50 [keV], 1 × 10
¹⁵~ 7 × 10¹⁵[Cm^-2] Ion implantation with a dose of about
I do. At this time, the gate pattern (gate electrode) 42 is
In order to lower the resistance, As is also applied to the gate pattern 42.
Inject ON. p ⁺In the formation of the layer 54, B is 3 to 10
Using an acceleration voltage of about [keV], 1 × 10¹⁵~ 7 × 1
0¹⁵[Cm^-2] At a dose of about]. That
Later, in order to activate the introduced impurities, for example,
5 seconds at 1000 ° C using high-speed heating and high-temperature method (RTA method)
A degree of heat treatment is performed. This heat treatment allows the gate putter
At the same time, the impurities introduced into the
Depletion of the electrode. Semiconductor that has gone through the steps up to this point
FIG. 20 shows the structure of the body substrate.

Next, a dilute HF treatment is performed to obtain an n ⁺ layer 52.
The silicon oxide film 44a on the top, the p ⁺ layer 54, and the gate pattern 42 is removed. Then, the following salicide process is performed. First, cobalt (Co) is formed to a thickness of about 70 ° on the n ⁺ layer 52, the p ⁺ layer 54, and the gate pattern 42 by a sputtering method. Then, 50
By performing a heat treatment for about 60 seconds in a nitrogen atmosphere at 0 ° C., a silicidation reaction is caused. As shown in FIG. 21, on the n ⁺ layer 52, the p ⁺ layer 54, and the gate pattern 42, A cobalt monosilicide film 56 is formed. Thereafter, unreacted cobalt is removed by a mixed solution of a hydrogen peroxide solution and sulfuric acid. Further, by performing a heat treatment in a nitrogen atmosphere at 700 ° C. for 60 seconds, the cobalt monosilicide film 56 undergoes a phase transition to reduce the resistance. FIG. 21 shows the structure of the semiconductor substrate that has undergone the above steps.
Shown in

Here, the roughness between the silicon and the cobalt silicide film 56 on the n ⁺ layer 52, the p ⁺ layer 54, and the gate pattern 42 was compared between the case where nitrogen was introduced and the case where nitrogen was not introduced. The result was the same as in the first embodiment. That is, it has been found that when nitrogen ions are implanted, the interface between the cobalt silicide layer and the silicon layer becomes extremely flat due to nitrogen remaining in the silicon substrate. It has been found that nitrogen remaining up to the silicide step has an effect of delaying the silicidation reaction and flattens the interface. It is considered that the remaining nitrogen was deposited at the silicon substrate interface.

Thereafter, a silicon oxide film serving as an interlayer insulating film is deposited by a commonly used method. Further, a wiring is formed in the MOSFET by using a commonly used method such as opening a contact hole in the interlayer insulating film and embedding a metal in the contact hole, thereby forming a CMOS.
An LSI is formed.

In such a method of manufacturing a semiconductor device, after the polysilicon gate electrode is formed, nitrogen is added to the semiconductor substrate before the post-oxidation, which is a step necessary to ensure the reliability of the gate insulating film, is performed. By ion implantation
The oxidation rate on the silicon substrate surface in the post-oxidation step is reduced. On the other hand, since nitrogen is not introduced into the side wall of the gate electrode by the ion implantation, the oxidation rate of the side wall does not decrease but is oxidized at a normal oxidation rate. Thereby, an oxidation process having anisotropy can be realized. Therefore, by the same oxidation process, the thickness of the oxide film formed on the surface of the silicon substrate can be reduced, and the thickness of the oxide film formed on the side wall of the gate electrode can be formed thicker than the oxide film on the surface of the silicon substrate. . This allows
A preferable structure in the ion implantation step required for forming the source and drain diffusion layers, that is, the oxide film on the surface of the semiconductor substrate has a small thickness, while the oxide film on the side wall of the gate electrode has a large thickness. It becomes possible. By using this manufacturing method, it is possible to cope with a shallow diffusion layer (shallow junction) which is essential for realizing a miniaturized CMOSFET.
In addition, a semiconductor device which can ensure reliability such as a withstand voltage of a gate insulating film can be formed.

As described above, according to the second embodiment, a thin oxide film is formed on the silicon substrate surface by the same thermal oxidation process before the ion implantation process for forming the source and drain diffusion layers. In addition, a method for manufacturing a semiconductor device which can cope with miniaturization can be provided because an oxide film having a thickness sufficient to secure reliability can be formed on the side wall of the gate electrode and the edge of the gate edge.

Next, a method of manufacturing a semiconductor device according to the third embodiment of the present invention will be described.

FIGS. 1 to 9 and FIGS. 23 to 26 are sectional views of a semiconductor device in respective steps showing a method of manufacturing a semiconductor device according to the third embodiment.

As in the first embodiment, FIGS.
After forming an element isolation region and forming a gate insulating film by using the process shown in FIG. 8, a gate pattern 22 is formed as shown in FIG. At this time, the size of the formed gate pattern 22 is about 0.05 to 0.25 μm. Further, the silicon oxide film 20 on the p-well region 16 and the n-well region 18 is removed. After that, the resist pattern 24 is peeled off.

Next, as shown in FIG. 8, a nitrogen atom (mass number 14) or a nitrogen molecule (mass number 28) is selected as an ion source by an ion implantation method, and an acceleration voltage of about 10 [keV] is used. Ion implantation is performed at a dose of about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ [cm ⁻² ]. As described above, after nitrogen is introduced into the substrate 2 by the ion implantation method, under predetermined conditions,
In this case, 40 ° on a silicon substrate into which nitrogen has not been introduced.
Oxidation is performed under the condition that a silicon oxide film of a degree is formed. For example, when oxidation is performed in an oxygen atmosphere at about 900 ° C. using a diffusion furnace, as shown in FIG. 9, the surface of the semiconductor substrate 2 (the surfaces of the p-well region 16 and the n-well region 18),
A silicon oxide film 26a of about 20 ° is formed on the upper surface of the gate pattern 22 (polysilicon film 22a), and a silicon oxide film 26b of about 50 ° is formed on the side wall of the gate pattern 22 at the same time.

At this time, at the gate bird's peak formed at the edge end of the gate pattern 22, the first
In this embodiment, a silicon oxide film of about 50 ° is formed in the same manner as the side wall portion of the gate pattern 22 into which nitrogen is not introduced. That is, when nitrogen is introduced on the silicon surface of the semiconductor substrate 2, the oxidized shape is greatly different from that when nitrogen is not introduced, and the amount of oxidation on the silicon surface is greatly reduced. As described above, when thermal oxidation is performed after nitrogen is ion-implanted into the silicon layer, the oxidation of the silicon layer into which nitrogen has been implanted is delayed, so that the thickness of the implanted portion differs from that of the non-implanted portion. Of silicon oxide film can be formed. The silicon oxide film 2
The reason why the film thickness of 6b becomes about 50 ° instead of 40 ° is that polysilicon has a higher oxidation rate than single crystal silicon.

Thereafter, as shown in FIG. 23, the silicon oxide film 26a formed on the surface of the semiconductor substrate 2 and the upper surface of the gate pattern 22 is removed using a dilute HF solution. At this time, even if the silicon oxide film 26a on the surface of the semiconductor substrate 2 is removed by the dilute HF treatment, the silicon oxide film 26b still remains on the side surface of the gate pattern 22, so that the gate breakdown voltage does not deteriorate.

Further, arsenic (A)
s), boron (B) is introduced into the pMOSFET region by an ion implantation method. Then, as shown in FIG.
An n ⁻ layer 58 and a p ⁻ layer 60 (shallow diffusion layer) to be a source or a drain are formed in the semiconductor substrate 2 on both sides of the gate pattern 22. At this time, when the dilute HF treatment is performed, the silicon oxide film does not exist on the surface of the semiconductor substrate 2, or even if it exists, its thickness is reduced to 5 ° or less (the thickness of the natural oxide film). Therefore, subsequent ion implantation for forming a shallow diffusion layer (shallow junction) can be performed under the following conditions. n ^- layer 58
Is formed by ion-implanting As with an acceleration voltage of about 0.5 [keV] and a dose of about 1 × 10 ¹⁵ [cm ⁻² ]. In the formation of the p ⁻ layer 60, B is set to 0.1 [ke].
V] with an acceleration voltage of about 1 × 10 ¹⁵ [cm ⁻² ]. Thereafter, the semiconductor substrate is heat-treated for 5 seconds in a nitrogen atmosphere at about 900 ° C. by using a high-speed high-temperature method (RTA method).

Subsequently, a silicon oxide film or a silicon nitride film is deposited by LPCVD or plasma CVD to a thickness of about 600 to 1000 膜厚. Then, as shown in FIG. 25, a silicon oxide film or a silicon nitride film is left only on the side wall portion of the gate pattern 22 by a reactive ion etching method to form a gate side wall film 62.

Further, As is applied to the nMOSFET region,
B is introduced into the pMOSFET region by ion implantation.
Then, as shown in FIG. 25, both sides of the gate side wall film 62 are formed.
N as a source or a drain in a semiconductor substrate of⁺layer
64 and p⁺A layer 66 (deep diffusion layer) is formed. n⁺layer
In forming 64, As is treated under commonly used conditions, for example,
Using an acceleration voltage of about 10 to 50 [keV], 1 × 10
¹⁵~ 7 × 10¹⁵[Cm^-2] Ion implantation with a dose of about
I do. At this time, the gate pattern (gate electrode) 42 is
In order to lower the resistance, As is also applied to the gate pattern 42.
Inject ON. p ⁺In the formation of the layer 66, B is 3 to 10
Using an acceleration voltage of about [keV], 1 × 10 ¹⁵~ 7 × 1
0¹⁵[Cm^-2] At a dose of about]. That
Later, in order to activate the introduced impurities, for example,
5 seconds at 1000 ° C using high-speed heating and high-temperature method (RTA method)
A degree of heat treatment is performed. This heat treatment allows the gate putter
At the same time, activation of the impurities introduced into the
Depletion of the electrode. Semiconductor that has gone through the steps up to this point
FIG. 25 shows the structure of the body substrate.

Thereafter, the following salicide process is performed.
U. First, n ⁺Layer 64, p⁺layer
66 and on the gate pattern 22
Is formed to a thickness of about 70 °. Subsequently, a nitrogen atmosphere of 500 ° C.
By performing heat treatment for about 60 seconds in the air,
A dating reaction was caused to occur, as shown in FIG.⁺
On layer 64, p⁺On the layer 66 and on the gate pattern 22
A cobalt monosilicide film 68 is formed. Then
Unreacted cobalt is removed by a mixed solution of hydrogen oxide water and sulfuric acid.
Remove. Further, in a nitrogen atmosphere at 700 ° C.,
By performing a heat treatment for 60 seconds, the cobalt monolith
The resistance of the reside film 68 is reduced by phase transition. So far
FIG. 26 shows the structure of the semiconductor substrate having undergone the step of FIG.

Here, the roughness of silicon and the cobalt silicide film 68 on the n ⁺ layer 64, the p ⁺ layer 66, and the gate pattern 22 was compared between the case where nitrogen was introduced and the case where nitrogen was not introduced. The result was the same as in the first embodiment. That is, it has been found that when nitrogen ions are implanted, the interface between the cobalt silicide layer and the silicon layer becomes extremely flat due to nitrogen remaining in the silicon substrate. It has been found that nitrogen remaining up to the silicide step has an effect of delaying the silicidation reaction and flattens the interface. It is considered that the remaining nitrogen was deposited at the silicon substrate interface.

Thereafter, a silicon oxide film as an interlayer insulating film is deposited by a commonly used method. Further, a wiring is formed in the MOSFET by using a commonly used method such as opening a contact hole in the interlayer insulating film and embedding a metal in the contact hole, thereby forming a CMOS.
An LSI is formed.

In such a method of manufacturing a semiconductor device, after forming the gate electrode of polysilicon, before performing post-oxidation, which is a step necessary to secure the reliability of the gate insulating film, nitrogen is added to the semiconductor substrate. By ion implantation
The oxidation rate on the silicon substrate surface in the post-oxidation step is reduced. On the other hand, since nitrogen is not introduced into the side wall of the gate electrode by the ion implantation, the oxidation rate of the side wall does not decrease but is oxidized at a normal oxidation rate. Thereby, an oxidation process having anisotropy can be realized. Therefore, by the same oxidation process, the thickness of the oxide film formed on the surface of the silicon substrate can be reduced, and the thickness of the oxide film formed on the side wall of the gate electrode can be formed thicker than the oxide film on the surface of the silicon substrate. .

Thereafter, the oxide film on the surface of the silicon substrate is removed by using a dilute HF treatment, and the thickness of the oxide film existing on the surface of the silicon substrate is reduced to the thickness of a natural oxide film (5 ° or less). Thereby, a preferable structure in the ion implantation step required for forming the source and drain diffusion layers, that is, the thickness of the oxide film on the surface of the semiconductor substrate is extremely small, while the thickness of the oxide film on the side wall of the gate electrode is large. It can be formed. Therefore, it is possible to perform ion implantation for forming a shallow diffusion layer at a lower acceleration voltage than in the first embodiment. Note that even if the oxide film on the surface of the silicon substrate is removed using the dilute HF treatment, the silicon oxide film remains on the side surface of the gate electrode, so that the gate breakdown voltage does not deteriorate. If such a manufacturing method is used, finer CM
A semiconductor device can be formed which can cope with a shallow diffusion layer (shallow junction) which is indispensable for realizing an OSFET, and which can secure reliability such as a dielectric strength of a gate insulating film.

As described above, according to the third embodiment, before the ion implantation step for forming the source and drain diffusion layers, the oxide film on the surface of the silicon substrate can be removed or extremely thinned, and the gate electrode can be removed. Since an oxide film having a thickness sufficient to ensure reliability can be formed on the side wall and the edge of the gate edge, a method for manufacturing a semiconductor device which can cope with miniaturization can be provided.

Next, a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described.

FIGS. 1 to 7 and FIGS. 27 to 32 are sectional views of a semiconductor device in respective steps showing a method of manufacturing a semiconductor device according to the fourth embodiment.

FIGS. 1 to 7 similarly to the first embodiment.
After forming an element isolation region and forming a gate insulating film using the process shown in FIG. 27, a gate pattern 22 is formed as shown in FIG. At this time, the size of the formed gate pattern 22 is about 0.05 to 0.25 μm.
Further, the silicon oxide film 20 on the p-well region 16 and the n-well region 18 is removed. After that, the resist pattern 24 is peeled off.

Next, as shown in FIG. 27, a carbon atom (C) was selected as an ion source by an ion implantation method, and 1 [k
Using an acceleration voltage of about eV], ions are implanted at a dose of about 5 × 10 ¹⁴ [cm ⁻² ]. After the carbon is introduced into the substrate 2 by the ion implantation method, a heat treatment is performed in a nitrogen atmosphere at about 800 ° C. for 10 seconds. And FIG.
As shown in FIG. 8, a silicon carbide (SiC) layer 70 is formed in a region on the surface of the silicon substrate 2 into which carbon has been ion-implanted. Here, when photoelectron spectroscopy analysis was performed, a bond between silicon atoms and carbon atoms was observed on the silicon substrate surface.

Subsequently, thermal oxidation is performed for 10 minutes in a diluted oxygen atmosphere at about 800 ° C. using a diffusion furnace. Then, as shown in FIG. 29, the surface of the semiconductor substrate 2 (p well region 1)
A silicon oxide film 72a of about 15 ° is formed on the upper surface of the gate pattern 22 (polysilicon film 22a) and the upper surface of the gate pattern 22. At the same time, a silicon oxide film 72 of about 50 ° is formed on the side wall of the gate pattern 22.
b is formed.

At this time, at the gate bird's peak formed at the edge end of the gate pattern 22, as in the case of the side wall portion of the gate pattern 22 into which carbon is not introduced, 50%.
A silicon oxide film of about Å is formed. FIG. 33A is a sectional view of the edge end of the gate pattern 22 according to the fourth embodiment, and FIG. 33B is a sectional view of the edge end of the gate pattern when carbon is not introduced. As can be seen from these figures, when carbon is introduced on the silicon surface of the semiconductor substrate 2, the oxidized shape is significantly different from that when carbon is not introduced, and the amount of oxidation on the silicon surface is greatly reduced. As described above, if thermal oxidation is performed after carbon is ion-implanted into the silicon layer, the oxidation of the silicon layer into which carbon has been implanted is delayed, so that the thickness of the implanted portion and that of the non-implanted portion are different. Of silicon oxide film can be formed.

Here, carbon is introduced by the ion implantation method, but carbon can be introduced into the silicon substrate also by a plasma process using an organic substance containing carbon as a source gas. Further, the oxide film thickness on the silicon substrate surface was reduced from 40 ° when carbon was not introduced to 15 ° by the carbon ion implantation in the above-described process and the thermal oxidation for 10 minutes in a diluted oxygen atmosphere at about 800 ° C. The reason why the thickness of the silicon oxide film 72b becomes about 50 ° instead of 40 ° is that polysilicon has a higher oxidation rate than single crystal silicon.

Thereafter, arsenic (A) is added to the nMOSFET region.
s), boron (B) is introduced into the pMOSFET region by an ion implantation method. Then, as shown in FIG.
An n ⁻ layer 74 and ap ⁻ layer 76 (shallow diffusion layer) serving as a source or a drain are formed in the semiconductor substrate 2 on both sides of the gate pattern 22. In forming the n ⁻ layer 74, As is set to 3
Using an acceleration voltage of about [keV], 5 × 10 ¹⁴ [c
[m ⁻² ]. In the formation of the p ⁻ layer 76, B is accelerated using an acceleration voltage of about 300 [eV].
Ion implantation is performed at a dose of about 5 × 10 ¹⁴ [cm ⁻² ]. Further, using a high-speed heating and high-temperature method (RTA method),
The semiconductor substrate is heat-treated in a nitrogen atmosphere at about 0 ° C. for 5 seconds.

Subsequently, a silicon oxide film or a silicon nitride film is deposited to a thickness of about 500.degree. By LPCVD or plasma CVD. Then, as shown in FIG. 31, a silicon oxide film or a silicon nitride film is left only on the side wall portion of the gate pattern 22 by a reactive ion etching method to form a gate side wall film 78.

Further, As is applied to the nMOSFET region,
B is introduced into the pMOSFET region by ion implantation.
Then, as shown in FIG. 31, both sides of the gate side wall film 78 are formed.
N as a source or a drain in a semiconductor substrate of⁺layer
80 and p⁺A layer 82 (deep diffusion layer) is formed. n⁺layer
In forming 80, As is treated under commonly used conditions, for example,
Using an acceleration voltage of about 10 to 50 [keV], 1 × 10
¹⁵~ 7 × 10¹⁵[Cm^-2] Ion implantation with a dose of about
I do. At this time, the gate pattern (gate electrode) 22 is
In order to lower the resistance, As is also applied to the gate pattern 22.
Inject ON. p ⁺In the formation of the layer 82, B is 3 to 10
Using an acceleration voltage of about [keV], 1 × 10 ¹⁵~ 7 × 1
0¹⁵[Cm^-2] At a dose of about]. That
Later, in order to activate the introduced impurities, for example,
5 seconds at 1000 ° C using high-speed heating and high-temperature method (RTA method)
A degree of heat treatment is performed. This heat treatment allows the gate putter
At the same time, activation of the impurities introduced into the
Depletion of the electrode. Semiconductor that has gone through the steps up to this point
FIG. 31 shows the structure of the body substrate.

Next, a dilute HF process is performed to form the n ⁺ layer 80.
The silicon oxide film 72a on the top, the p ⁺ layer 82, and the gate pattern 22 is removed. After that, by performing a plasma treatment in an oxygen atmosphere, the SiC layer 70 formed on the surface of the silicon substrate 2 is oxidized to remove carbon. By thus transforming the SiC layer 70 insoluble in the diluted HF solution into a silicon oxide film, a dilute HF process, which is a pretreatment of sputtering for forming cobalt silicide described later,
It becomes possible to remove the oxide film on the silicon surface.

After removing the oxide film on the surface of the semiconductor substrate 2,
The following salicide process is performed. First, cobalt (Co) is formed to a thickness of about 70 ° on the n ⁺ layer 80, the p ⁺ layer 82, and the gate pattern 22 by a sputtering method. Subsequently, a heat treatment is performed in a nitrogen atmosphere at 500 ° C. for about 60 seconds to cause a silicidation reaction, and as shown in FIG. 32, on the n ⁺ layer 80 and the p ⁺ layer 82
A cobalt monosilicide film 84 is formed on the upper surface and the gate pattern 22. Thereafter, unreacted cobalt is removed by a mixed solution of a hydrogen peroxide solution and sulfuric acid. In addition, 7
By performing a heat treatment in a nitrogen atmosphere at 00 ° C. for 60 seconds, the cobalt monosilicide film 84 undergoes a phase transition to reduce the resistance. FIG. 32 shows the structure of the semiconductor substrate having undergone the above steps.

Thereafter, a silicon oxide film serving as an interlayer insulating film is deposited by a commonly used method. Further, a wiring is formed in the MOSFET by using a commonly used method such as opening a contact hole in the interlayer insulating film and embedding a metal in the contact hole, thereby forming a CMOS.
An LSI is formed.

In such a method of manufacturing a semiconductor device, after forming a gate electrode of polysilicon, before performing post-oxidation, which is a step necessary to secure the reliability of the gate insulating film, carbon dioxide is added to the semiconductor substrate. By ion implantation of
An iC layer is formed to lower the oxidation rate of the silicon substrate surface in the post-oxidation step. On the other hand, since no carbon is introduced into the side wall of the gate electrode, the side wall is oxidized at a normal oxidation rate. Thereby, an oxidation process having anisotropy can be realized. Therefore, by the same oxidation process, the thickness of the oxide film formed on the surface of the silicon substrate can be reduced, and the thickness of the oxide film formed on the side wall of the gate electrode can be formed thicker than the oxide film on the surface of the silicon substrate. . Thereby, the preferred structure in the ion implantation step required when forming the source and drain diffusion layers, that is, the thickness of the oxide film on the surface of the semiconductor substrate is small,
On the other hand, the thickness of the oxide film on the side wall of the gate electrode can be increased. If this manufacturing method is used, finer CM
A semiconductor device which can cope with a shallow junction which is indispensable for realizing an OSFET and which can secure reliability such as a withstand voltage of a gate insulating film can be formed.

As described above, according to the fourth embodiment, a thin oxide film is formed on the silicon substrate surface by the same thermal oxidation process before the ion implantation process for forming the source and drain diffusion layers. In addition, a method for manufacturing a semiconductor device which can cope with miniaturization can be provided because an oxide film having a thickness sufficient to secure reliability can be formed on the side wall of the gate electrode and the edge of the gate edge.

[0083]

As described above, according to the present invention, a thin oxide film can be formed on the silicon substrate surface by the same thermal oxidation process before the ion implantation process for forming the source and drain diffusion layers. Since an oxide film having a thickness sufficient to ensure reliability can be formed on the gate electrode side wall and the gate edge end, a method for manufacturing a semiconductor device which can cope with miniaturization can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device in a first step showing a method of manufacturing a semiconductor device according to first to fourth embodiments.

FIG. 2 is a cross-sectional view of the semiconductor device in a second step of the method for manufacturing the semiconductor device according to the first to fourth embodiments;

FIG. 3 is a cross-sectional view of the semiconductor device in a third step showing the method of manufacturing the semiconductor device according to the first to fourth embodiments;

FIG. 4 is a cross-sectional view of the semiconductor device in a fourth step of the method for manufacturing the semiconductor device according to the first to fourth embodiments;

FIG. 5 is a cross-sectional view of the semiconductor device in a fifth step showing the method of manufacturing the semiconductor device according to the first to fourth embodiments;

FIG. 6 is a sectional view of the semiconductor device in a sixth step showing the method for manufacturing the semiconductor device of the first to fourth embodiments;

FIG. 7 is a cross-sectional view of the semiconductor device in a seventh step showing the method of manufacturing the semiconductor device according to the first, third, and fourth embodiments.

FIG. 8 is a cross-sectional view of the semiconductor device in an eighth step illustrating the method of manufacturing the semiconductor device according to the first and third embodiments.

FIG. 9 is a cross-sectional view of the semiconductor device in a ninth step showing the method of manufacturing the semiconductor device according to the first and third embodiments.

FIG. 10 is a sectional view of the semiconductor device in a tenth step of the method for manufacturing the semiconductor device according to the first embodiment;

FIG. 11 is a sectional view of the semiconductor device in an eleventh step of the method for manufacturing the semiconductor device according to the first embodiment;

FIG. 12 is a cross-sectional view of the semiconductor device in a twelfth step showing the method for manufacturing the semiconductor device of the first embodiment.

FIG. 13A is a sectional view of an edge end of the gate pattern in the first embodiment, and FIG. 13B is a sectional view of an edge end of the gate pattern when nitrogen is not introduced.

14A is a diagram showing an average roughness of a boundary surface between a silicon layer and a cobalt silicide film in a semiconductor device, and FIG. 14B is a diagram showing a maximum difference between a peak and a valley on the surface of the silicon layer. .

FIG. 15 is a sectional view of the semiconductor device in a seventh step showing the method for manufacturing the semiconductor device of the second embodiment;

FIG. 16 is a sectional view of the semiconductor device in an eighth step showing the method of manufacturing the semiconductor device according to the second embodiment;

FIG. 17 is a cross-sectional view of the semiconductor device in a ninth step showing the method for manufacturing the semiconductor device of the second embodiment.

FIG. 18 is a sectional view of the semiconductor device in a tenth step showing the method for manufacturing the semiconductor device of the second embodiment.

FIG. 19 is a sectional view of the semiconductor device in an eleventh step of the method for manufacturing the semiconductor device according to the third embodiment;

FIG. 20 is a sectional view of the semiconductor device in a twelfth step showing the method for manufacturing the semiconductor device of the fourth embodiment;

FIG. 21 is a sectional view of the semiconductor device in a thirteenth step showing the method for manufacturing the semiconductor device of the fifth embodiment.

FIG. 22A is a sectional view of an edge end of a gate pattern in the second embodiment, and FIG. 22B is a sectional view of an edge end of the gate pattern when nitrogen is not introduced.

FIG. 23 is a cross-sectional view of the semiconductor device in a tenth step showing the method for manufacturing the semiconductor device of the third embodiment.

FIG. 24 is a sectional view of the semiconductor device in an eleventh step of the method for manufacturing the semiconductor device according to the third embodiment;

FIG. 25 is a cross-sectional view of the semiconductor device in a twelfth step showing the method for manufacturing the semiconductor device of the third embodiment.

FIG. 26 is a sectional view of the semiconductor device in a thirteenth step showing the method for manufacturing the semiconductor device of the third embodiment.

FIG. 27 is a sectional view of the semiconductor device in an eighth step showing the method of manufacturing the semiconductor device of the fourth embodiment;

FIG. 28 is a sectional view of the semiconductor device in a ninth step of the method for manufacturing the semiconductor device of the fourth embodiment.

FIG. 29 is a sectional view of the semiconductor device in a tenth step showing the method for manufacturing the semiconductor device of the fourth embodiment;

FIG. 30 is a cross-sectional view of the semiconductor device in an eleventh step of the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 31 is a sectional view of the semiconductor device in a twelfth step showing the method for manufacturing the semiconductor device of the fourth embodiment;

FIG. 32 is a sectional view of the semiconductor device in a thirteenth step showing the method for manufacturing the semiconductor device of the fourth embodiment;

FIG. 33A is a sectional view of an edge end of a gate pattern in the fourth embodiment, and FIG. 33B is a sectional view of an edge end of the gate pattern when nitrogen is not introduced.

34A is a diagram showing a relationship between an acceleration voltage and an average range when arsenic (As) is introduced into silicon by ion implantation, and FIG. 34B is a diagram showing boron (B) in silicon. It is a figure which shows the relationship between the acceleration voltage at the time of introduction, and an average range.

FIG. 35 is a cross-sectional view showing a structure after post-oxidation in a conventional MOSFET manufacturing process.

[Explanation of symbols]

2 ... p-type silicon semiconductor substrate 4 ... silicon oxide film 6 ... silicon nitride film 8 ... resist pattern 10 ... silicon groove 12 ... element isolation region 14 ... silicon oxide film 16 ... p-well region 18 ... n-well region 20 ... silicon oxide film 22 gate pattern (gate electrode) 22a polysilicon film 24 resist pattern 26a silicon oxide film 26b silicon oxide film 28 n ^- layer 30 p ^- layer 32 gate sidewall film 34 n ⁺ layer 36 p ⁺ Layer 38 ... cobalt monosilicide film 40a ... silicon oxide film 40b ... silicon nitride film 42 ... gate pattern 44a ... silicon oxide film 44b ... silicon oxide film 46 ... n ^- layer 48 ... p ^- layer 50 ... gate sidewall film 52 ... n ⁺ Layer 54 ... p ⁺ layer 56 ... cobalt monosilicide film 58 ... n ^- layer 60 ... p ^- layer 62 ... gate sidewall film 64 ... n ⁺ layer 66 ... p ⁺ layer 68 ... cobalt monosilicide film 70 ... SiC layer 72a ... silicon oxide film 72b ... silicon oxide film 74 ... n ^- layer 76 ... p ^- layer 78 ... gate sidewall film 80 ... n ⁺ layer 82 ... p ⁺ layer 84 ... cobalt monosilicide film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/336 H01L 29/78 301P 301S F term (Reference) 4M104 AA01 BB01 BB20 CC01 CC05 DD03 DD04 DD37 DD65 DD80 DD84 DD88 DD89 EE03 EE12 EE17 FF14 GG10 HH14 5F040 DA19 DB03 DC01 EC01 EC04 EC07 EC13 ED01 ED05 EF02 EF11 EH02 EK05 FA03 FA05 FA07 FA16 FA19 FB02 FB04 FC00 FC04 FC10 FC15 FC19 5F048 AA07 AC03 BA01 BB05 BB05 DA02

Claims (15)

[Claims] A step of forming a gate insulating film on a silicon semiconductor substrate; a step of forming a gate electrode on the gate insulating film; and delaying oxidation of silicon in the semiconductor substrate on both sides of the gate electrode. After the step of introducing an element and the step of introducing the element, thermal oxidation is performed to form a first silicon oxide film on the semiconductor substrate, and at the same time, the first silicon oxide film is formed on a sidewall of the gate electrode. Forming a second silicon oxide film thicker than a film; and forming a diffusion layer serving as a source or a drain in the semiconductor substrate on both sides of the gate electrode. A method for manufacturing a semiconductor device. 2. A step of forming a gate insulating film in which a silicon oxide film and a silicon nitride film are stacked in this order on a silicon semiconductor substrate; a step of forming a gate electrode on the gate insulating film; Removing the silicon nitride film formed on the semiconductor substrate on both sides of the gate electrode; introducing an element that delays oxidation of silicon into the semiconductor substrate on both sides of the gate electrode; and introducing the element Thereafter, thermal oxidation is performed to form a first silicon oxide film on the semiconductor substrate, and at the same time, a second silicon oxide film having a thickness larger than the first silicon oxide film on the side wall of the gate electrode. Forming a diffusion layer serving as a source or a drain in the semiconductor substrate on both sides of the gate electrode. Method. 3. A step of forming a gate insulating film on a silicon semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and delaying oxidation of silicon in the semiconductor substrate on both sides of the gate electrode. After the step of introducing an element and the step of introducing the element, thermal oxidation is performed to form a first silicon oxide film on the semiconductor substrate, and at the same time, the first silicon oxide film is formed on a sidewall of the gate electrode. Forming a second silicon oxide film having a thickness greater than that of the film; removing the first silicon oxide film on the semiconductor substrate; and simultaneously forming the second silicon oxide film on a side wall of the gate electrode. And a step of forming a diffusion layer serving as a source or a drain in the semiconductor substrate on both sides of the gate electrode. . 4. A step of forming a gate insulating film on a silicon semiconductor substrate; a step of forming a gate electrode made of silicon on the gate insulating film; A step of introducing an element that delays the oxidation of silicon over the gate electrode; and a step of introducing the element, and then performing thermal oxidation to form a first silicon oxide film over the semiconductor substrate and over the gate electrode. Simultaneously forming a second silicon oxide film having a thickness greater than that of the first silicon oxide film on the side wall of the gate electrode; and forming a second source or drain in the semiconductor substrate on both sides of the gate electrode. After the step of forming the first diffusion layer and the step of forming the first diffusion layer, an insulating film is deposited, and the insulating film is left only on the side wall of the gate electrode. Forming a side wall film; forming a second diffusion layer deeper than the first diffusion layer serving as a source or a drain in the semiconductor substrate on both sides of the gate side wall film; Removing the first silicon oxide film on the upper and gate electrodes; forming a refractory metal film on the second diffusion layer and the gate electrode; silicidizing the refractory metal to form the refractory metal; Forming a metal silicide film on the second diffusion layer and the gate electrode. 5. A step of forming an element isolation region for partitioning an element region on a silicon semiconductor substrate; a step of forming a p-well region and an n-well region in the element region of the semiconductor substrate; Forming a gate insulating film thereon; forming a gate electrode made of silicon on the gate insulating film; in the p-well region and the n-well region on both sides of the gate electrode; A step of introducing an element that delays oxidation of silicon; and a step of performing a thermal oxidation after the step of introducing the element to form a first silicon oxide film on the p-well region, the n-well region, and the gate electrode. Forming a second silicon oxide film thicker than the first silicon oxide film on the side wall of the gate electrode at the same time; and forming the p on both sides of the gate electrode. A step of forming a shallow diffusion layer serving as a source or a drain in a well region and an n-well region; and a step of forming the shallow diffusion layer. After that, an insulating film is deposited, and the insulating film is formed only on sidewalls of the gate electrode. Forming a gate side wall film while leaving a deep diffusion layer serving as a source or a drain in the p well region and the n well region on both sides of the gate side wall film; Removing the first silicon oxide film on the gate electrode; forming a refractory metal film on the deep diffusion layer and the gate electrode; siliciding the refractory metal to form the deep diffusion layer Forming a metal silicide film on the gate electrode and on the gate electrode. 6. The method according to claim 1, wherein the gate electrode is made of a polysilicon film. 7. The method according to claim 1, wherein the gate electrode is made of an amorphous silicon film. 8. The method according to claim 1, wherein the element in the step of introducing the element is nitrogen.
5. A method for manufacturing a semiconductor device according to any one of the above. 9. The method according to claim 8, wherein the nitrogen is introduced by an ion implantation method. 10. The implantation conditions in the ion implantation method include an acceleration voltage of about 10 keV and a dose of 1 × 1.
The method for manufacturing a semiconductor device according to claim 9, wherein the value is about 0 ¹⁴ to 1 × 10 ¹⁵ [cm ⁻² ]. 11. The method according to claim 9, wherein the thermal oxidation performed after the step of introducing the element is performed in an oxygen atmosphere at about 900 ° C. 12. The method according to claim 1, wherein the element in the step of introducing the element is carbon. 13. The method according to claim 12, wherein the carbon is introduced by an ion implantation method. 14. An ion implantation method according to claim 1, wherein an acceleration voltage is about 1 keV and a dose is 5 × 10 5.
^{14. The} method according to claim 13, wherein the pressure is about ¹⁴ [cm ^-2 ]. 15. A step of forming a gate insulating film on a silicon semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a step of introducing carbon into the semiconductor substrate on both sides of the gate electrode. After the step of introducing carbon, a heat treatment is performed to form a silicon carbide layer on the semiconductor substrate; and, after the step of forming the silicon carbide layer, thermal oxidation is performed. Forming a first silicon oxide film on the upper portion, and simultaneously forming a second silicon oxide film thicker than the first silicon oxide film on a side wall of the gate electrode; Forming a diffusion layer serving as a source or a drain in the semiconductor substrate.