544859544859
B 五、發％說明： 發明領域： ?-c閲讀背面之注意事項再填寫本頁 本發明係有關於一種半導體元件之製造方法，特別 是有關於一種具有凹陷之自行對準的金屬矽ί匕物接點及 延伸源沒極接面（extended source/drain junctions)之金氧 半場效電晶體（Metal Oxide Semiconductor Field Effect Transistor; MOSFET)的製造方法。 發明背景： 自從第一個積體電路於西元1960年首先發明以來， 半導體製程中單一晶片上的元件數目，即以爆炸性的速 度快速成長，隨著現階段的半導體製程技術已邁入超大 型積體電路（ultra large scale integration; ULSI)、甚至更 高密度的時代，單一晶片上的元件數目也由以往的數千 個元件，增加至數百萬個元件，甚至可達到單一晶片上 製作數千萬個或是更多個元件的程度。 經濟部中央標準局員工消费合作杜印製 單一晶片上元件數目的大幅增加，形成對半導體製 程技術的一大挑戰，每一個半導體元件皆必須在不影響 其功能的前提下，進一步縮減其尺寸或占用的面積，而 在更高的積集度（packing density)之下，整體元件或電路 之功能仍須維持不變、甚至必須具有更好的可靠度、工 作壽命、並同時加入低功率消耗及低發熱率的特性。因 此半導體製程中的製程技術，諸如微影、蝕刻、沈積、 離子佈植等等的主要製程技術，必須同時的研究與發 木紙張尺度適；Π屮國S家標準（（、S ) MML格（公t ) 544859 經濟部中央標準局Μ工消费合作社印聚 脊捐説.扣： ' 展，以達成下一代積體電路的發展目標。 在一般的積體電路中，最常被應闬的元件之一即是 具有控制特性的電晶體，尤其是所謂的金氧半場效電晶 禮（MOSF JE T)，隨著元件尺寸的日益縮減，次微米尺寸的 金氧半場效電晶體同時面臨更多的挑戰。當積體電路中 每一個金氧半場效電晶體所占的長度與寬度縮小時，電 晶體的通道長度亦隨之縮減，而導致如墜穿效應、洩漏 電流、接觸電阻等問題的加重，因而降低了半導體製程 的良率及元件的可靠度。 為了發展未來高速度的超大型積體電路（ULSI)、未 來的金氧半場效電晶體，必須使用如自行對準石夕化金屬 接觸、以及極淺的延伸源沒極接面（extended ultrashallow source/drain junction)等技術 ，以 提供更 為提昇 的元件特性。在超大型積體電路（ULSI)或是大型積體電 路（VLSI)的電晶體元件中，自行對準的矽化金屬技術， 是用以提昇微米尺寸元件操作速度的關鍵，但相對來 說，使用自行對準的矽化金屬技術也必須面臨許多的挑 戰。 一般而言，自行對準矽化金屬的技術會導致金屬入 侵半導體基材的現象，而產生接面處洩漏電流的問題； 而於自行對準矽化金屬的過程中，往往會有未完全去除 的金屬層殘餘於閘極兩側的間隙壁上，而導致鄰近區域 間橋接（b r i d g i n g)或短路（s h 〇 r t)等的效應。有關使用自行 對準矽化金屬的技術上負面的效應，可參考C.Y. Lu 等 本紙张尺度適州中國國家標準（CNS ) Λ4現格（公择j ('tT屯閱讀背面之注意事項再填寫本頁)B. V.% Description: Field of the invention:? -C Read the notes on the back and then fill out this page. The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a self-aligned metal silicon with a recess. Method for manufacturing metal oxide semiconductor field effect transistor (MOSFET) of metal contact and extended source / drain junctions. Background of the Invention: Since the first integrated circuit was first invented in 1960, the number of components on a single wafer in the semiconductor process has grown rapidly at an explosive rate. With the current stage of semiconductor process technology, ultra-large In the era of ultra large scale integration (ULSI) and even higher density, the number of components on a single chip has increased from thousands of components in the past to millions of components, and even thousands of components can be fabricated on a single chip 10,000 or more components. The consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs has significantly increased the number of components on a single wafer. This has created a major challenge to semiconductor process technology. Each semiconductor component must be further reduced in size or without affecting its function. The area occupied, and under higher packing density, the function of the overall component or circuit must still remain unchanged, and it must even have better reliability, working life, and at the same time add low power consumption and Low heating rate. Therefore, the process technology in the semiconductor process, such as lithography, etching, deposition, ion implantation, etc., must be studied at the same time as the wood paper size; Π 屮 country standard ((, S) MML grid (Public t) 544859 Yin Juji, the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, said: "Develop to achieve the development goals of the next generation of integrated circuits. In general integrated circuits, the most commonly One of the components is a transistor with control characteristics, especially the so-called metal-oxide-semiconductor field-effect transistor (MOSF JE T). As the size of the element is shrinking, sub-micron-sized metal-oxide-semiconductor transistors are facing more Many challenges. When the length and width of each metal-oxide-semiconductor half-effect transistor in the integrated circuit are reduced, the channel length of the transistor is also reduced, resulting in problems such as fall-through effects, leakage current, and contact resistance. Increase, which reduces the yield of semiconductor processes and the reliability of components. In order to develop future high-speed ultra large integrated circuits (ULSI) and future metal-oxide-semiconductor field-effect transistors, it is necessary to use Self-aligned technologies such as metal contact and ultra-shallow source / drain junction are used to provide improved component characteristics. In ultra-large integrated circuit (ULSI) or Among large-scale integrated circuit (VLSI) transistor components, self-aligned silicide technology is the key to improving the operation speed of micron-sized components, but relatively speaking, the use of self-aligned silicide technology must also face many Generally speaking, the technology of self-aligning metal silicide will cause the metal to invade the semiconductor substrate, which will cause the leakage current at the interface. In the process of self-aligning the metal silicide, there are often incomplete The removed metal layer remains on the gaps on both sides of the gate, causing bridging or short circuit (sh rt) effects between adjacent areas. Technically negative effects of using self-aligned silicide metal can be Refer to CY Lu and other papers in accordance with the Chinese National Standards (CNS) of this paper. Write this page)
544859 經濟部中央標準局K工消费合作社印裂 五、發明説頓 人所發表的研究結果（“Process Limitation and Device Design Tradeoffs of Self-Aligned T i S i、 J u n c Μ ο n Formation in S ubmicrometer CMOS Devices' IEEE Trans. Electron Devices, vol. ED-38，No. 2，1991)，其中提出在 應用自行對準矽化金屬技術與淺接面技術兩者間，在設 計上所需面臨的取捨。 在目前的製程技術之中，自行對準的矽化金屬已應 用於次微米以下的元件中，以增加積體電路的積集度， 並減少内部連接時的電阻，改進其操作速度。上述技術 之相關文獻之一，可參閱由 K· Fujii等人所發表之，，A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM”（1996，IEEE, IEDM 96-451)，在此 文獻中，發現自行對準的石夕化金屬製程中，若使用鹤原 子佔原子百分率約5 °/。的TiW合金作為金屬材料，則對於 閘極寬度為〇 · 1 8微米的元件而言，於熱回火溫度高達攝 氏8 0 0度時，片電阻仍相當低。 至於因為元件尺寸變得越來越小所導致的「短通道 效應」（short channel effect)，可以藉著形成一極淺的延 伸源沒極接面（extended ultra-shallow source/drain j u n c t i ο n s )，而得到改善，有關此部分技術之相關文獻， 可參閱由A. Hori等人所提出之” A O.〇5pm-CMOS with Ultra Shallow S ource/Drain Junctions Fabricated by 5 Ke v Ion Implantation and Rapid Thermal Annealing” （1994, IEEE，IEDM 94-485)。 4 本紙张尺度適用中國國家標苹（CNS )八4規格（210X297公漦） 讀先閱讀背面之注意事項再填寫本頁) ¾衣--- --訂 經濟部中央標準局M工消费合作社印製 544859544859 Printed by the K-Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the People ’s Republic of China 5. Research results published by the people of the invention ("Process Limitation and Device Design Tradeoffs of Self-Aligned T i S i, J unc Μ ο n Formation in S ubmicrometer CMOS Devices' IEEE Trans. Electron Devices, vol. ED-38, No. 2, 1991), which proposes the trade-offs in design that need to be faced between the application of self-aligned metal silicide technology and shallow junction technology. Among current process technologies, self-aligned silicided metals have been used in sub-micron components to increase the integration of integrated circuits, reduce the resistance during internal connections, and improve their operating speed. Related to the above technologies One of the literatures can be found in A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM "(1996, IEEE, IEDM 96-451) published by K. Fujii et al. In the self-aligned metal process of Shixi Chemical, if the crane atom is used, the atomic percentage is about 5 ° /. As a metallic material, for a device with a gate width of 0.18 microns, the sheet resistance is still quite low when the thermal tempering temperature is as high as 800 degrees Celsius. As for the "short channel effect" caused by the component size becoming smaller and smaller, it can be achieved by forming an ultra-shallow source / drain juncti ο ns And improved, related literature on this part of technology can refer to "A O.〇5pm-CMOS with Ultra Shallow S ource / Drain Junctions Fabricated by 5 Ke v Ion Implantation and Rapid Thermal proposed by A. Hori et al." Annealing "(1994, IEEE, IEDM 94-485). 4 This paper size applies to China National Standard Apple (CNS) 8-4 specifications (210X297 cm). Read the precautions on the back before filling in this page.) ¾ Clothing --- --- Printed by the M Industry Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs System
—一 . -« ΐ T 卜 q ρ Ύ ,：j 發明目的及概述： 本發明的主要目的為提供一種形成電晶體之方法。 本發明的另一目的為提供一種形成金氧半場效電晶 體（MOSFETs)的製造方法，以形成具有凹陷之自行對準的 矽化金屬接點及延伸源汲極接面。 本發明的再一目的為提供一種之金氧半場效電晶體 (MOSFETs)的製造方法，以提昇電晶體的操作速度，並改 善次微米及更小尺寸元件中短通道效應的問題。 本發明中形成具有凹陷之自行對準的金屬矽化物接 點及延伸源汲極接面之金氧半場效電晶體的方法，可包 含以下步驟：首先形成隔離區域於基材之上；並形成閘 極絕緣層於基材上；再形成第一導體層於閘極絕緣層 上；接著形成第一介電層於第一導體層上；並去除部分 之第一介電層、第一導體層、及閘極絕緣層，以定義閘 極結構；然後形成熱氧化層於基材上及第一導體層之側 壁上；再形成間隙壁於閘極結構之側壁上；接著去除未 被間隙壁覆蓋之熱氧化層；之後去除基材之部分表面區 域，以形成凹陷區域於基材上未被閘極結構及間隙壁覆 蓋處；並去除第一介電層；再形成第一金屬層於基材上； 然後進行源極/汲極/閘極之離子植入；並進行一熱製程， 以將位於凹陷區域及第一導體層上方之第一金屬層反應 為矽化金屬層；接著去除第一金屬層未反應之部分；並 去除間隙壁；最後進行一離子植入以形成延伸源汲極接 面於基材内熱氧化層下方之區域處。 本紙張尺度適用中國國家標準（（：％//\4規格（21()：<2^7公趋） ! ] Ϊ Γ 裝 請先閲讀背面之注意事項再填寫本頁) 、*|1...... I HI ;i nn -11--1 - -1« -1 *— mu 111 544859 經濟部中央標準局員工消赍合作、· —製 Η1: :·ττ 昏 少形 至面 成接 形極 以汲 ，源 程伸 製延 續於 後先 入首 加’ 步構 一 結 進線 可連 並間 ’ 件 外元 之的 此上 除以 蓍 一 其 行於 Μ 同 > i 、、/ 材觸 基接 對成 再形 •， 以 上層 材電 基介 於二 層第 電之 介分 二部 第除 一 去 成並 形 _， ’程 後製 之火 成回 上 層 電 介二。 第線 及連 内内 洞義 觸定 接以 於層 層屬 屬金 金二 二第 第之 成分 形部 後除 之去 ;後 内最 明 說 單 簡 式 圖 上 之 材 基 體 導 半 於 域 區 β 隔 成 形。 中圖 明意 發示 本面 示截 顯之 圖 - 第 、 結 層極 體閘 導義 一 定 第以 、分 層部 緣其 絕除 極去 閘並 成 ，。 形層圖 中電意 明r示 發一面 本第截 示及之 顯以構 圖二 第 導 一 第 及 上 材 基 於。 層圖 /1 音心 氧示 熱面 成截 形之 中上 明壁 發側 本之 示層 顯體 圖 三 i弟 明除 發去。 本並圖 示，意 顯上示 圖 四 第 間 成 形 中 極 閘 於 壁 , . J Ί 0閱讀背面之注意事項再填寫本頁) 未 之 蓋 覆 壁 隙 間 氧 壁面 側截 之之 構層 結化 4 圖 圖 五 六 第 第 極 閘 被 未 上。 材圖 基意 於示 域面 區截 陷之 凹處 成蓋 形覆 中壁 明隙 發間 本及 示構 顯結 示 顯層 本 並 第極 除汲 去， 中 明 發 極 源 行 進 屬 示 金面 一 截 第之 成入 形植 、 子 層離 電之 介極 一 閘 意 示 面 截 之 後 應 反 屬 金 化 行 進 中 明 發 〇 本 圖示 意顯 圖 七 第 ____________6_ 本紙張尺度適中國國家慄準（CNS ) Λ4規格（210〆 297公I ) 經濟部中央標準局R工消費合作社印製 544859 j 叫 T- ‘-γ 一一 ：二 .ν·. 一 , 圖。 第八圖 顯示衣發明中去哙間隙璧、並進汙離工植入、以 形成延伸源汲極接面之截面示意圖。 第九圖 顯示本發明中定義内連線於第二介電層円之截 面示意圖。 發明詳細說明： 本發明提供一種具有凹陷之自行對準的矽化会屬接 身及延伸源汲極接®之金氧半場效電晶體（MOSFETs)的 製造方法，藉由矽化金屬接點的應用，配合具矽化金屬 接點的閘極，可使電晶體的操作速度進一步提昇；而延 伸源汲極接面的結構，可改善傳統結構中短通道效應的 問題；而以本發明中之方法所形成之元件，可進一步應 用於更高積集度的製程之中，以增加元件的密度及效 能。 在不限制本發明的精神及應用範圍下，以下即以一 半導體製程中，形成一 N通道之金氧半場效電晶體 (NMOS)的製程為例，介紹本發明之實施，而熟悉此領域 技藝者，可利相近之方法，以形成一 P通道之金氧半場 效電晶體（PMOS)，其變化之細節即不做贅述。參見第一 圖所示，首先提供一半導體基材2，半導體基材2可為一 矽材質、晶向為< 1 〇 〇>之半導體基材，並形成一氧化矽層 4於半導體基材2上，如圖中所示，氧化石夕層4係於一含 氧環境中，由半導體基材2加熱氧化成長而成；之後形 本紙张尺度適用中國國家標準（〇〇/\4現格（21〇/ 297公漦） IJ JI 讀-t閲讀背面之注意事項再填寫本頁) 訂—— d 544859 成一氮化石夕層6於氧化石夕層4上，以本實施例而言，氮 化$ f 6之形成可使用沈積方弍達成，例如使用化學氣 相沈積法等。 接著可利用微影及蝕刻製程以去除部分的氮化矽層 6及氧化矽層4，以定義所需形成隔離區域的範圍，再接 著形成隔離區域，如圖中所示的場氧化區（field oxide region; F0X)8，以提供基材2上各元件間的所需隔離作 用。 參見第二圖所示，接著利用溼蝕刻法去除二氧化矽 層4及氮化矽層6，再形成閘極絕緣層1 0於基材2上， 本例中可利用熱氧化法形成二氧化矽層於基材2上，作 為閘極的氧化層。然後形成第一導體層 12於基材2上 方、也就是閘極絕緣層1 〇與場氧化區8上方，在較佳實 施例中，可利用低壓化學氣相沈積法（Low Pressure Chemical Vapor Deposition，LPCVD)形成摻雜的多晶石夕 作為第一導體層12;接著即形成第一介電層14於第一導 體層1 2之上，本例中可使用一氧化層，並利用化學氣相 沈積方式加以形成。 經濟部中央標準局員工消费合作社印製 ! I—·裝—— "毛閱讀背面之注意事項再填寫本頁) 在1 0，1 2及1 4三個不同膜層相疊的結構形成之後， 即可藉由微影及蝕刻製程的應用，蝕去部分之第一介電 層1 4、第一導體層1 2、以及閘極絕緣層1 0，以定義出電 晶體之閘極結構1 6。依據本發明中較佳之實施例，第一 導體層1 2係為摻有雜質之多晶矽層、其厚度約為5 0 0到 5000埃（angstroms)之間，第一介電層14可為利用四乙基 本紙張尺度適用中S國家標準（CNS ) Λ4規格（公籍） 544859 石夕酸鹽（tetra-ethyl-ortho-silicate; TEOS)作為反應氣體所 形炙之氡化矽罾，其導度約鸟1 ο 〇至！ 〇 〇 〇拄之皙， 參見第三圖所示，接著即分別形成熱氧化居；.s_及2 〇 於矽基材2的裸露區域上、以及第一導體層丨2之側璧 上，藉由熱氧化層1 8的形成，可恢愎先前矽基材2因蝕 刻製程所造成的表面破壞或缺陷。依據本發明之一較佳 實施例，熱氧化層1 8及2 0可於N1 2 0或N 0的環境中， 利用熱氧化製程，分別於矽基材2、以及第一導體層12 側面，藉由與矽的氧化反應而形成，而熱氧化層1 8的厚 度約為20到1 50埃之間；熱氧化層20的厚度約為40到 2 5 0埃之間。 參閱第四圖，之後形成間隙壁2 2於閘極結構丨6的 側壁上，以較佳實施例而言，間隙壁2 2可藉由沈積並回 餘氮化矽層加以形成，其方法即是先沈積氮化矽層於熱 氧化層1 8及閘極結構1 6上，再以回蝕方式去除部分之 氮化矽層，即留下氮化矽間隙壁22 ;在回蝕製程中，未 被間隙壁22所覆蓋部分之第一熱氧化層1 8亦會同時被 去除。依據本發明之一實施例，氮化矽層之厚度約為5 0 0 至2〇〇〇埃之間，而其沈積的方法可利用低壓化學氣相沈 積法（Low Pres sure Chemical Vapor Deposition; LPCVD) 或笔漿增強式化學氣相沈積法（Plasma Enhanced Chemical Vapor Deposition; PECVD)等方式。 參閱第五圖所示，將基材2之部分表面區域去除， 以形成凹陷區域於基材2上未被閘極結構1 6及間隙壁2 2 也閱讀背面之注意事項再填寫本百( 敷------- 訂 經濟部中央標準局Η工消费合作社印裝 1 ------ ^_______________2__ 2 本紙张尺度4 $中囚_巧準（C，NS—「^格(2! () X 297.公筇7 經濟部中央標準局員工消費合作社印裝 544859 覆蓋的區域處；以最佳實施例而言，凹陷區域的形成方 法，可变用司時具嘴選擇性與等向性特色的蝕刻製隹， 直接紬刻基材]的矽材質曝露區域，並於蝕刻時提供相 對於間隙壁2 2與第一介電層1 4之材質的蝕刻選擇率， 以避免間隙壁2 2與第一介電層1 4在蝕刻凹陷區域時被 去除。此蚀刻製程之一例，可應用向下流動的蝕刻技術、 並配合氟原子團做為主要的蝕刻劑。在Y. Mitani等人所 發表的著作 “Buried Source and Drain (BSD) Structure for Ultra-shallow Junction Using Selective Deposition of Highly Doped Amorphous Silicon” （p. 176-177， 1996— 一.-«Ϊ́ T 卜 q ρ Ύ,: j Purpose and summary of the invention: The main purpose of the present invention is to provide a method for forming a transistor. Another object of the present invention is to provide a manufacturing method for forming metal-oxide-semiconductor field-effect transistors (MOSFETs) to form self-aligned silicided metal contacts with recesses and extended source drain contacts. Yet another object of the present invention is to provide a method for manufacturing metal-oxide-semiconductor field-effect transistors (MOSFETs) to improve the operating speed of the transistors and improve the problem of short channel effects in sub-micron and smaller-sized devices. The method for forming a self-aligned metal silicide contact with a recess and a metal-oxygen half field-effect transistor extending the source-drain junction in the present invention may include the following steps: first forming an isolation region on a substrate; and forming The gate insulation layer is on the substrate; a first conductor layer is formed on the gate insulation layer; a first dielectric layer is formed on the first conductor layer; and a part of the first dielectric layer and the first conductor layer are removed And gate insulation layer to define the gate structure; then a thermal oxide layer is formed on the substrate and the side wall of the first conductor layer; a gap wall is formed on the side wall of the gate structure; Thermal oxidation layer; then removing a part of the surface area of the substrate to form a recessed area on the substrate that is not covered by the gate structure and the barrier wall; and removing the first dielectric layer; and then forming a first metal layer on the substrate And then performing a source / drain / gate ion implantation; and performing a thermal process to react the first metal layer located above the recessed area and the first conductor layer to a silicided metal layer; and then removing the first metal Layer not reversed The portion; and removing the spacer; and finally a ion implantation to form the source to the drain region of the contact surface of the substrate below the oxide layer of heat. This paper size applies to Chinese national standards ((:% // \ 4 specifications (21 (): < 2 ^ 7))!! Γ Please read the precautions on the back before filling this page), * | 1 ...... I HI; i nn -11--1--1 «-1 * — mu 111 544859 Employees of the Central Standards Bureau of the Ministry of Economic Affairs have cooperated with the staff, ...— Control 1: 1: · ττ Form the connection poles to draw, the source process extension continues to the first plus the first step, 'step structure a knot into the line can be connected and connected' pieces of the foreign element divided by the number of lines in the same with i>, / The material contact base is connected and reshaped. • The base material of the above layer is between the second layer and the second part of the dielectric. The second part is divided into one to form the union. The line and the inner inner hole sense connection are removed after the layered component of the Jinjin 22nd component; the latter is most clearly stated that the material base on the single diagram is guided by the β region of the domain. The middle figure clearly shows the cut-out figure on this side-the first, the layered polar gates must be guided, and the layered parts are bounded by the extinction poles and removed. In the layered diagram, the electric meaning r indicates that the first section is shown and the display is based on the composition of the second guide and the first material. The layer diagram / 1 the sound heart oxygen surface is cut into the upper section The display layer on the wall side of the book is shown in Figure 3, which is removed by the brother. This book is shown in the figure, which means that the pole gate on the wall is shown in the figure 4 above. J Ί 0 Read the notes on the back and fill out this book. Page) The structure layering of the oxygen wall surface between the cover and the gap is not covered. The material map base is intended to cover the recessed area of the display area, cover the middle wall, open the gap between the hair, and show the structure, show the layer, and remove the first pole. The Zhongming hair pole is a gold indicator. After the surface is cut into the shape, the sublayer is separated from the electricity, and the gate electrode is shown. The surface should be anti-metallized. The picture is shown in the figure. The seventh paper ____________6_ This paper is suitable for Chinese countries. Li Jun (CNS) Λ4 specification (210〆297 male I) Printed by the R Industrial Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 544859 j Called T -'- γ One-to-two: ν ·. One, figure. Figure 8 shows a schematic cross-sectional view of the invention in removing the interstitial space and implanting it into the soil to form an extended source drain junction. The ninth figure is a schematic cross-sectional view of an interconnect defined on the second dielectric layer in the present invention. Detailed description of the invention: The present invention provides a method for manufacturing self-aligned silicides with recesses and metal-oxide-semiconductor field-effect transistors (MOSFETs) with extended source-drain connections®, by the application of silicided metal contacts, With the gate with silicided metal contacts, the operating speed of the transistor can be further improved; the structure of extending the source-drain junction can improve the problem of short channel effect in the traditional structure; and formed by the method of the present invention The components can be further applied to processes with higher accumulation to increase the density and performance of the components. Without limiting the spirit and scope of the present invention, the following is a process of forming an N-channel metal-oxide-semiconductor field-effect transistor (NMOS) in a semiconductor process as an example to introduce the implementation of the present invention and be familiar with the art in this field. Alternatively, a similar method can be used to form a P-channel metal-oxide-half field-effect transistor (PMOS). Details of the changes are not described in detail. Referring to the first figure, a semiconductor substrate 2 is first provided. The semiconductor substrate 2 may be a silicon substrate with a crystal orientation of <100; and a silicon oxide layer 4 is formed on the semiconductor substrate. On the material 2, as shown in the figure, the oxidized stone layer 4 is formed in an oxygen-containing environment, and is grown by heating and oxidizing the semiconductor substrate 2. The size of the paper after this applies to Chinese national standards (〇〇 / \ 4present Grid (21〇 / 297 cm) IJ JI read -t read the notes on the back and fill in this page) order-d 544859 into a nitride layer 6 on the oxide layer 4, in this embodiment, The formation of the nitride $ f6 can be achieved by using a deposition method such as chemical vapor deposition. Then, a lithography and etching process can be used to remove a part of the silicon nitride layer 6 and the silicon oxide layer 4 to define the range of the isolation region to be formed, and then an isolation region is formed, as shown in the field oxide field (field). oxide region; F0X) 8 to provide the required isolation between the various components on the substrate 2. As shown in the second figure, the silicon dioxide layer 4 and the silicon nitride layer 6 are removed by a wet etching method, and then a gate insulating layer 10 is formed on the substrate 2. In this example, a thermal oxidation method can be used to form the dioxide. The silicon layer is on the substrate 2 and serves as an oxide layer of the gate. A first conductor layer 12 is then formed over the substrate 2, that is, above the gate insulating layer 10 and the field oxidation region 8. In a preferred embodiment, a Low Pressure Chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition, LPCVD) to form a doped polycrystalline stone as the first conductive layer 12; then, a first dielectric layer 14 is formed on the first conductive layer 12; in this example, an oxide layer can be used and a chemical vapor phase can be used. Formed by deposition. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs! I— · Installation— " Mao read the notes on the back of the page and fill in this page again) After the formation of three different film layers of 10, 12, 2 and 14 That is, by the application of the lithography and etching process, part of the first dielectric layer 14, the first conductor layer 1 2, and the gate insulating layer 10 are etched to define the gate structure 1 of the transistor 1 6. According to a preferred embodiment of the present invention, the first conductive layer 12 is a polycrystalline silicon layer doped with impurities and has a thickness of about 500 to 5000 angstroms. The first dielectric layer 14 may be made of four layers. The size of the ethyl paper is in accordance with the Chinese National Standard (CNS) Λ4 specification (public registration) 544859 Tetra-ethyl-ortho-silicate (TEOS) as a reaction gas, its conductivity is about Bird 1 ο 〇 to! 〇〇〇 拄 拄 see, as shown in the third figure, and then form thermal oxidation respectively; .s_ and 20 on the exposed area of the silicon substrate 2 and on the side of the first conductor layer 2, The formation of the thermal oxidation layer 18 can recover the surface damage or defects caused by the previous etching process of the silicon substrate 2. According to a preferred embodiment of the present invention, the thermally oxidized layers 18 and 20 can be thermally oxidized on the sides of the silicon substrate 2 and the first conductive layer 12 in a N1 2 0 or N 0 environment. It is formed by an oxidation reaction with silicon, and the thickness of the thermal oxidation layer 18 is between about 20 and 150 angstroms; the thickness of the thermal oxidation layer 20 is between about 40 and 250 angstroms. Referring to the fourth figure, a spacer 22 is formed on the side wall of the gate structure. In a preferred embodiment, the spacer 22 can be formed by depositing and backing up a silicon nitride layer. The method is as follows: First, a silicon nitride layer is deposited on the thermal oxidation layer 18 and the gate structure 16, and then a part of the silicon nitride layer is removed by etchback, leaving a silicon nitride spacer 22. In the etchback process, The first thermal oxide layer 18 that is not covered by the partition wall 22 is also removed at the same time. According to an embodiment of the present invention, the thickness of the silicon nitride layer is between about 500 and 2000 angstroms, and the method for depositing the silicon nitride layer can be low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition; LPCVD). ) Or Plasma Enhanced Chemical Vapor Deposition (PECVD). Referring to the fifth figure, a part of the surface area of the substrate 2 is removed to form a recessed area on the substrate 2. The gate structure 16 and the spacer 2 2 are also read. ------- Ordered by the Central Standards Bureau, Ministry of Economic Affairs, Machining and Consumer Cooperatives. 1 ------ ^ _______________ 2__ 2 This paper size is 4 $ () X 297. Public address 7 The area covered by 544859 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs; in the preferred embodiment, the method of forming the recessed area can be changed with the mouth selectivity and isotropy. Characteristic etching system, directly engraving the silicon material exposed area], and provide an etching selectivity relative to the materials of the spacer 22 and the first dielectric layer 14 during the etching to avoid the spacer 2 2 and the first dielectric layer 1 4 are removed when etching the recessed area. An example of this etching process is to apply a down-flow etching technique with fluorine atom groups as the main etchant. In Y. Mitani et al. Publication "Buried Source and Drain (BSD) Structure for Ultra-shallow Junction U sing Selective Deposition of Highly Doped Amorphous Silicon "(p. 176-177, 1996
Symposium on VLSI Technology Digest of Technical Papers, IEEE)之中，即提到有關此一等向性餘刻技術的 細節，，可提供蝕刻矽表面時較少的蝕刻損害，並具有相 對於氧化矽材質的選擇性。 參閱第六圖所示，然後即除去位於閘極結構1 6上方 的第一氧化層14，本例中可使用為溼蝕刻製程，配合缓 衝氧化物姓刻劑（b u f f e r ο X i d e e t c h a n t; Β Ο E)溶液或是稀 釋的氫氟酸（diluted HF)，即可加以去除。並沈積第一金 屬層26於矽基材2上，然後使用離子佈植的製程，、進行 源極/沒極/閘極區域中摻雜物的植入。以一般的製程應用 而言’第一金屬層26可為如鈦、鎢、鈷、鉑、鎳及鉻等 的材料’以於後續製程之中與矽反應形成矽化金屬層’ 本例中其厚度約為5 0至1 〇 〇 〇埃之間，其沈積方法可應 用為化學氣相沈積法（CVD)或是濺鍍等的物理氣相沈積 法（PVD)〇 •—.—-—~ ；------------- 10 本紙張尺度適.丨家標準（)八4規格（2{()x297公势 〈清屯閱讀背面之注意事項再填寫本頁)Symposium on VLSI Technology Digest of Technical Papers (IEEE) refers to the details of this isotropic epitaxial technology, which can provide less etching damage when etching the silicon surface, and has a relative Selective. Referring to the sixth figure, the first oxide layer 14 located above the gate structure 16 is then removed. In this example, a wet etching process may be used, and a buffer oxide name etching agent (buffer ο X ideetchant; Β 〇 E) The solution or diluted hydrofluoric acid (diluted HF) can be removed. A first metal layer 26 is deposited on the silicon substrate 2 and implanted with dopants in the source / non-electrode / gate regions using an ion implantation process. In terms of general process applications, 'the first metal layer 26 may be a material such as titanium, tungsten, cobalt, platinum, nickel, chromium, etc.' to react with silicon to form a silicided metal layer in subsequent processes. 'Its thickness in this example Between about 50 and 1000 angstroms, the deposition method can be applied as chemical vapor deposition (CVD) or physical vapor deposition (PVD) such as sputtering. ------------- 10 This paper is suitable in size. 丨 Home Standard () 8 4 specifications (2 {() x297 public momentum <Please read the notes on the back of Qingtun before filling out this page)
544859544859
經濟部中央標準局員工消費合作社印製 而源極/汲極/閘極區域的離子植入，以形成N型金氧 半場效電晶體為例，可使用含砷的離子或是含德的離 子；在較佳實施中，所使用的植入能量約為 1 0到 120 KeV，以產生約為5E14至5E16atoms/cm2之間的離子濃 度，以於後續熱製程中擴散形成源極與汲極區域，並進 一步增加閘極結構1 6中多晶矽材料的摻雜濃度。 接著參見第七圖，進行以加熱製程將金屬藉由高溫 的反應而矽化的製程，以將部分的第一金屬層2 6經由與 矽的反應形成石夕化金屬層 2 8，其中位於場氧化區域 8 上、以及在氮化矽間隙壁 2 2上方與侧邊之第一金屬層 26，由於未與矽表面接觸，因此並不參與反應。 之後並去除未反應的殘餘第一金屬層26，以留下石夕 化金屬2 8。依據本發明之一較佳實施例，石夕化金屬形成 之熱製程所使用的溫度約為3 5 0到7 0 0 °C之間，而殘餘第 一金屬層2 6之去除方法係為習知用以去除金屬的濕蝕刻 法，並使第一金屬層26於前述製程中植入的離子向下擴 散而形成源極與汲極區域2 7。 參見第八圖所示，將間隙壁2 2加以去除，本例中可 利用熱磷酸溶液來除去氮化矽間隙壁2 2，接著並可利用 離子佈植法或是電漿擴散浸入法（plasma immersion)，進 行扯伸源i極區3 0之摻雜植入；以形成N型金氧半場效 電晶體為例，可使用含砷的離子或是含磷的離子；在較 佳實施中，離子佈植所使用的植入能量約為 0.5 Ke v至 30KeV之間，以產生約為5E13至2E15 atoms/cm2之間的 本紙張尺度適用中國國家標準（CNS )八4規_格ί 210〆 297公t ) _ τ 裝 請毛閱讀背面之注意事項再填寫本頁) 訂—— ----SI 1 1--1-1 - - 1— · 544859 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（ :子”思而形成如圈中所示的，具有凹陷之自行對準 曰Z化 接點、以及延伸源汲極接面的金氧半場效電 晶體。 除了上述的製程之外，可進一步加入一系列的後續 製程，以形成—展、Λ β 層或通常疋多層的元件間連線結構， 參見第九圖所示，首·參开彡士、 首先$成第二介電層32於基材2之 ^本例中可利用化學氣相沈積法沈積氧化矽層做為第 一介電層32。並接著進行回火製程，以 32 的材料變得較為宓誓，摆I* α 馬密實 &昇其隔絕特性，並使矽化金屬 層28經由回火# 淮 & 的處理進入較為穩定的狀態；接著去除部 分之第"一介電層1 7，IV ^ ¥ ts η , 增32以疋義接觸洞於其内，一般可使用 微影製程及餘刻^丨、,、去丄、 一域幻製程加以達成之。然後再形成第二金屬 層34於第_介電層32、並填人於接觸洞内。最後可配合 微影製程及餘刻激兹的你田 、— ％製程的使用，除去部分之第二金屬層 34以疋義内連線。依據本發明之較佳實施例，回火製Ion implantation in the source / drain / gate region printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ; In a preferred implementation, the implantation energy used is about 10 to 120 KeV to generate an ion concentration between about 5E14 to 5E16 atoms / cm2 for diffusion and formation of source and drain regions in subsequent thermal processes And further increase the doping concentration of the polycrystalline silicon material in the gate structure 16. Next, referring to the seventh figure, a process of siliciding the metal by a high-temperature reaction in a heating process is performed to form a part of the first metal layer 26 through a reaction with silicon to form a petrified metal layer 28, which is located in the field oxidation The first metal layer 26 on the region 8 and above and on the side of the silicon nitride spacer 22 is not in contact with the silicon surface and therefore does not participate in the reaction. After that, the unreacted residual first metal layer 26 is removed to leave the petrified metal 28. According to a preferred embodiment of the present invention, the temperature used in the thermal process of forming the metallized petrochemicals is between about 350 ° and 700 ° C, and the method of removing the remaining first metal layer 26 is conventional. The wet etching method for removing metal is known, and the ions implanted in the first metal layer 26 in the aforementioned process are diffused downward to form source and drain regions 27. Referring to the eighth figure, the spacer 22 is removed. In this example, a thermal phosphoric acid solution can be used to remove the silicon nitride spacer 22, and then an ion implantation method or a plasma diffusion immersion method can be used. immersion) to perform doping implantation of the source i-electrode region 30; taking the formation of an N-type metal-oxide half field effect transistor as an example, arsenic-containing ions or phosphorus-containing ions may be used; in a preferred implementation, The implantation energy used for ion implantation is about 0.5 Ke v to 30 KeV to generate about 5E13 to 2E15 atoms / cm2. This paper scale is applicable to China National Standard (CNS) Regulation 8_ 格 ί 210〆 297g t) _ τ Please read the notes on the back and then fill out this page) Order ——SI 1 1--1-1--1— · 544859 A7 B7 Employee Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs Printed 5. Description of the invention (: zi) formed as shown in the circle, with a recessed self-aligned Z-shaped contact, and extended source-drain junction metal-oxide half field effect transistor. In addition to the above In addition to the manufacturing process, a series of subsequent processes can be further added to form-spread, Λ β layer, or usually Multi-layer connection structure between elements, as shown in Fig. 9. First, the first step is to form a second dielectric layer 32 on the substrate 2. In this example, silicon oxide can be deposited by chemical vapor deposition. Layer as the first dielectric layer 32. Then the tempering process is performed, with the material of 32 becoming more oath, I * α horse compact & improve its insulation characteristics, and make the silicided metal layer 28 via tempering # The processing of Huai & enters a more stable state; then remove the part of a " dielectric layer 17, IV ^ ¥ ts η, increase 32 in the meaning of the contact hole in it, generally can use the lithography process and the rest Carved ^ 丨 ,,, 丄, and a domain magic process to achieve it. Then a second metal layer 34 is formed on the _ dielectric layer 32 and filled in the contact hole. Finally, it can be used with the lithography process and the rest You are excited about the use of this process, except for a part of the second metal layer 34, which is interconnected in a sense. According to a preferred embodiment of the present invention, the tempering system is used.
程的處理溫度約為700到95〇t之間，而第二金屬層W 可為如鋁、銅、鈦、鎢、鈷、鉑、鎳及鉻等的材料。 因此，藉由本發明中之方法，可形成具有凹陷之自 盯對準的矽化金屬接點、以及延伸源汲極接面的金氧半 場效電晶體，並提供良好的操作速度，同時抑制傳統製 程與元件所產生的短通道效應，而進一步提昇積體電路 的運作特性及元件積集度。 本發明僅以較佳實施例說明如上，並非用以限定本 發明之申請範圍，·凡熟習該項技藝人士，在未脫離本發 12 本紙張尺度適用中國國家標準（CNS ) A4祝格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 破 544859 A7 B7 五、發明説明（ 飾。 修内 或圍 變範 改利 許專 些請 作申 可之 當述 ，下 下在 神含 精包 之應 明均 圍 範 護 保 利 專 其 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐）The processing temperature of the process is about 700 to 950 t, and the second metal layer W may be a material such as aluminum, copper, titanium, tungsten, cobalt, platinum, nickel, and chromium. Therefore, by the method of the present invention, a self-aligned silicided metal contact with a recess and a metal-oxide half-field-effect transistor extending the source-drain interface can be formed, and provide a good operating speed while suppressing the traditional process And the short-channel effect produced by the components, and further improve the operating characteristics of the integrated circuit and component integration. The present invention is only described in the preferred embodiment as above, and is not intended to limit the scope of application of the present invention. Those skilled in the art can apply the Chinese National Standard (CNS) A4 Zhuge (210) without departing from this paper. X 297 mm) (Please read the precautions on the back before filling out this page) Order 544859 A7 B7 V. Description of the invention (decoration. Renovation or modification within the scope of change or license. Please refer to the application form below. The following should be included in the package containing God's package. Please read the precautions on the back before filling out this page. Printed on paper standards of the China National Standards (CNS) A4. Zhuge (210X297 mm)