TW439133B - Multi-gate method for forming silicide - Google Patents

Abstract

The present invention discloses a method for forming a titanium silicide gate to decrease the resistance of the deep sub-micron device. The method comprises: forming an oxide layer on the surface of the substrate; using the low pressure chemical vapor phase deposition method to form a polysilicon layer on the oxide layer; forming a titanium nitride layer on the polysilicon layer; forming a TiSi2 layer on the titanium nitride layer; forming an amorphous silicon layer on the titanium nitride layer to obtain a titanium silicide layer; next, sputtering a titanium layer on the amorphous silicon layer; forming a titanium nitride layer on the titanium layer; performing two thermal annealing processes to form a titanium silicide layer on the titanium nitride; then, using a peeling off step to remove the titanium layer and titanium nitride layer without being reacted; and finally, using a standard photolithography and etching technique to form a gate structure.

Description

^ 3 313 3 A7 B7 V. Description of the invention () 明 1 _Mingling 敁: The present invention is related to a semiconductor process, especially a metal oxide half field effect transistor (M 0 SFET) formed with self-alignment_quasi-cut Method of compound gate. Invention No .: In the integrated circuit, the MOSFET is an omnipresent element. A typical MOSFET includes one pole, one source, and -no pole. Recently, as the mounting density of wafer elements continues to increase, the dimensions of MOSFET elements have been continuously reduced. However, high-speed operation is one of many important requirements for MOSFETs, but the speed of MOSFETs is often affected by RC delay and contact resistance. Therefore, for deep submicron M0S devices, self-aligned metal silicides (se 1 f-a 1 i and 11 pds 1 1 1 c 1 de) (ie, self-aligned silicides) are used to improve the operation of the device. speed. I--II --- ·-ί-I .1-1-- I in _-J. V -9 (Please read the notes on the back before filling out this page) In the previously disclosed technology, 'for deep sub-micron high-speed MOSFETs, it has the excellent performance of metal silicide WSi22CM0S transistor, which is often attributed to its low-chip capacitor and its material °. Titanium silicide is used to make the gate, source, and drain. The method of reducing the gate resistance and the source and drain resistance is one of the effective methods. In the traditional process of forming self-aligned silicide, the typical practice is that the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm > —. 4 3 w '4 A7 ___B7 V. Description of the invention () Take for example ο layer metal structure on the pole gate and metal base metal on the I-shaped square plated surface of the base metal base and so on N 1 is, to the pole on the gate and side metal gold The brake moves the fire back to the rapid heat step and removes the quick peeling line. □ C belongs to β gold, and the fusion resistance is 35, otherwise it will be reversed after the reaction. Bottom layer, Weili There are too many crystals in the M). The RA pole (the memory element in the D gate body takes the rice storage microcomputer time and the deep state as the action system. The system is used for this purpose. When it is made, it will go down when it is made. Using the 25-meter formula of the formula meter to make small pieces of material with small ginseng material size, when silicon is quasi-positive, η belongs to W gold WS, with deep depth 0 middle weight 0 yuan weight% J Strictly shrinking for Yu Gen's use of the past and the right one, let's not ask this one. Because of this resistance, a high-quality rice is produced. The micro gate is more inferior than this (please read the precautions on the back before filling this page). It is recommended to use the gate as a low-voltage switch, which is considered to be electric,]. The material of the material of the quality technique SW material technology has the same sand in Youhua. If it belongs to the metal material of the medium quality material S S 2 T 4 5 C position and the phase 9 4 Μ C 5 c C. Including si electric T1, it has a high level of shrinkage, and it is changed to 49, so C is a tool. And C5 is a tool. It is printed by the Pager Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs and the Ministry of Economic Affairs in order to facilitate the development of a new method, which is necessary. Xiangdian 4 & 5 ί degenerate debris. Belonging to _ material gold silicon material. 12 exhibition 2 S 1 I s T 3 T bit S1 T1 line --.-- ^-f. This paper scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) A7 _____B7 V. Description of the invention () The present invention discloses a method for forming a gate with titanium silicide. Deep sub-micron reduce the resistance element. This method comprises forming an oxide layer, a polysilicon layer on the surface of the substrate, using a low pressure chemical vapor deposition on the oxide layer formed. A titanium nitride layer is formed on the polycrystalline silicon layer, and then a TiSi2 layer is formed on the titanium nitride layer. A titanium silicide layer can be obtained by forming an amorphous silicon layer on the titanium nitride layer. Next, a metal layer was plated on the amorphous silicon layer 'to form a hafnium nitride layer on the titanium metal layer. The thermal tempering step is performed twice to form a titanium silicide layer 'on the titanium nitride layer, and then a stripping step is used to remove the titanium metal layer and the titanium nitride layer which are not involved in the reaction. Next, by standard lithography and etching techniques, a gate structure can be formed, which is illustrated in a simple and easy way. The figure can be shown in the following: The detailed items are detailed below, and the semi-crystalline crystals are guided on the base of the material by the figure described in the description. On one side of the multi-graph, the sliced oxygen crystals are integrated into a conductive half. The Central Bureau of Standards of the Ministry of Silicon Economics and Consumers cooperated with the work. The company printed a step-by-step Mingfa based on the graphic display of the sliced crystal 3a. The first half of the moon is shown in Figure 2. The first silicon is formed into Figure 3. The second piece of the second piece and the semi-metallic gold-guiding layer are clearly issued. Shows step by step, 4

I This paper size applies to China's National Standards (CNS) A4 specifications (2 丨 OX 297 mm) Printed by A7 __ B7_ from the Beijin Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention () Perform a thermal process to form a Steps of metal silicide layer. The fourth figure is a cross-sectional view of a semiconductor wafer, showing a step of forming a metal silicide according to another implementation method of the present invention. The fifth figure is a cross-sectional view of a semiconductor wafer, showing a step of forming a transistor according to the present invention. Detailed description of the invention: The present invention provides a new method for constructing a polycrystalline silicon silicide (P ο 1 y c i d e) contact. The so-called polycrystalline silicon silicide refers to the formation of a metal silicide layer on a polycrystalline silicon gate. By using this technology ', not only the component operation speed can be increased, but also T 1 S 1 2 with C 5 4 梠 can be obtained to effectively reduce the chip resistance. This new method is not the same as the traditional metal silicide process. The T i S i 2 layer is formed on the polysilicon gate, rather than on the source and drain. Referring to the first figure, a specific embodiment of the present invention is described. According to this embodiment, a single crystal substrate 2 having a < 10 0 > crystal orientation is provided, and a thick field oxide (FOX) region 4 is formed on the substrate to provide an isolation effect between components. Through traditional lithography and etching techniques, a nitride-silicon oxide composite layer is etched to form the F ◦x region 4. After removing the photoresist and fishing-type cleaning, a thermal oxidation method is used in a steam environment to generate the F0X region 4. In addition, a plurality of shallow trench isolations (s h a 1 1 0 w t r e n c h i s. 1 a t i ο n S) may be used instead of F 0 X region 4. t This paper size applies to Chinese national standards (CNS} A4 size {2 丨 0X 297 mm) ^ 、 ^ Order ------- ^ line (please read the precautions on the back before filling this page) 5. Description of the invention () A7 B7 The next step is to make a semiconductor transistor on the substrate 2, for example, to form a dream oxide layer 6 on the surface of the substrate 2 as the next MOS transistor to be formed. Gate oxide layer. The silicon oxide layer 6 is preferably formed in an oxygen-filled environment of about 8000 to 1 100 0. The thickness of the silicon oxide layer is about 15-2 50 Angstroms = may Alternatively, a chemical vapor deposition method may be used to form the oxide layer 6. Then, a low-pressure chemical vapor deposition method is used to form a polycrystalline silicon layer 8 on the FOX region 4 and the silicon oxide layer 6. In a preferred embodiment, the polycrystalline silicon layer 8 is deposited on the gate oxide layer by a conventional technique, and its thickness is about 800 to 120 angstroms. In a preferred embodiment, the polycrystalline silicon layer 8 is a doped polycrystalline silicon process or a synchronous doping process. Polycrystalline silicon process is used to form. Next, a thickness of about 50 to 15 is formed on the polycrystalline silicon layer 8. 0 angstrom titanium nitride (T i N) layer 10, the T 1 N layer 10 is used as a barrier layer to prevent the polycrystalline silicon layer from reacting with the subsequent T i S i 2 layer. Rhodium is not nitrided Ti (Ti) layer 10, the Ti_Si internal diffusion effect will occur between the polycrystalline silicon layer and TiSi2 layer, leading to a reduction in the effectiveness of the gate oxide layer. Staff Consumer Cooperative, Central Bureau of Prototype, Ministry of Economic Affairs The printed ruler paper I is shown in the second figure as gold T, and the silicon resisting titanium electrification is lowered by the element layer and the lower layer is made of silicon. The layer of Ni is made of silicon. In .1! 2) 着 P is connected to X Ϊ can belong to this object, M ^ iY silicon

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Printed by Shellfish Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs 4 3 91 3 3ι $ A 7 __B7_ V. Description of the Invention () By using the following method, we can form a silicide layer on the Ti layer 10. For example, a cut layer, preferably an amorphous dream layer 12 is formed on the hafnium nitride layer 10, and then a titanium metal layer I 4 is plated on the amorphous chip layer 12 and then formed. Another nitride layer 16 is on top of the metal layer 14. This second hafnium nitride layer functions as a cap to prevent contamination and prevent oxygen from interacting with the deposited metal layer 14 to affect it. The reaction between T! And S i is shown. The thickness of the titanium nitride layer is about 1 Q 0 to 3 0 0 Angstroms. Next, referring to FIG. 3, a first rapid thermal tempering (RTA) step is performed in an N 2 environment at 700 to 800 ° C to promote the reaction between the titanium metal layer 14 and the amorphous silicon layer 1 2. This generates a titanium silicide layer 1S on the titanium nitride layer 10. Then, a second rapid thermal tempering (RTA) step is used to completely convert the titanium silicide layer 18 to the C5 4 phase. In a preferred embodiment, the thermal tempering process is performed at a temperature of about 850 to 100 ° C in a nitrogen gas environment for about 30 to 90 seconds. In addition, the titanium silicide layer 18 can also be formed in a furnace, and then, using wet etching, such as in a SPM (H2S〇4 + H2〇2) solution, a stripping step is performed to remove the remaining non-participating effects. The titanium metal layer I4 and the titanium nitride layer 16.

Alternatively, referring to the fourth figure, a titanium silicide layer 18 can also be formed on the titanium nitride layer 10 by using a chemical vapor deposition method, and T 312 can be formed from T i C 1 and S i Η in a reactor. 4 is obtained by a reaction, and the chemical formula of this reaction is shown below. The temperature for forming titanium silicide is about 5 50 to 6 8 0 ° C. The paper size is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) *., ≫ Packing -------- Order ---- --- line (Please read the notes on the back before filling this page} Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs Α7 Β7 V. Description of Invention ()

TiCl + 2SiH4--T 1 S i, + 4HC 1 + 2H „Finally, a silicon nitride layer or a silicon oxide layer 20 is formed on the titanium silicide layer 18 for isolation. Then refer to the fifth Figure, using a standard lithography and etching technique to etch on the isolation layer 2 Q, titanium silicide layer 18, titanium nitride layer 10 'polycrystalline silicon layer 8 and gate oxide 4' to form a gate structure ° and then available The traditional mask and ion implantation technology are used to build the source / depositor of M 0 s. For those skilled in the art, it will be easy to understand that by simply implanting a positive dopant instead of the MOS originally used as N channel, A P-channel MOSFET can be formed. More importantly, CMOS MOSFETs can also be obtained in a similar way. A slightly doped drain electrode 22 is formed. ^ 11111? DoPed drain) ο For example, with the completion of the slightly doped drain electrode 2 2 ', a dielectric layer may be formed on the gate structure and the substrate 2 where the dielectric is formed. An anisotropic candlestick is performed on the layer to form a side wall 24 on the side wall of the gate structure. Then, by Using the gate structure and the side wall 24 as a curtain and performing N + source / drain ion implantation of arsenic ions, a source electrode and a set electrode 2 6 0 can be formed in the substrate 2. Multi-layer gate structure, will be obtained-can be used in deep micro-paper scales to apply Chinese National Standards (CNS) A4 regulations (210X297 mm) C .------- Order ------ qi (please Please read the precautions on the back before filling this page) __B7_ V. Description of the invention () Polysilicon drum poly-gate used in meter components, such as 0.18 micron DRAM S 0 After the application of one of the various applications, although it was widely stated that it was the most explicit to issue a contract to the should, they are all out of the box and settled. Please refer to this article for explanations. Please refer to the issue of the Divine Skills and Skills of the Realm of Knowledge. This is to limit the maturity in order to use it. It is true and practical. The entity Jiashi is more clearly included in the inner circle of the work that should be modified. The Liming with the inner circle of the fine circle issued a special request for this statement to leave. No less in (Please read the notes on the back before filling out this page) -t

-IT i Printed by the Central Ministry of Economic Affairs, Zhuhai Cooperative Consumer Cooperative, This paper size applies to China National Standard (CNS) Α4 (210X 297 mm)

Claims (1)

ABCD, Employees' Cooperative of the Central Standard Vehicle Bureau of the Ministry of Economic Affairs, India 6. Application for Patent Scope 1. A method for forming a gate of a MOSFET on a substrate, the method includes the steps of: forming a gate oxide layer on the substrate: forming A polycrystalline silicon layer on the gate oxide layer; forming a 'said yttrium nitride layer on the polycrystalline layer as a barrier layer; forming an amorphous stone layer on the first nitride “On the layer; forming a titanium metal layer on the #crystalline silicon layer; forming a second hafnium nitride layer on the gold layer as a masking layer; performing a first heat treatment to make the amorphous silicon layer and The titanium metal reacts, thereby forming a titanium silicide layer on the first titanium nitride layer, and the second titanium nitride layer is used as the covering layer to prevent contamination and prevent oxygen from reacting with the titanium metal layer. Causing the reaction between the amorphous silicon layer and the titanium metal to be affected; removing the second titanium nitride layer and the metal layer that have not reacted with the amorphous silicon layer; forming an isolation layer on the titanium silicide layer ; And etched on the isolation layer, on the titanium silicide layer, the multiple The silicon layer and the gate oxide layer to form the gate. 2. The method of item 1 of the scope of application further includes performing a second heat treatment to switch the titanium silicide layer to the C 5 4 phase. (Please read the precautions on the back before filling out this page) €-The size of the bound paper is applicable to China National Standard (CNS) A4 (210X297 mm) ABCD Printed by the Consumers' Cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs Patent scope 3. The method as described in item 1 of the claim, wherein the first titanium nitride layer has a thickness of about 50 to 15 Q angstroms and the first titanium nitride layer is used as a barrier layer to prevent The polycrystalline silicon layer reacts with the titanium silicide layer. 4. The method according to item I of the application scope, wherein the temperature of the first heat treatment is about 7 Q Q to 80 Q. 5. The method according to item 1 of the scope of application, wherein the first heat treatment is performed in an environment filled with N 2 gas. 6. The method according to item 2 of the application range, wherein the temperature of the second heat treatment is about 8 5 Q to 1 Q Q 0. 7. The method according to item 2 of the application scope, wherein the second heat treatment is performed in an environment filled with nitrogen gas. 8. The method according to item 1 of the application scope, wherein the above isolation layer can be selected from silicon nitride or oxidation. Silicon. 9. The method as described in item 1 of the scope of application, wherein the second titanium nitride layer has a thickness of about 1,000 to 300 angstroms. 10. —A method of forming the MOSFET on the substrate, please read the precautions on the reverse side and fill in this page first. -Packing. The paper size of the paper is applicable to China National Standard (CNS) 8-4 U10X297 (Mm) Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. The scope of the patent application method includes the steps of: forming a gate tritium layer on the substrate; forming a polycrystalline sand layer on the gate oxide layer; forming A first vaporized plutonium layer is formed on the polycrystalline cutting layer as a barrier layer; a stone atomic layer is formed on the first plutonium metal layer; a conductive layer is formed on the silicon atomic layer; a first The dinitride layer serves as a cover layer 1 on the conductive slide, and a first heat treatment is performed to make the silicon atomic layer react with the conductive layer, thereby forming a metal silicide layer on the first titanium nitride layer. The second titanium nitride layer is used to prevent contamination and prevent oxygen from reacting with the conductive layer, which affects the reaction between the silicon atomic layer and the conductive layer; and removes the second nitrogen that has not reacted with the silicon atomic layer. A titanium compound layer and the conductive layer; Spacer layer on the metal silicide layer; and engraved only on the spacer layer, the sand on the metal friction compound, to form the polycrystalline silicon layer on the gate electrode and the gate oxide layer. 11. The method of claim 10, wherein the conductive layer can be selected from titanium, tungsten or nickel. I2 · As for the method of the 11th application scope, in which the above conductive layer includes Yan13 (Please read the precautions on the back before filling this page) The paper size is applicable to China National Standards (CNS) M specifications (210X297 mm) 8 8 8 8 ABCD 43 913 3 VI. Patent Application Range 1 3. The method of item 12 of the application range further includes performing a second heat treatment to switch the titanium silicide layer to the C 5 4 phase. I4. The method of claim 10, wherein the first titanium nitride layer has a thickness of about 50 to 150 angstroms and the first titanium nitride layer is used as a barrier layer to prevent the polycrystalline silicon layer. Reacts with this metal silicide layer. I5. The method according to item 10 of the application, wherein the first heat treatment has a temperature of about 700 to 800 ° C. I6. The method according to item 10 of the application, wherein the first heat treatment is performed in a gas-filled environment. I7. The method according to item I3 of the application scope, wherein the temperature of the second heat treatment is about 8 5 Q to 1 0 0 1 0. 1S. The method according to item I3 of the scope of application, wherein the above-mentioned second heat treatment is performed in an atmosphere filled with nitrogen gas. I9. The method according to item I3 of the application scope, wherein the second heat treatment is performed for about 30 to 90 seconds. 20. The method according to item 10 of the application scope, wherein the above-mentioned second nitrogen paper size is based on the Chinese national standard (CNS > A4 specification (210X297 mm) ------- k --- " ------ ^ ------ line (please read the notes on the back before filling out this page) India Central Bureau of Standards, Ministry of Economic Affairs, Consumer Cooperatives, India 8 8 8 8 ABCD 43 913 3 VI. Application Patent scope 1 3. The method according to item 12 of the application scope, further comprising performing a second heat treatment to switch the titanium silicide layer to the C 5 4 phase. I4. The method according to item 10 of the application scope, wherein the first nitrogen The titanium compound layer has a thickness of about 5 Q to 15 Q Angstroms and the first titanium nitride layer is used as a barrier layer to prevent the polycrystalline silicon layer from reacting with the metal silicide layer. I5. As for item 10 of the scope of application The method, wherein the temperature of the first heat treatment is about 700 to 8 ΰ Q. 1 (3. The method according to item 10 of the application scope, wherein the first heat treatment is performed in an environment filled with N2 gas. I7. The method according to item I3 of the application scope, wherein the temperature of the second heat treatment is about 8 50 to 100 0. 1S. Such as Please apply the method of the scope item I3, wherein the above-mentioned second heat treatment is performed in an atmosphere filled with nitrogen gas. 19. If the method of the scope of the application item I3, wherein the above-mentioned second heat treatment is performed for about 30 to 90 seconds 20. The method of item 10 of the application scope, in which the above-mentioned second nitrogen paper size is free from the Chinese national standard (CNS > A4 specification (210X29? Mm)) ------- k'-li- ----- IT ------- (Please read the notes on the back before filling in the book f) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 43 〇 Α8 Β8 C8 D8 The thickness of the titanium layer is about 1 Q 〇 to 3 Q 0 Angstroms. (Please read the notes on the back before filling this page). Binding line. Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Standard (CNS) A4 specification (210X29? Mm)