經濟部中央標準局員工消費合作社印製 A7 __________B7 五、發明説明（）Mijg领诚： 本發明係有關於半導體元件，特別是關於互補式金氧 半導體（CMOS)元件。 爱1_明背景： 關於極大型積體電路（ULSI)之應用，元件尺寸已縮小 至次微米或深次微米範圍，自行對準金屬矽化物（SALICIDE) 製程為一普遍用於減少閘極、源極與汲極電阻之方法，如 此’具有自行對準金屬矽化物製程之互補式金氧半導體 (C Μ 0 S )元件可增加操作速度。 最近，A. Hori等人提出具有極淺源極與汲極接面之 元件’利用5 KeV離子佈植法及快速熱回火法，此法可用 於抑制短通道效應’在此文章中，源極與汲極延長利用離 子佈植法製造以獲得極淺的輪廓，請參考A. Hori等人所 提之文章’於 IEDM Tech. Dig. p.485, 1994,定名為 “A 0.05 μιη-CMO S with Ultra Shallow Source/Drain Junction Fabricated by 5 KeV Ion Implantation and Rapid Thermal Annealing” ° 關於ULSI電路之應用，閘氧化層之厚度需要縮小尺 寸至十億分之一公尺’因此’極薄氧化層之可靠性成為縮 短元件之一嚴重問題’傳統上，閘氧化層之可靠性由許多 -2- 本紙張尺度適用中國國家標準（CNS)A4規格（2丨0X297公釐） (請先閲讀背面之注意事項再填寫本頁) --I I I I II I —A--Γ— - L--- 訂 .1:----J ——；-------------- 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 因素影響’例如即使供應0 _ 2 5微米Μ 0 S之電壓降至2 · 5 伏特，熱載子為降低元件性能之一主要關鍵。為了提供可 靠的金氧半場效電晶體（MOSFETs)，許多MOSFET結構已 被提供’例如，一接近改善熱載子電阻之習知技術使用一 NICE(nitr〇gen implantation into CMOS gate electrode and source and drain)結構，NICE 結構由 T. Kuroi，et al.，in IEDM Tech. Dig.，p3 25,1 993所提出，此結構中，具有p+多 晶矽閘極PMOS表面的通道已被研究代替具有n+多晶矽閘 極遮蓋的通道’然而，高劑量（高於4E15原子/平方公分） 氮佈植將造成多晶矽閘極之片電阻大量的增加，因此元件 之性能將因此方式而被降級，一相關的文章為“ Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter-Micron Metal Oxide Field-Effect Transistors with Lightly Doped Drain Structure” , S. Shimizu, et al., Jpn. J. Appel. Phys., vol. 35，p.802, 1996，在 LDD n-MOS 中熱載子降級 因侧壁間隙壁中介面態或電子陷阱的產生而造成，關於 NICE結構，氮化閘氧化層在閘電極之下無法有效抑制介 面態電子陷阱的產生，如此，S. Shimizu提出一 NISW (nitrogen implantation in the silicon oxide sidewall spacers) 結構以解決前述的結果，此結果被抑制由於隔離氮原子造 成側壁間隙壁與石夕基材之間介面形成吊鍵（dangling bonds) 及弱鍵（weakened bonds) ° -3- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁) ，裝. 訂 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 明目的及概述： 根擄：本發明’提供—具有延長的淺源極與汲極接面之 一次微米CMOS，於一實施例中，利用適當製程於一基材 中建立一 N井與一 p井，隨後形成一薄氧化層於基材上作 為閑氧化層利用化學氣相沉積法於閘氧化層上沉積一未 接雜多晶石夕層’其次’ 一氮化矽層隨後形成於多晶矽層上 作為抗反射層（arc)，然後，未摻雜多晶矽層、抗反射層 (arc)及氧化層被钱刻個別形成極短通道多晶矽閘極於p 井與N井上’執行一熱回火法以修復蝕刻毁損的基材，並 產生一墊氧化層於多晶矽閘極與基材表面上。使用氮同步 摻雜製程或氮離子佈植製程，形成一氮摻雜非Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 __________B7 V. Description of the Invention () Mijg Leader: This invention relates to semiconductor elements, especially complementary metal-oxide-semiconductor (CMOS) elements. Love 1_Bright Background: With regard to the application of very large integrated circuits (ULSI), the component size has been reduced to the sub-micron or deep sub-micron range. The self-aligned metal silicide (SALICIDE) process is commonly used to reduce the gate, The method of source and drain resistance, so that a complementary metal-oxide-semiconductor (CMOS) device with a self-aligned metal silicide process can increase the operating speed. Recently, A. Hori et al. Proposed a component with a very shallow source-drain junction 'using the 5 KeV ion implantation method and rapid thermal tempering method, which can be used to suppress the short channel effect.' In this article, the source The poles and drains are extended by ion implantation to obtain extremely shallow contours. Please refer to the article by A. Hori et al. 'In IEDM Tech. Dig. P.485, 1994, named “A 0.05 μηη-CMO S with Ultra Shallow Source / Drain Junction Fabricated by 5 KeV Ion Implantation and Rapid Thermal Annealing ”° Regarding the application of ULSI circuits, the thickness of the gate oxide layer needs to be reduced to one billionth of a meter. Reliability becomes a serious problem of shortening components. 'Traditionally, the reliability of the gate oxide layer has been changed by many -2- This paper size applies to China National Standard (CNS) A4 specifications (2 丨 0X297 mm) (Please read the note on the back first Please fill in this page for matters) --IIII II I --A--Γ---L --- subscribe. 1: ---- J ——; -------------- Ministry of Economic Affairs Printed by A7 B7 of the Consumer Standards Cooperative of the Central Standards Bureau So that the supply _ 2 0 0 5 [mu] m S voltage of 2.5 volts to 2, in order to reduce hot-carrier properties of one of the main key element. In order to provide reliable metal-oxide-semiconductor field-effect transistors (MOSFETs), many MOSFET structures have been provided. 'For example, a conventional technique close to improving hot-carrier resistance uses a NICE (nitrgen implantation into CMOS gate electrode and source and drain). ) Structure, NICE structure proposed by T. Kuroi, et al., In IEDM Tech. Dig., P3 25,1 993, in this structure, the channel with p + polycrystalline silicon gate PMOS surface has been studied to replace the n + polycrystalline silicon gate Extremely covered channels' However, high doses (above 4E15 atoms / cm²) of nitrogen implantation will cause a large increase in the sheet resistance of polycrystalline silicon gates, so the performance of the components will be degraded in this way. A related article read " Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter-Micron Metal Oxide Field-Effect Transistors with Lightly Doped Drain Structure ", S. Shimizu, et al., Jpn. J. Appel. Phys., Vol. 35, p.802, In 1996, the degradation of hot carriers in LDD n-MOS was caused by the interface state or electron traps in the sidewall spacers. Regarding the NICE structure, the nitrided gate oxide layer is located on the gate electrode. Can not effectively suppress the generation of interface state electron traps. In this way, S. Shimizu proposed a NISW (nitrogen implantation in the silicon oxide sidewall spacers) structure to solve the foregoing results. Interfaces between substrates form dangling bonds and weakened bonds ° -3- This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before reading (Fill this page), binding. Order printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Purpose and summary: Root: The present invention 'provides — with extended shallow source and drain interface One-time micro CMOS, in one embodiment, an N-well and a p-well are established in a substrate by a suitable process, and then a thin oxide layer is formed on the substrate as a free oxide layer using chemical vapor deposition on the gate An undoped polycrystalline silicon layer is deposited on the oxide layer 'second', and a silicon nitride layer is subsequently formed on the polycrystalline silicon layer as an anti-reflection layer (ARC). The crystalline silicon layer, anti-reflection layer (arc) and oxide layer are individually carved into extremely short-channel polycrystalline silicon gates on p-well and N-well 'to perform a thermal tempering method to repair the etched damaged substrate and generate a pad of oxidation Layered on the surface of the polysilicon gate and the substrate. Use a nitrogen simultaneous doping process or a nitrogen ion implantation process to form a nitrogen-doped non-
極結構與塾氧化層上，其次，進行一離子佈植法以換J 質入閘極舆基材中，因而形成源極與汲極由一間隔約非晶 矽層厚度之閘極所隔離。於一含氧原子環境中執行一蒸2 氧化法以轉換一氮摻雜非晶矽層為—氮摻雜熱氧化矽層， 同時鄰近閘極結構之一極淺延長的源極與汲極接面利用非 晶矽層為一擴散源而得到，隨後氮摻雜氧化矽層被回蝕以 形成氮摻雜氧化間隙壁於閘極結構之側壁上，鈇 “、、说，除去 遮蓋氮化矽層以暴露出閘極，然後，使用已知的兩步驟金 屬矽化製程於暴露出之基材與閘極上分別形成自行對準金 屬矽化物（SALICIDE)與多晶矽化金屬。 4- 私紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)On the electrode structure and the plutonium oxide layer, an ion implantation method is performed in order to change the J-mass into the gate substrate, so that the source and the drain are separated by a gate separated by an amorphous silicon layer. A vaporization 2 oxidation method is performed in an oxygen-containing environment to convert a nitrogen-doped amorphous silicon layer to a nitrogen-doped thermal silicon oxide layer. At the same time, an extremely shallow extended source adjacent to the gate structure is connected to the drain. The surface is obtained by using an amorphous silicon layer as a diffusion source, and then the nitrogen-doped silicon oxide layer is etched back to form a nitrogen-doped oxide spacer on the side wall of the gate structure. Layer to expose the gate, and then use a known two-step metal silicidation process to form self-aligned metal silicide (SALICIDE) and polycrystalline silicon silicide on the exposed substrate and gate, respectively. National Standard (CNS) A4 Specification (210X297 mm) (Please read the precautions on the back before filling this page)
-----------一I— J_| 交！--I 、ΐΤ 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） a式簡單說明： 參考下述說明連同隨附圖式，此發明的前述觀點及許 多優點將變得更容易認識及了解，其中： 圖1為一半導體基材之截面圖，說明依據本發明形成 一墊氧化層於半導體基材上之步驟。 圖2為一半導體基材之截面圖，說明依據本發明形成 閘結構於半導體基材上之步驟。 圖3為一半導體基材之截面圖，說明依據本發明進行 一熱回火法之步驟。 圖4為一半導體基材之截面圖，說明依據本發明形成 一氮摻雜非晶矽層於半導體基材上之步驟。 圖5為一半導體基材之截面圖，說明依據本發明進行 一離子佈植法於半導體基材中之步驟。 圖6為一半導體基材之截面圖，說明依據本發明進行 一氧化法之步驟。 圖7為一半導體基材之截面圖，說明依據本發明進行 一蝕刻步驟以形成間隙壁之步驟。 圖8為一半導體基材之截面圖，說明依據本發明形成 一金屬層於半導體基材與閘極上之步驟。 圖9為一半導體基材之截面圖，說明依據本發明分別 形成金屬矽化物、多晶矽化金屬於基材與閘極上之步驟。 -5- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---1--.--— — ----IT-------、J (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 —^___________ 五、發明説明（） 〜 iu月祥細說明： 本發明提出一新潁的方法用以製造具有一極淺延長源 極與汲極接面之自行對準金屬矽化深次微米 CMOS電„曰 / 曰日 體’詳細說明如下述並連同隨附圖式。 參考圖1，一具有<100>結晶方向之單晶基材2用於 較佳實施例’在此實例中，厚的場氧化（F〇X)區域4建立 為隔離之目的’傳統上，FOX區域4經由一第一光阻及乾 式钮刻而建立以定義一氮化石夕-二氧化梦混合層，光阻去 除及濕式潔淨製程之後’於一含氧環境中進行熱氧化法以 形成FOX區域4 ’厚度約3000至8000A，然後氮化矽層 傳統地利用熱麟酸溶液除去，而二氧化石夕層利用稀釋Hf 或BOE溶液除去，然後雙井區形成於基材2中。· 隨後形成一薄的氧化層6於基材2上作為一閘氧化 層’在較佳實施例中’閘氧化層6為使用一氧蒸氣環境所 开> 之氧化發組成，溫度約攝氏8 0 〇至1 1 〇 〇度之間，閘氧 化層6可選擇性地使用其他已知氧化物化學組成及製程形 成’例如’閘氧化層6可為利用一化學氣相沉積製程形成 之二氧化矽’以TE0S為來源’溫度約攝氏6〇〇至8〇〇度 及壓力約0.1至10托耳（torr)，於較佳實施例中，閘氧化 層6之厚度約15至200 A。 參考圖2’石夕氧化層6形成之後，一未掺雜多晶矽層 8利用化學氣相沉積法沉積於閘氧化層6之上，其次，一 ______ -6- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐j -------;- (請先閱讀背面之注意事項再填寫本頁} 訂· 經濟部中央標準局員工消費合作社印製 A7 — B7 五、發明説明（） 氮化石夕層隨後形成於多晶石夕層8之上作為一抗反射層 (ARC)，然後未摻雜多晶矽層8、ARC層1 〇及氧化層ό被 钮刻分別形成極短通道多晶矽閘結構於ρ井及Ν井上。 下接圖3，進行一熱回火法約攝氏75〇至11〇〇度以 修復蝕刻毁損之基材2,產生一極薄墊氧化層12於多晶矽 閘極8表面及未被閘極8遮蓋之基材2表面上。----------- 一 I— J_ | Cross! --I 、 ΐΤ Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () A simple explanation: With reference to the following description and accompanying drawings, the foregoing ideas and many advantages of this invention will become more It is easy to recognize and understand, in which: FIG. 1 is a cross-sectional view of a semiconductor substrate, illustrating the steps of forming a pad oxide layer on the semiconductor substrate according to the present invention. FIG. 2 is a cross-sectional view of a semiconductor substrate, illustrating a step of forming a gate structure on the semiconductor substrate according to the present invention. Fig. 3 is a cross-sectional view of a semiconductor substrate, illustrating the steps of a thermal tempering method according to the present invention. FIG. 4 is a cross-sectional view of a semiconductor substrate, illustrating a step of forming a nitrogen-doped amorphous silicon layer on the semiconductor substrate according to the present invention. Fig. 5 is a sectional view of a semiconductor substrate, illustrating the steps of performing an ion implantation method in a semiconductor substrate according to the present invention. Fig. 6 is a cross-sectional view of a semiconductor substrate, illustrating the steps of performing an oxidation method according to the present invention. Fig. 7 is a cross-sectional view of a semiconductor substrate, illustrating a step of performing an etching step to form a spacer according to the present invention. FIG. 8 is a cross-sectional view of a semiconductor substrate, illustrating a step of forming a metal layer on the semiconductor substrate and the gate electrode according to the present invention. FIG. 9 is a cross-sectional view of a semiconductor substrate, illustrating the steps of forming a metal silicide and a polycrystalline metal silicide on a substrate and a gate, respectively, according to the present invention. -5- This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) --- 1 --.--------- IT -------, J (Please read and read first Note on the back, please fill in this page again.) Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. A7 — ^ ___________ V. Description of the invention () ~ iu Yuexiang Detailed description: The present invention proposes a novel method for manufacturing a pole The self-aligned metal silicided deep sub-micron CMOS electrical device with shallow extended source-drain interface is described in detail below with the accompanying drawings. Referring to FIG. 1, a crystal structure with < 100 > The single crystal substrate 2 is used in the preferred embodiment, "In this example, a thick field oxide (FOX) region 4 is established for isolation purposes." Traditionally, the FOX region 4 is passed through a first photoresist and a dry button. Established to define a mixed layer of nitrided oxide-Dream dioxide, after photoresist removal and wet cleaning process, 'the thermal oxidation method is performed in an oxygen-containing environment to form a FOX region 4' with a thickness of about 3000 to 8000A, and then nitrogen The siliconized layer is traditionally removed using a hot linoleic acid solution, while the dioxide layer is diluted with Hf or BOE The solution is removed, and then a double well region is formed in the substrate 2. Subsequently, a thin oxide layer 6 is formed on the substrate 2 as a gate oxide layer. In a preferred embodiment, the gate oxide layer 6 uses an oxygen vapor. The temperature is about 800 ° C to 1100 ° C. The gate oxide layer 6 can optionally use other known oxide chemical compositions and processes to form 'such as' gate oxide layers. 6 can be silicon dioxide formed by a chemical vapor deposition process using TEOS as a source, with a temperature of about 600 to 800 degrees Celsius and a pressure of about 0.1 to 10 torr, in a preferred embodiment The thickness of the gate oxide layer 6 is about 15 to 200 A. Referring to FIG. 2 ', after the formation of the stone evening oxide layer 6, an undoped polycrystalline silicon layer 8 is deposited on the gate oxide layer 6 by chemical vapor deposition. Second, a ______ -6- This paper size applies Chinese National Standard (CNS) A4 specification (210X297mm j -------;-(Please read the precautions on the back before filling this page}) A7 — B7 printed by the Bureau ’s Consumer Cooperatives V. Description of the invention It is formed on the polycrystalline silicon layer 8 as an anti-reflection layer (ARC), and then the undoped polycrystalline silicon layer 8, the ARC layer 10 and the oxide layer are respectively pressed to form a very short channel polycrystalline silicon gate structure. Well N. Going to Figure 3 below, a thermal tempering method is used to repair the damaged substrate 2 at about 75 to 1100 degrees Celsius, and an extremely thin pad oxide layer 12 is formed on the surface of the polycrystalline silicon gate 8 and not gated. The electrode 8 covers the surface of the substrate 2.
參考圖4，形成一氮摻雜非晶矽層丨4於閘極結構與 墊氧化層12上，最好利用由τ. K〇bayashi，et &1,，& IEDMReferring to FIG. 4, a nitrogen-doped amorphous silicon layer 丨 4 is formed on the gate structure and the pad oxide layer 12, preferably using τ. Kobayashi, et & 1, & IEDM
Tech. Dig.，P.683, 1 994所提出之一氮同步摻雜多晶矽緩衝 方法，在此步驟中，氮同步摻雜非晶矽層14以si2H6_NH3 氣體系統攝氏500度下形成，氮濃度約1E18至1E21 at〇ms/ 立方公分’氮同步摻雜非晶矽層14厚度約400至i5〇〇A， 氮同步摻雜非晶矽層14可選擇.性地首先利用沉積一非晶 矽而形成，然後，一含氮原子離子佈植法隨後被執行摻雜 離子入非晶矽層，因此形成氮同步摻雜非晶矽層14。其他 方法，例如背景中提到分別由A. H〇ri及τ Kur〇i所提之 方向可用於此，氮同步摻雜非晶矽層14展示兩個優點， 第一，矽層於氧化過程中保留一微結晶體，以及另外，氮 同步摻雜非晶矽層1 4之氧化速率較非摻雜矽慢。 進行一離子佈植法以摻雜摻質入閘極8與基材2中， 因而形成源極與汲極由一閘極結構所隔離，包含具有一約 非晶矽層14厚度之間隙壁之閘極8 ’如圖5，摻質最好分 别包括神、麟或將它組合用於NM〇s元件，以及硼或 ( CNS ) --：— I-------「.裝-- (請先閱讀背面之注意事項再填寫本頁) 、?τ A7 B7 經濟部中央標準局員工消費合作社印製 五 '發明説明（ 或將組合用於PMOS元#。处θ如… b I與佈植劑量分別為約0.5 至12〇KeV及5E14至5E16原子/平方公分。 接續圖6，於含氧環境中谁并_ v & 订 蒸瑕•氧化法以轉變氮 雜非晶梦層14為·一氮換雜 q 孔修雜熱氧化矽層1 8，於一案例中， 此步驟之溫度約攝氏800至1150度範圍。同時，鄰於閘 極結構一極淺延長源極與汲極介面20利用非晶矽層14為 一擴散源而得到，一關於此方法之文章由s. L_ wu，et ai.， in IEEE Trans. Electron Devices, Y〇l. ED-40, p.1 797, 1 993 所提出，此論文中，利用一 SAS (堆疊非晶矽）為摻雜擴散 源形成高效能淺接面二極體。隨後氮摻雜氧化矽層1 8以 非等向性回韻形成氮摻雜氧化間隙壁丨8於閘結構之側壁 上’結果結構說明於圖7中。 接續圖8 ’除去遮蓋氮化矽層1 〇以暴露出閘極8，可 藉熱碌酸溶液方法完成’然後自行對準金屬；5夕化物 (SALICIDE)24及多晶矽化金屬26分別形成於暴露出之基 材2與閘極8上，傳統上可利用已知製程達成，例如，一 情性的或貴重的金屬層22，如Ti，Pt, Co, W，Ni，Pd，Cr等 被濺鍍於基材2、間隙壁18及閘極8上，然後，進行一快 速熱回火（RTA)K N2環境中攝氏350至700度下，使濺鍍 的金屬與多晶矽閘極8及矽基材2反應，因此形成金屬石夕 化物於這些部分上。然後一剝除步驟除去側壁間隙壁 18 上未反應的金屬，如此，自行對準金屬矽化物24及多晶 矽化金屬26自行對準形成於這些區域上。 -8- ^紙張尺度適用中國國家標準（CNS ) A4規格（21〇'〆297公釐〉 I------^--ο裝-------訂 ------- (請先鬩讀背面之注意事項再填寫本頁) A7 ----------- 五、發明説明（ ） 由以上揭露可了解’本發明提供下列優點：）利用 自行對準金屬發化物及延長源極與汲極介面技術可增加元 件f生能’（2)延長的極淺接面結構可利用間隙壁為一擴散源 而仵到，用以抑制短通道效應或逆短通道效應，請參考一 文章由 P G V τ . , • . Tsui，et al.，in IEDM Tech. Dig.，p.5〇l，1 994 所提出；（3)閘極之片電阻可利用遮蓋氮化矽層為一氮佈植 阻障而被抵擋。 本發明以一較佳實施例說明如上，僅用於藉以幫助了 、本發月之實施，非用以限定本發明之精神，而熟悉此領 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 範圍内，當可作些許更動潤飾及等同之變化替換，其專利 保護範圍當視後附之申請專利範圍及其等同嘮域而定。 ------^--:"裝------訂！----1)^ (請先閱讀背面之注意事項再填寫本頁) 準 標 國 國 中 用 適 度 尺 張 紙 _本 經濟部中央標準局員工消費合作社印製Tech. Dig., P.683, 1 994 proposed a nitrogen synchronously doped polycrystalline silicon buffer method. In this step, the nitrogen synchronously doped amorphous silicon layer 14 is formed at a temperature of 500 ° C in a si2H6_NH3 gas system, and the nitrogen concentration is about 1E18 to 1E21 at 0ms / cm 3 'N synchronously doped amorphous silicon layer 14 has a thickness of about 400 to i500A. Nitrogen synchronously doped amorphous silicon layer 14 is optional. First, an amorphous silicon is deposited by Forming, and then, a nitrogen atom-containing ion implantation method is subsequently performed to dope ions into the amorphous silicon layer, thereby forming a nitrogen-doped amorphous silicon layer 14 simultaneously. Other methods, such as those mentioned in the background by A. Hori and τ Kur〇i, can be used for this purpose. Nitrogen synchronously doped amorphous silicon layer 14 shows two advantages. First, the silicon layer undergoes an oxidation process. A microcrystal remains in the substrate, and the oxidation rate of the nitrogen-doped amorphous silicon layer 14 is slower than that of the undoped silicon. An ion implantation method is used to dopant dopants into the gate 8 and the substrate 2 so that the source and the drain are separated by a gate structure, including a spacer having a thickness of approximately 14 Å. The gate electrode 8 'is shown in FIG. 5. The dopants preferably include Shen, Lin, or a combination of them for NMOS devices, and boron or (CNS)-:-I ---- --- ". 装- -(Please read the precautions on the back before filling out this page),? Τ A7 B7 Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China to print the 5 'invention description (or use the combination for PMOS Yuan #. The implantation doses are about 0.5 to 120 KeV and 5E14 to 5E16 atoms / cm 2. Continuing with Figure 6, who does _ v & order steaming and oxidation in an oxygen-containing environment to transform the aza-amorphous dream layer 14 A nitrogen-doped q-hole repaired thermal silicon oxide layer 18 is used. In one case, the temperature of this step is about 800 to 1150 degrees Celsius. At the same time, the source and drain electrodes are extended very shallowly next to the gate structure. The interface 20 is obtained by using the amorphous silicon layer 14 as a diffusion source. An article on this method is provided by s. L_wu, et ai., In IEEE Trans. Electron Devices, Y〇l. ED -40, p.1 797, 1 993. In this paper, a SAS (stacked amorphous silicon) is used as a doped diffusion source to form a high-performance shallow junction diode. Subsequent nitrogen-doped silicon oxide layer 1 8 A non-isotropic rhyme is used to form a nitrogen-doped oxide spacer on the sidewall of the gate structure. The resulting structure is illustrated in Figure 7. Continued from Figure 8 'removing the masking silicon nitride layer 10 to expose the gate electrode 8, It can be done by the hot acid solution method and then align the metal by itself; SALICIDE 24 and polycrystalline silicon silicide metal 26 are formed on the exposed substrate 2 and gate 8, respectively. Traditionally, it can be achieved by known processes. For example, an emotional or precious metal layer 22 such as Ti, Pt, Co, W, Ni, Pd, Cr, etc. is sputtered on the substrate 2, the spacer 18, and the gate 8, and then, a In the rapid thermal tempering (RTA) K N2 environment, the sputtered metal reacts with the polycrystalline silicon gate 8 and the silicon substrate 2 at a temperature of 350 to 700 degrees Celsius, so a metal oxide is formed on these parts. Then it is stripped Step to remove unreacted metal on the side wall spacer 18, so that the metal silicide 24 and the polycrystalline silicon silicide 2 are aligned by themselves 6 Self-alignment is formed on these areas. -8- ^ The paper size applies the Chinese National Standard (CNS) A4 specification (21〇'〆297mm> I ------ ^-ο equipment ---- --- Order ------- (Please read the precautions on the back before filling out this page) A7 ----------- 5. Description of the invention () From the above disclosure, you can understand 'this The invention provides the following advantages :) The use of self-aligned metal compounds and extended source and drain interface technology can increase the element's energy generation. (2) The extended very shallow junction structure can be achieved by using a partition wall as a diffusion source. To suppress the short-channel effect or reverse short-channel effect, please refer to an article proposed by PGV τ., •. Tsui, et al., In IEDM Tech. Dig., P. 501, 1 994; (3 The gate resistor can be resisted by covering the silicon nitride layer as a nitrogen implant barrier. The present invention is described above with a preferred embodiment, which is only used to help, the implementation of this month, not to limit the spirit of the present invention, and those skilled in the art will not depart from the spirit of the present invention. Within the spirit of the present invention, when some modifications and equivalent changes can be made, the scope of patent protection shall depend on the scope of the attached patent application and its equivalent scope. ------ ^-: " Equipment ------ Order! ---- 1) ^ (Please read the precautions on the back before filling this page) Applicable Standards Country China Moderate Rule Sheets _ This is printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs