TW444281B - Manufacturing method for deep submicron CMOS transistor - Google Patents

Abstract

The present invention comprises forming the gate structure and a silicon nitride spacer on the sidewall of the gate; next, removing the ARC and the silicon nitride spacer; conducting the first ion implantation to form the doping area in the N-well; conducting the second ion implantation to form the doping area in the P-well; conducting an oxidation to convert the nitrogen-doped amorphous silicon layer into a nitrogen-doped thermal silicon oxide layer and also forming extended source and drain interface using the amorphous silicon layer as a diffusion source; then, forming a silicon nitride layer and conducting an anisotropic back-etching to form the silicon nitride spacer on the sidewall of the gate structure; and, forming the self-aligned metal silicide and polysilicon metal on the exposed substrate and the gate respectively.

Description

Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs of the Industrial and Commercial Cooperatives rV 4 442 8 < V. Description of the Invention () Field of the Invention: The present invention relates to semiconductor devices, especially to complementary metal-oxide-semiconductor (CMOS) devices. Invention: For the application of ultra large integrated circuits (uL SI), the component size has been reduced to the sub-micron or deep sub-micron range, and the self-aligned metal silicide (SALIC IDE) process is a widely used to reduce the gate The method of source and drain resistance. 'So, a complementary metal-oxide-semiconductor (CMOS) device with a self-aligned metal silicide process can increase the operating speed.

-V A method called SAS (stackedamr: p .h 〇ussi 1 ic ο η) is disclosed in the following documents. The literature on this method is by .s. L. Wu, et al., In IEEE Trans. Electron Devices, Vol. ED-40 ;, p. 1797; 1993 proposed 'in this paper' to use a SAS (stacked amorphous stone) to form a high-efficiency shallow junction diode for a dopant diffusion source. The ultra-shallow junction; and the electrode and the source can use heat treatment to diffuse ions into the substrate °..... Recently, A. 〇 〇 et al. Proposed a device with an extremely shallow source and non-electrode interface, using 5 KeV ion implantation method and rapid thermal tempering method, this method can be used to suppress the short-channel effect. In this article, the source and drain are extended to use... ....... -2- This paper music scale is applicable to Chinese cabinet standards (CNS) Λ4 is present (210X 297 public trend) H ί I— —l11- -I *. I--IT— 1-In I 1 · 1--- In 1-i ------ (Please read the notes on the back before filling in this page) The Intellectual Property Office of the Ministry of Economic Affairs :: Printed by Shellfish ^ Fee Cooperatives " 4442 81 、 ____ Β 5. Description of Invention () The sub-planting method is used to produce extremely shallow contours. Please refer to the article mentioned by A. Hori et al., In IEDM Tech. Dig. P.485, 1994, named “A0.05 μηι-CMOS with Ultra Shallow Source / Drain Junction Fabricated by 5 KeV Ion Implantation and Rapid Thermal Annealing. " Regarding the application of ULSI circuits, the thickness of the gate oxide layer needs to be reduced to one billionth of a meter. Therefore, the reliability of the extremely thin oxide layer has become a serious problem in shortening components. Traditionally, the reliability of the gate oxide layer Due to many factors, for example, even if the supply voltage of 0.2 5 micron M 0 S drops to 2.5 volts, hot carriers are one of the main keys to reducing the performance of the device. In order to provide reliable gold field effect transistors (MOSFETs), many MOSFET structures have been provided, for example, a conventional technique close to improving the hot-carrier resistance uses one ... .... · NIC E (nitrogen implantation into CMOS gate., .ele.ctro.de, and '/. source and drain) structure, NICE i Gyrostructure by T. Kuroi', ._. et.aL, in I EDM Tech, D i g., p3 In this structure, channels with multiple 'silicon gate PMOS surfaces have been studied to replace channels with η' polycrystalline sand and gate cover. However, high-dose (higher than 4E15 atoms / cm 2) Nitrogen implantation will cause a large increase in the sheet resistance of polycrystalline silicon gates, so the performance of components will be degraded due to this method. A related article is "Impact of

Nitrogen Implantation on Hi g h 1 y Reliable Sub-Quarter-

Micron Metal Oxide Field-Effect Transistors with Lightly

Doped Drain Structure ", S. Shimizu, et al., J pn. J. Appel. -------------------- -------- 3 * This standard is applicable to China National Standards (CNS) / \ Xingge (210X297 material (-, please read the two notes before filling in this guide)

άάά2 8 Λ 7 Η7 V. Description of the invention ()

Phys .. vol. 3 5, p. 802. 1996. Degradation of hot carriers in LDD n-MOS caused by the interface state or electron traps in the sidewall spacer. 'About N IC E structure, nitrided gate oxide layer It is not possible to effectively suppress the generation of interface state electron traps under the gate electrode. Thus, Shimizu proposed a NISW (nitrogen implantation in the silicon oxide sidewall spacers) structure to solve the aforementioned result. This result was suppressed due to the isolation of nitrogen atoms. The interface between the wall gap wall and the silicon substrate forms a dang1 in§ bond, Sl 41 M (weakened bonds) ° and the like. The purpose and summary of the present invention is to provide an extended shallow source and drain connection. One of the sub-micron CMOS. ..... The present invention includes forming a field oxide insulation region, and subsequently forming a thin oxide layer on the substrate as a gate oxide layer. An undoped polycrystalline silicon layer utilizes a chemical vapor phase. Deposition method is deposited on the gate oxide layer. 'Second, a silicon nitride layer is subsequently formed on the polycrystalline silicon layer as an anti-reflection layer (ARC). A very short channel polycrystalline stone gate structure is formed on wells P and N. A thermal tempering process is performed to generate a thin pad oxide layer on the surface of the polycrystalline silicon gate and the surface of the substrate that is not covered by the gate. Form one. The amorphous amorphous silicon layer is on the interlayer structure and the pad oxide layer. -4- The good standard of this paper is applicable to the Chinese standard for house (CN'S) Λ4 is now (2 丨 0X297 public box) (-Please read the precautions on the back before filling this page) Printed by the consumer cooperative, printed by the Intellectual Property Office of the Ministry of Economic Affairs, and printed by the cooperative, printed by AAA2 8 1 Λ7 Ιΐ7 V. Description of the invention ()-The silicon nitride gap sidewall is formed on the gate sidewall. Then, the ARC and the silicon nitride gap wall are removed. The silicon nitride gap sidewall is favorable for forming an L-shaped structure adjacent to the gate. A low-energy, high-dose ion implantation method is used to implant dopants into the interrogator and the substrate, thereby forming doped regions. The dopant preferably includes boron and BF 2 or a combination thereof for the P M 0S element. The energy and implantation dose are about 0.5 to 120 K e ν and 5 Ε 1 4 to 5E16 atoms / cm 2, respectively. The photoresist is successively covered on N 丼, and a second ion implantation method is performed to implant the dopant into the gate and the substrate, thereby forming a doped region. Dopants include arsenic, phosphorus, or a combination thereof for NMOS devices. The energy and implantation dose are about 0.5 to 120 K e V and 5 E 1 4 to 5 E 1 6 * atom / cm 2, respectively. Perform an oxidation method in an oxygen-containing environment to convert the nitrogen-doped amorphous silicon layer into a nitrogen-doped thermal silicon oxide layer. At the same time, it is adjacent to the gate structure, a very shallow source and drain interface, and an extended source and drain. The interface is obtained by using the amorphous silicon layer and the substrate ions as a diffusion source. Then 'form a silicon nitride layer. 丨.' .. Then apply an anisotropic return button to form a nitrided sand gap sidewall on the side wall of the closed structure, and self-align the metal oxide (SALICI.DE) and more Spar crystals are formed on the exposed substrate and gate, respectively. «Style ffi mushroom description: * '

J With reference to the following description and accompanying drawings, the above-mentioned viewpoints and many advantages of this invention will become easier to recognize and understand. 'Among them :. The first figure is a surface view of a semiconductor substrate, illustrating the This paper size is applicable to the National Standard for Valves (CNS) 8-4 specifications (2I0XW7 males) --.---; ------ ^ ------ 1T ------ 4 (please first (Please read the notes on the back and fill in this page) A7 Printed by the Consumers Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, B7. 5. Description of the invention () Steps to form a pad on the semiconductor substrate. The second figure is a cross-sectional view of a semiconductor substrate, illustrating the steps of forming a gate structure on the semiconductor substrate according to the present invention. The third figure is a cross-sectional view of a semiconductor substrate, illustrating the steps of performing a thermal tempering method according to the present invention. The fourth figure is a cross-sectional view of a semiconductor substrate, illustrating the steps for forming a nitrogen-doped amorphous silicon layer on a rich conductor substrate according to the present invention. The fifth figure is a cutaway view of a semiconductor substrate, illustrating the steps of forming a silicon nitride gap sidewall on a semiconductor substrate according to the present invention. The sixth figure is a cross section of a semiconductor substrate 圊 'illustrating the steps of removing the gap sidewall and the cover layer according to the present invention. The seventh figure is a cross-sectional view of a semiconductor substrate, illustrating the steps of performing an ion implantation according to the present invention. The eighth figure is a cross-sectional view of a semiconductor substrate in winter, illustrating the steps of performing the second ion implantation on the substrate of the abundant conductor according to the present invention. '. +... .. The ninth figure is a cross-sectional view of a semiconductor substrate' and illustrates the steps of performing the thermal oxidation according to the present invention. The tenth figure is a winter cut surface view of a semiconductor substrate ', illustrating the steps of removing the gap sidewall according to the present invention. .,,.! ++ Figure 11 is a cross-sectional view of a semiconductor substrate, illustrating the steps of forming a metal silicide and polycrystalline silicon north metal on the substrate and the interlayer according to the invention. {Please read the precautions on the back before filling this page) _-6- This paper size is applicable to the Chinese family standard (CNS) Λ4 specification (210X297 mm) The Ministry of Economic Affairs of the Ministry of Economic Affairs, the Ministry of Economic Affairs and the Ministry of Economic Affairs, the Ministry of Economic Affairs and the Ministry of Economic Affairs and Economic Cooperation said that AAA2 81 Λ7 Β V. Description of the invention () Detailed description of the invention: The present invention proposes a new method for manufacturing self-aligned metal silicide deep submicron C Μ 0 S electricity with a very shallow extended source-drain interface. The crystals are described in detail below together with the accompanying drawings. Referring to FIG. 1, a single crystal substrate 2 having a crystal orientation of < 1 00 > is used in a preferred embodiment. In this example, the 'thickness field oxidation (F 0X) region 4 is established as an isolation purpose_ , Traditionally, the 1 F Ο X region 4 is established by a first photoresist and dry etching to define a silicon nitride-silicon dioxide mixed layer 'after the photoresist removal and wet cleaning process' in an oxygen-containing environment A thermal gasification method is performed to form a F 0 X region 4 with a thickness of about 30000 to 80000 people. Then the silicon nitride layer is conventionally removed using a hot phosphorous solution, and the silicon dioxide layer is diluted with .HF Or the B 0 E solution is removed, and then a double well region is formed in the substrate 2. '^. Subsequently, a thin oxide layer 6 is formed on the substrate 2 as a gate oxide layer. In a preferred embodiment, the gate oxide layer: 6 is a silicon oxide composition formed using an oxygen vapor environment. , The temperature is about 8000 to 110 degrees Celsius, the gate gasification layer 6 can optionally use other known oxides chemical composition and process shape ...

... S into, for example, the gate-forming layer 6 may be a silicon dioxide formed using a chemical vapor deposition process: using TEOS as a source, with a temperature of about 600 to 800 degrees Celsius and a pressure of about 0.1 To 10 Torr (t0 rr), in the preferred embodiment, the thickness of the gate oxide layer 6 is about 15 to 200 A. In addition, the gate oxide layer can also use wood paper hat ruler yil applicable to the ten-valve valve family standard (CNS) A4ASL grid (210x2y7 common) ft Shi K ----- In n T n] I nn (Please read the back first Please note this page and fill in this page again) Λ · 4 p ft 1 A7 ____ B7 V. Description of the invention () The gasification stone 1 formed in the JVD system 1 means ^ deP〇SltlOn. The gasification debris produced by JVD has better electrical properties and lower leakage current than silicon oxide, and its ability to prevent boron penetration is also better. Usually, it can be deposited at room temperature, and then 800-850. 〇Heat treatment. Referring to the second figure, after the formation of silicidation & 6, an undoped polycrystalline silicon layer 8 is deposited on the gate oxide layer 6 by chemical vapor deposition, followed by a 'silicon nitride layer is subsequently formed on the polycrystalline silicon layer 8 As an anti-reflection layer (ARC), the undoped polycrystalline silicon layer 8, the ARC layer 10 and the oxide layer 6 are etched to form a very short channel polycrystalline silicon gate structure on the p-well and the N-well, respectively. Next, the second step is carried out-the thermal tempering method is used to repair the damaged substrate 2 at about 75 to 1100 degrees Celsius β, resulting in: a very thin pad oxide layer 2 on the surface of the polycrystalline silicon gate 8 and not gated The electrode 8 covers the surface of the substrate 2. Referring to the fourth figure, a nitrogen-doped amorphous silicon layer M is formed on the gate structure and the pad oxide layer 12, preferably by T. Kobayashi, et al., In IEDM Tech. D lg, p. 6 8 3 'One of the nitrogen synchronously doped polycrystalline silicon buffer methods proposed by 1 9 94' In this step, the ytterbium synchronously doped amorphous silicon layer 14 is formed at a temperature of 500 degrees with a S.l 2H6-NH3 gas system, and the nitrogen degree is about 1 e〗 8 to 1 E2 Patorns / cubic centimeter, I synchronously doped amorphous silicon layer 44 has a thickness of about 400 to 1500 A, and nitrogen synchronously doped amorphous silicon layer 14 may be formed by first depositing an amorphous silicon selectively. Then, an argon-containing atomic ion implantation method was subsequently performed to dope this paper. The national standard (CNS) Λ4 specification (210X297 mm);, I n I iu I nu III .. ^-(please first Read the note on the back and write this page again) Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4442 81 A 7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () 1 1 Ion-into amorphous silicon Layer 1 thus forms a nitrogen synchronous doped amorphous stone layer 14 0 Other 1 1 Method example As mentioned in the background, the II direction mentioned by A. Hori and T. Kur 01 can be used for this J. Nitrogen synchronously doped amorphous silicon layer 14 shows two advantages J Please 1 first 1 first 1 silicon layer is oxidized A microcrystal remains during the process, and in addition > Nitrogen reading 1 1 ii, the synchronously doped amorphous silicon layer 14 has a slower oxidation rate than the non-doped silicon.面 意 1 ί Refer to the fifth figure 9 a fl fossil evening gap side. Wall 16 is formed on the side of the gate 1 [fill] on the wall 〇 To achieve this step, a silicon nitride is deposited first, and then executed-write The nitrogen-filled page 1 can be obtained by the anisotropic etching process. The above-mentioned gap sidewall 16 Q doped amorphous silicon is also etched in this step, so it only remains on the gate sidewall 1 and the silicon nitride gap sidewall. 1 6 below. Then > remove the cover layer (ARC) 10 with! I and the silicon nitride gap side wall 16 as shown in the sixth figure. The silicon nitride gap 1 and the side wall 16 are favorable for forming an L-shaped junction; 嗔 14 η: connected to the -gate. L 'f. The direction of the structure 1 1 14 lies horizontally on the substrate 2 σ It is worth noting that-·, on the gate ... ί I is exposed accordingly 〇1 |-: · _ See Figure 7 for low energy The high-dose ion implantation method implants doped i 1 into the gate 8 and the substrate 2 to form a doped region 20 0. In this 1 I step, the P well is controlled by a photoresist 18. This miscellaneous area is about a distance from gate 1 II about the same width as the sidewall of the silicon gap. The dopant table preferably includes boron and 1 1 bf2 or a combination of the above for PMOS devices. The energy and implantation dose L 1 1 are about 0.5 to 1 20 K eV and 5E14 to 5E1 6 atoms / cm 2 0 Special II Please note that 1 is located in the L-shaped structure after the above-mentioned doping.] 1 of 1 below 1 1 1 -9- 1 i 1 This paper size applies to the Chinese National Standard (CNS 丨 Ad Specification (210X29 ·?)) Ministry of Economic Affairs Central Standards Bureau, Shellfish Consumer Cooperative, Yinfan 4442 81 A7 ________ B7 _ __ V. Description of the invention () The substrate concentration is less than the area covered by the L-shaped structure 1 4. Then the photoresist 18 is removed. Continue to the eighth figure and cover the light Resist 22 over N wells 'for the second ion implantation method to implant dopants into gate 8 and substrate 2' thus forming doped regions 24 = perform this doping with low energy and high dose in this step The impurity region 24 is about a distance from the gate and about the same width as the sidewall of the nitrogen and silicon gap. The dopants preferably include arsenic, phosphorus, or a combination of the above for NMOS devices. The energy and implant dose are about 0.5 to 120 KeV And 5E14 to 5E16 Sub-cm per square centimeter. It is particularly noted that after the above doping, the concentration of the substrate 'under the L-shaped structure 14 is less than the area covered by the L-shaped structure 14. Then the photoresist 22 is removed. The order can be reversed. Referring to the ninth figure, a tritium method is performed in an oxygen-containing environment to change the argon doping ........ Silicon layer 14a 'Yi, Example •-· *, *' 'Circle., ..--, .. The temperature of this step is about 800 to 1150 degrees Celsius. At the same time, it is adjacent to the gate structure 1 Extremely shallow source and drain interfaces 20a, 24a and extended source and drain interfaces 20b, 24b are obtained using the ions of the amorphous silicon layer 14 and the substrate as a diffusion source. An article on this method is provided by S.L .. Wu, et ah in IEEE Trans. Electron Devices, Vol. ED-40, p 1797 1993 ^ 'In this paper, a SAS (stacked amorphous layer) is used to form a high-performance shallow junction for a doped diffusion source. Polar body. _____- 10- This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) --- · ---'------ install --- ^ ---- order ------ Travel (Please read the notes on the back before filling this page)

Cx / \ Α0 9, \ V. Description of the invention () Subsequently, a silicon nitride layer is formed, and then anisotropic etchback is performed to form a silicon nitride gap sidewall 26 on the gate wall of the gate structure. The resulting structure is described in Figure +. The oxide layer 14 a, which is covered by the gap sidewalls, is removed above the gate. Continuing the eleventh figure, the self-aligned metal silicide (SALIC IDE) 30 and the polycrystalline metal silicide 28 are formed on the exposed substrate 2 and the gate 8, respectively. Traditionally, it can be achieved by a known process. For example, a Refractory or precious metal layers, such as Ti, Pt.Co.W. Ni.Pd, Cr, etc .; base bonds on the substrate 2, the spacer 26 and the gate 8, and then a rapid thermal tempering (RTA ) At a temperature of 350 to 700 degrees Celsius in the N: environment, the sputtered metal is allowed to react with the polycrystalline silicon gate 8 and the broken substrate 2 to thereby form metal compounds on these parts. Then a stripping step removes the unreacted metal on the side wall spacer 26, such as .. '.t. ....., and so, self-aligns the metal silicide 3 0 and more; the crystal silicide metal 2 8 Since: 'Line alignment •... Is formed on these areas: I' ...-·. '-. ·........... As can be understood from the above disclosure, the present invention provides the following advantages : (1) the use of self-aligned metal silicide and extended source and drain interface technology can increase device performance; (2) extended very shallow junction structure can be used as a diffusion source. .. :: + ·. · Get. To suppress short-channel effect or inverse short-channel effect ', please refer to the article " v.'. 1 .. _ Chapter by .P. G.. Y. Ts ui , Eta 1., in IED M Te ch. Dig., P.50I; 1994; (3) Drain / source and extended drain / source of P Μ OS or NM 0 S use primary ions Implantation is complete. _____ This paper size is applicable to the 屮 valve 屮 Song standard (CNS) Λ4 is now (public release) I. Read the precautions before filling in this page Printed 4442 81 A7 B7 V. Description of the Invention The invention is described above with a preferred embodiment, and is only used to help understand the implementation of the invention. It is not intended to limit the spirit of the invention, and those skilled in the art will be familiar with After comprehending the spirit of the present invention, without departing from the spirit of the present invention, when it can be modified and replaced equivalently, its patent protection scope depends on the attached patent application scope and its equivalent fields. (Please read the precautions on the back before filling out this page) Printed by Shellfish Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs -12- This paper size applies to the Chinese Standard (CNS) A4 (210X297 mm)

Claims (1)

4442 81 in Contains as little as French element SοΜ C / | \ Body conduction semi-oxygen gold supplementary forming shape Xuanxuan => ρ is used as the upper layer electricity; dielectric electrode base conduction half is p = layer electricity Multi-hybrid doped gates are not metaphysical poles, and blue S & M C-radiation resistance is used as the upper layer of silicon crystals. 'The stratified gas should be formed at the moment 0, 0, 0; the upper engraving material is based on the body, and is repaired by the method of semi-reduction. '-^ 系 · " · " Fill " Ben · £, Attach the knot; The upper gate structure should be connected; the upper pole gate should be closed, the surface of the oxygen material and a grassroots body are formed into a half when the oxygen is conducted. The same layer should cover the dream, cover the crystal. The non-basic structure of the structure is doped with the gate nitrogen, and the structured junction emitter of the undeformed and destroyed structure should be reversed. Silicon between the side wall and the side gap of the wall. The silicide nitrogen IL should be removed to dope nitrogen. The semi-conductive by the guide .: The pole gate. The dopant doped with the structural junction. The plant-type cloth is separated into a set of first-layer silicon lines. _ _ _! Central Standards Bureau of the Ministry of Economic Affairs Industrial Consumer Cooperative Co., Ltd. printed half of the gate and gate; the domain into the region doped doped with dopants. The doping method using a well method, a plant is formed into a sub-shape, the first material is the substrate oxygen. Turn doped IL one into; layered silicon region crystals are not mixed. # 杂 之 'doped nitrogen well iridium II · change the first: converted into shape to reduce the oxygen, a material to the substrate half pole the gate to S- 5 The long-adjacent surface layer is connected to the silicon dioxide crystal and the hetero-electrode doped source gas. The formation is the same, due to the layer, the guide material base; the paper size is applicable. Chinese National Standard (CNS) 8 4 (210X297 mm) 4442 81 8 8 8 8 ABCD Printed by the Consumers' Cooperatives of the Zhongli Bureau of the Ministry of Economic Affairs 6. Apply for a patent to form a gap side wall on the side of the gate structure Up · 'remove the nitrided layer; and form a self-alignment It is a silicide (SALICiDE) on the semiconductor substrate and a polycrystalline silicon oxide on the electrode 2. The method of the first item of the scope of the patent application 'wherein the above-mentioned gas-exchanged amorphous silicon layer uses a synchronous doping process Forming ° 3. The method according to item 2 of the patent application range, wherein the synchronous doping process described above is performed with Si 2 H 6 -NH 5 gas. 4. The method according to item 1 of the scope of patent application further includes the following steps to form the above-mentioned nitrogen-doped amorphous silicon layer ,: forming an amorphous silicon layer on the above-mentioned finalizing layer and the above-mentioned closed-electrode structure ... ..; And an ion implantation method to remove the impurity I into the above amorphous stone layer. 5. The method according to item 1 of the scope of patent application, wherein the above-mentioned thermal tempering method is performed at a temperature of about 750 to Π ° C. 6. The method according to item 1 of the scope of patent application, wherein the first ion implanting energy is about 0.5 to 120 KeV. -14- Wooden identification applies the national standard (CNS) A4 specification according to the standard 2) 0 X mm) (Please read the precautions on the back before filling in this purchase)--1-I ..... Order ♦ _-----.—— 4442 81 \ Λ D8 The scope of patent application is the method of the first scope of patent application, where the first ion mentioned above) dose is about 5E14 to 5E16 atoms / cm 2 ° The method of the first scope of the patent application 'where the above-mentioned second ion implantation energy is about 0.5 to 120 KeV " The method of the first scope of the patent application' where the above-mentioned second ion cloth 'is about 5 E 1 4 to 5 E 1 6 atoms / cm 2. Please read it first The method of claim 1 in which the above-mentioned ion implantation dopant is selected from a group including arsenic 'phosphorus or a combination thereof for NM 0 S element' and selected from a group including boron, BF3 and a combination thereof for PMOS element . For example, the method of applying for patent. The method of item 1 is that the oxidation method of Shangbu is carried out at the wave extinction \ about S00 ° C to U50 degrees 3 The item of the French side is the description of the oxygen, and the item above is filled in & ": `` Printed by Bad Zhongci # quasi- bureau Η 工 consuming cooperatives No. „Go to Fan., Except for Profit. Liquid Dissolve” Please · ^ 6 Shen Phosphorus Φ—The item of the French method silicon d. Fc. The above description of the "·" * Xingli Special Method of the game 0L The description above is in the middle. Its 5 'paper is in accordance with Chinese standards (CNS,) A4 size (2! 0X297 mm: 1 4442 81 S 8 8 VB c D according to ruler). 1. The method according to item 1 of the scope of patent application, wherein the nitrogen ion concentration in the above-mentioned heterooxygen is about 1ei8 to 1 E2i at 0ms / cubic centimeter. For example, the method of the first scope of the application for patents, wherein the thickness of the above-mentioned amorphous silicon layer is about 400 to 1500A. For example, the method of applying for the first item of the patent scope further includes the following steps: forming the above-mentioned self-aligned metal lithium oxide (SALICiDE) and the above-mentioned polycrystalline 1¾1 metal: f. Forming a metal layer covering the above-mentioned semiconductor substrate, The above-mentioned barrier wall and the above-mentioned gate; a thermal process of the rail line makes the above-mentioned metal layer react with the above-mentioned vehicle conductor base material and the above-mentioned gate; and removes the unreacted part of the above-mentioned gold layer. (Please read the precautions on the back before filling this page)-^ --- N ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Lee T ^ 3 contains the special title, please request the application group to apply for the contract as if the temperature is in the layer t P Section C, Item: ^ The description of the gold, the L, C method and method d P ο To ο ο the method of heating. Progression i, lower degree 6- Wood paper size is applicable to national standard (CNS) A4 specifications (2; 0 × 297 mm) 4442 81 By (Please read the precautions on the back before filling in this page for binding --- Scripture Hongbei. China Maru Standards Bureau ίκτ_ 消 f Cooperative Press $ < This paper size is applicable to the Chinese National Standard (CN $) A4 (2l) 〇y mm)