TW426898B - Method for making stepped transistor with improved short channel effects - Google Patents

Abstract

A method for making a stepped transistor with improved short channel effects comprises providing a substrate having a surface formed thereon a step region; using an ion implanting method to form an anti-penetration region in the substrate below the step region; using an ion implanting method to form a lightly doped region in the substrate on the two sides of the anti-penetration region; forming a gate oxide layer on the top of the step region; forming a gate conductive layer on the gate oxide layer; forming an insulating layer on the gate conductive layer; using a photolithography and an etching process to define a gate region; forming a spacer on the etched sidewall of the gate conductive layer; and doping the lightly doped region to form a source/drain region.

Description

4 ^^ 8 9 8 V. Description of the invention (l) 5 -1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor transistor, and particularly to a method for manufacturing a stepped transistor, which can improve the short channel effect. 5-2 Background of the Invention: In the traditional process of general semiconductors, a metal-oxide-semiconductor (MOS) transistor is completed by the following main steps. A substrate 100 is provided. The top surface is a flat surface. As shown in the first figure, a gate oxide layer 101 is formed on the flat surface of the substrate 100, and the thickness is approximately 25 to 500 angstroms (angstroms); Next, a conductor layer 102 is formed on the gate oxide layer 101, which can be made of polysilicon or other suitable conductive materials; After the cap ox i de or silicon nitride 103 is on the conductive layer 102, the gate region is defined by lithography and engraving procedures, which covers the halide or nitride nitride 103. The thickness is about 500 to 5000 angstroms, and the width of the gate conductor layer 102 is about 2.0 micrometers. The next step is to implant the ions into the substrate 10 by ion implantation method (i0n implanta1; i〇r〇 or other traditional methods to form a lightly doped region (LDD), if the transistor is NMOS For the transistor, n-type ions are used. If it is a pM0s transistor, p-type ions are used. The following steps are used to form this closed electrode ^ 1_

Page 4 V. Description of the invention (2) Spacer 'First deposit an insulating material such as an oxide (〇x 丨 de) or silicon nitride (silicon nitride) on the covering oxide 103 and the substrate 10. 〇, and then etch back (etch back), then the spacer wall 105 is formed; finally, by any conventional method such as ion implantation doping ions into the lightly doped region 104 'then forming a source Source / drain region 1 0 6 'The ions here have the same electrical properties as the lightly doped region 104. At this point, a conventional transistor has been completed. The traditional transistor manufactured according to the above method is the main manufacturing step. It still has some other manufacturing processes, such as 3111 ^ -punchthrough region 107, and other manufacturing procedures are briefly described here. The channel length (channe 1 1 eng th) of the channel 108 is equivalent to the gate width (about 2.0 microns). However, in today's second micron manufacturing process, in order to increase the integration of integrated circuits and reduce the volume of semiconductor components, it has become a trend. 'When the gate width is reduced to 0-15 micron, this traditional transistor The channel length is also reduced to about 0.15 μm 'and the distance between the source and the drain becomes very close. Therefore, the impact of short channel effects significantly increases' the actual starting voltage (thresh). ld voltage, Vt) becomes smaller than the predicted value 'and when the gate voltage is less than the starting voltage, electrons are also prone to punchthrough, and leakage currents will also increase', making the integrated circuit stable Decreased sex and quality. According to the above factors, it is necessary to develop a method for manufacturing a semiconductor transistor.

4 ^ 689 q V. Description of the invention (3) ′ In order to solve the problem of short channel effect, the quality of the product can be improved. 5-3 Purpose and Summary of the Invention: In the above background of the invention, the shortcomings of conventional semiconductor transistors' are aimed at improving the disturbance caused by the short channel effect. The method according to the purpose described above. In the first embodiment, a stepped region is included; an isolation layer is formed, and then a first stone layer is formed by a grinding method to grind the first stone layer to a portion of the step located on the top surface of the step region to the step region. The top surface is exposed for the top surface of the polished stepped region and the second layer on the second stepped gate oxide layer on the top surface of the stepped region to form an insulation shadow and button process to define a gate layer. And the first stone layer to form a gap on both sides of the first stone layer; finally, a source / drain region is formed. The invention provides that a stepped transistor is first provided with a substrate, the surface of which is covered on the substrate and all surface insulation layers in the stepped region; then, the top surface of the chemical mechanical region is used, and the insulation layer is used as a termination layer and will After being polished away, a second stone layer is formed on the stone layer, a gate oxide layer is formed, and a gate conductive layer is formed on the gate conductive layer. Ions are pushed into the second lightly doped region; ions are doped into the lightly doped region at the gate conductive layer to

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4 ^ SQ9q _ V. Description of the invention (6) 43 Channel 10 0 Substrate 101 Gate oxide layer 10 2 Interrogation conductor layer 10 3 Cover oxide 10 4 Lightly doped region 105 Spacer wall 10 6 Source / drain region 107 Anti-penetration region 108 Channel 5-5 Detailed description of the invention: The present invention uses the generation of stepped metal oxide semiconductor (MOS transistor) to solve the short channel effect (sh〇r1; channel eff ec t, SCE) Question 'This transistor has a stepped semiconductor part, and the stepped region includes a top and side steps. This step can be one, two, or multiple layers. In the following two embodiments, two layers are used. Take the ladder as an example. From this two-layered stepped semiconductor part, a transistor that can improve the short channel effect has been developed. In the first embodiment, 'a substrate 10 is provided first, and a raised f-step region 11' is provided thereon as shown in the second figure. The formation of the stepped region 11 can be performed by using a sieve method such as a polysilicon or epitaxial silicon (polysi licon).

98_42 of 42 V. Description of the invention (7) epitaxial silicon) is deposited on the substrate 10; part of the surface of the substrate 10 can be etched down by conventional lithography and etching processes to form this step region 11. Refer to the third figure, 'Isolation layer 12 is formed on all surfaces of substrate 10 (including stepped area 1 1). This isolation layer 12 can be formed by deposition' and its thickness is less than 50 angstroms. And the material can be selected from pentoxide (Ta ^), silicon oxynitride (SiON) or oxide (ox i de). Then, a conventional method such as a deposition method is used to form a silicon layer 13 on the isolation layer 2. The material of the silicon layer 13 can be the same as the epitaxial silicon of the substrate 10. Crystal spar (po1ysi1 icon) ° Refer to the fourth figure, the silicon layer 13 is polished by chemical mechanical polishing (CMP) to the height of the top of the stepped region π. The isolation layer 12 is used as the termination layer of the CMP process (Stop layer) 'and will be abraded to expose the top surface of the stepped region 11, and then deposit a silicon layer 14 on the polished silicon layer 13 and the top surface of the stepped region 11, this silicon layer 1 The thickness of 4 is about 50 to 500 angstroms, and the material can be telecrystalline silicon or polycrystalline silicon. The fabrication of the gate of the transistor will be described below. It can be formed by a conventional standard process. In this embodiment, the following procedure is taken as an example, but it does not limit the scope of the present invention. See Figure 5 for thermal oxidation (t h e r m a 1

Page 10 4c! 6 ^ 9 8 Five 'Invention Description (8) oxidation) or other processes to form a gate oxide layer 15 on the silicon layer 14, and then deposit a polycrystalline silicon layer 16 on the interlayer oxide layer 15, Secondly, a metal silicide layer 17 is deposited on the polysilicon layer 16. The composite layer formed by the two conductors (polysilicon and metal silicide) is used as the gate conductive layer. The single-layer structure is used as the conductive layer of the gate (a metal silicide layer or a polycrystalline silicon layer); and a cap oxide is deposited on the metal silicide layer. 8 is used as the gate top insulation. In order to define the area of the gate, a photoresist layer 19 is formed on the cover oxide 18, and the photoresist layer 19 has been passed. Patterning (pa 11 erned) during exposure and development; next, an anisotropic silver etch process will cover oxide 18, metal silicide layer 17, polycrystalline silicon layer 16 and gate oxide layer丨 5 etching, after the above lithography and surname engraving process After 'may define the gate regions, the photoresist layer 19 is then removed, the resultant structure as shown in FIG sixth. Ion implantation is used to implant ions 20 into the silicon layer 13 and silicon layer 14 to form a lightly doped drain (LDD) 21 'of the semiconductor transistor. The implanted ions 20 can be selected from butterfly ions, arsenic ions or scale ions, and will be blocked by the insulating layer 12 so as not to enter the substrate 10. Referring to the seventh figure, an insulating layer 22 such as oxide, silicon nitride (SiN) or silicon oxynitride (CSiON) is deposited on all exposed surfaces, and then etched back

Page 11, 4, _ V. Description of the invention (9) " '----- It becomes the spacer of the gate, and the resulting structure is as shown in the eighth figure. Completed. The next step is to re-dop the ions 24 into the LDD region 21 by the ion implantation method to form the source μdrain region 25. The doped ions here and the ions in the [⑽ region 2 1 ions] the same. 1. Refer to the ninth figure. At this point, the transistor exemplified in this embodiment has been completed. When the shape of the pole 23 is "ON", the electric field will generate a channel 26 below it. And the source / drain region 25 is turned on. This channel is located in the silicon layer 14. Because there is no barrier layer 2 in it, the electrons in the source / drain region 25 can be driven by the electric field. On the other hand, the electrons will not penetrate through the area with the insulating layer 12 and cause leakage currents. That is, the penetration phenomenon of traditional transistors can be avoided. Short channel effect (short channel effect, SCE) was improved. Because the function of the isolation layer 12 can replace the traditional anti-punchthrough regions, some ion implantation steps are omitted. In the second embodiment of the present invention, a two-layer stepped semiconductor portion is also mainly used, and the formation method and location of the source / drain region are changed to form a transistor.

Page 12 4 If _ V. Description of the invention (see the tenth figure), a substrate 30 is provided with a stepped area 3 1 raised thereon. In this stepped region 31, a silicon material such as polysilicon or epitaxial silicon can be deposited on the substrate 30 by a deposition method; or a conventional lithography and etching process can be used to deposit a portion of the substrate 30. The surface is etched down to form the stepped region 3 丨. The above process is the same as the previous embodiment. Next, ions are doped into the substrate 30 under the stepped region 31 by ion implantation to form a reverse penetration region 32, and boron ions or arsenic ions or phosphorus ions are doped into the substrate by ion implantation. Within 30, a lightly doped region (LDD) 33 is formed, and the lightly doped region 33 is located on both sides of the anti-penetration region 32. By the anti-penetration region 32, the source / drain electron penetration of the transistor or the leakage of the current can be reduced. See Figure Η. A gate oxide layer 3 4 is formed on the top surface of the stepped region 3 1 by thermal oxidation or other conventional methods. A polycrystalline silicon layer 3 5 is deposited thereon, followed by a metal silicide. The physical layer 36 is on the polycrystalline silicon layer 35. The composite layer composed of the two conductors is used as the gate conductive layer, and the composite layer can also be replaced by a single layer structure (a metal silicide layer or a polycrystalline silicon layer). Structure; then a cap oxide (cap χχ de) 3 7 is deposited on the metal hairpin layer 36 for insulation purposes; silicon nitride can also be used to replace the cap oxide 37; and then a photoresist layer 38 is formed On the cover oxide 37. This photoresist layer 38 has been patterned 'for defining a gate region. After the above lithography process is completed, the covering oxide 37 and the conductive layer are etched, and then the photoresist 38 is removed. s

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V. Description of the invention (11) See Article XII. An insulating layer 39 is formed on all surfaces. The material of this insulating layer 39 can be oxide, silicon nitride or silicon oxynitride. In the structure of FIG. 12, the 3 g of the etched back insulating layer can insulate the side wall of the gate conductive layer as a spacer. At this point, the fabrication of the gate 40 has been completed, and the etch back process is completed. The unnecessary oxide layer 34 is also removed. Then, the ions 4 are doped into the lightly doped region (LDD) 33 on the substrate 30 by ion implantation or other conventional methods to form the source / drain region 42 of the transistor, which is the step of the second embodiment. The transistor is now complete. "ON" (ON electrode area 42, so its length is more troublesome, see Figure 14). When the transistor's gate status is)%, a channel 43 will be turned on / source and this channel will Extending along the side wall of the step and the bottom surface of the gate electrode, the traditional is long. It can solve the short channel effect of the traditional transistor. The application disclosed above is not limited to the above. The above description is only a preferred implementation of the present invention. For example, the scope of patent application of the present invention has been determined; all other equivalent changes or modifications that do not depart from the spirit of this invention should be included in the scope of patent.

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Claims (1)

1T4T9 8._ VI. Scope of patent application 1. A method for forming a stepped transistor, including at least: providing a substrate, the surface of which includes a stepped region; forming an insulation layer on the substrate and all surfaces of the stepped region Forming a first stone layer on the insulating layer; grinding the first silicon layer to the top surface of the stepped region by a chemical mechanical polishing method, and a portion of the insulating layer on the top surface of the stepped region is used as The termination layer will be abraded until the top surface of the stepped area is exposed; a second silicon layer is formed on the top surface of the stepped area after polishing and the first stone layer; a gate oxide layer is formed on On the step, the formation of the inter-electrode conductive layer in the range of the free =-2 pole; Ran "" and an etching process to define a gate doping ions into the lightly doped region in the second stone layer; at the gate The two sides of the electrode conductive layer are doped with ions into the lightly doped region and the first silicon layer to form a gap wall; and to form a source / drain region. Among them, the above-mentioned substrates include at least 2. If the scope of the first patent application includes one of the following: epitaxial silicon, polycrystalline silicon ^ 3. If the scope of the first patent application has a step shape of at least one layer. The first step area Page 15 of 42 of 98_ VI. Patent application scope 4 · The method of item 1 of the patent application scope, wherein the thickness of the above-mentioned insulation layer is less than 50 Angstroms. 5. The method according to item 1 of the patent application, wherein the above-mentioned insulation layer includes at least one of the following: silicon oxynitride, aluminum pentoxide. 6. The method according to item 1 of the patent application range, wherein the above-mentioned insulation layer contains at least an oxide. 7. The method according to item 1 of the scope of patent application, wherein the first silicon layer mentioned above includes at least one of the following: worm crystal and polycrystalline stone. 8. The method according to item 1 of the scope of patent application, wherein the second silicon layer mentioned above includes at least one of the following: telomerite and polycrystalline. The use of layers and light electric dreams until the crystal is ground into a very many edge-shaped gates, a unique layer, the description of the description of the transformation of the upper and upper ^ 6- Miaozhong, among them, gold, 0, law ,. The method is broken, the method is layered, the formula is layered, the formula is rigid, and the nitrogen is complex. < VI. Patent application scope: Boron :: The source of the ion contains at least 12 of the τ column, as in the method of patent application item 1, wherein the above mentioned nudge region and the source / drain region are based on Formed by ion implantation. 13. The method of item No. 17 in the patent scope, wherein the above-mentioned partition wall includes at least one of the following: silicon oxynitride, silicon nitride. Claimed in: Patent. &Amp; Method of item 1, wherein the above-mentioned partition wall contains at least an oxide. 1 5. — A method of forming a stepped transistor, including a stepped area from its surface ... anti-penetration]; formed in the substrate below the stepped area-using ion implantation in the and Pass-through rust-lightly doped region; a gate oxide layer is formed in the substrate on both sides of the coin tooth & domain to form a stepped electrode conductive layer on the gate oxide layer, and then two pages are formed. 'Formation-gate electrical layer, followed by lithography and etching procedures = open-lead conduction, etched side walls of the free-electrode conductive layer, doping ions into the lightly doped region to form a barrier wall' and u-source / Drain region. Page 17 42 ⑼ 98 6. Scope of Patent Application 16. For the method of claim 15 in the scope of patent application, the above substrates include at least one of the following: epitaxial silicon and polycrystalline silicon. 17. The method according to item 15 of the scope of patent application, wherein the above-mentioned stepped region includes at least one step of a top surface and a side edge. 18. The method according to item 15 of the scope of patent application, wherein the above-mentioned gate conductive layer includes at least one of the following: a polycrystalline stone layer, a metal hairpin layer, a composite composed of a polycrystal stone and a metal oxide Floor. 19. The method according to item 15 of the scope of patent application, wherein the above-mentioned insulating layer contains at least one of the following _ oxides and nitrides. I 20. The method according to item 15 of the scope of patent application, wherein the above-mentioned partition wall contains at least one of the following: oxynitride and nitrided oxide. 21. The method according to item 15 of the patent application range, wherein the above-mentioned barrier wall contains at least an oxide. 22. A stepped transistor structure comprising at least: a substrate including at least a stepped surface, the stepped surface being at least one step with a top surface and sides; an oxide layer formed on the substrate The top surface of the stepped surface Page 18 G ~ _ VI. Patent application scope A conductive layer is formed on the oxide layer; an insulating layer is formed on the conductive layer to isolate the conductive layer from above; a gap wall is formed on the conductive layer The side walls of the layer are used to isolate the sides of the conductive layer; and a source / drain region is formed on both sides of the stepped surface. 23. For the structure of the scope of application for patent No. 22, the above-mentioned substrate includes at least one of the following: stupid and polycrystalline. 24. For the structure of the scope of application for patent No. 22, wherein the above-mentioned conductive layer includes at least one of the following: a polycrystalline stone layer, a metallic stone material layer, a composite layer composed of a polycrystalline stone material and a golden stone material . 25. For the structure of the scope of application for patent No. 22, the above-mentioned insulating layer contains at least one of the following: oxide, nitride stone. 26. If the structure of the scope of patent application No. 22, wherein the above-mentioned partition wall contains at least an oxide. 27. For the structure of the scope of application for item 22, the above-mentioned spacers include at least one of the following: silicon oxynitride, silicon nitride. 28. The structure according to item 22 of the patent application scope, wherein the source / drain described above Page 19 ~ Q_ VI. Patent application area The area is formed in the substrate on both sides of the stepped surface. 29. The structure of claim 22, wherein the source / drain region is formed above the substrate on both sides of the stepped surface. Page 20