TWI679768B - Stepped device and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 230000007423 decrease Effects 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 89
- 239000000463 material Substances 0.000 claims description 47
- 238000002955 isolation Methods 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 25
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 239000002019 doping agent Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 6
- -1 boron ions Chemical class 0.000 claims description 6
- 229910021529 ammonia Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims 1
- 238000003682 fluorination reaction Methods 0.000 claims 1
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 8
- 229910015900 BF3 Inorganic materials 0.000 description 4
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- DLNOIRAFPPLAPE-UHFFFAOYSA-L tetramethylazanium dihydroxide Chemical compound [OH-].[OH-].C[N+](C)(C)C.C[N+](C)(C)C DLNOIRAFPPLAPE-UHFFFAOYSA-L 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
一種階梯式元件，包括基底。位在主動區中的基底具有階梯式結構。階梯式結構的高度在通道寬度方向上從主動區的一端至另一端逐步降低。A stepped element includes a substrate. The substrate located in the active area has a stepped structure. The height of the stepped structure gradually decreases from one end of the active area to the other end in the channel width direction.
Description
本發明是有關於一種元件及其製造方法，且特別是有關於一種階梯式元件及其製造方法。The present invention relates to a component and a method for manufacturing the same, and more particularly, to a stepped component and a method for manufacturing the same.
目前隨著半導體製造技術不斷發展，在元件尺寸設計方面，製程線寬逐年微縮。然而，尺寸微縮也衍生出各種問題。就通道寬度而言，尺寸微縮會造成通道寬度變窄，而使得元件的飽和汲極電流變小，進而造成元件性能降低。With the continuous development of semiconductor manufacturing technology, the process line width has been shrinking year by year in terms of component size design. However, downsizing also raises various issues. In terms of channel width, shrinking the size will cause the channel width to become narrower, and the saturation drain current of the device will be smaller, which will cause the performance of the device to decrease.
本發明提供一種階梯式元件及其製造方法，其可有效地增加通道寬度，進而提升元件性能。The invention provides a stepped component and a manufacturing method thereof, which can effectively increase the channel width and further improve the performance of the component.
本發明提出一種階梯式元件，包括基底。位在主動區中的基底具有階梯式結構。階梯式結構的高度在通道寬度方向上從主動區的一端至另一端逐步降低。The invention provides a stepped element, which includes a substrate. The substrate located in the active area has a stepped structure. The height of the stepped structure gradually decreases from one end of the active area to the other end in the channel width direction.
依照本發明的一實施例所述，在上述階梯式元件中，階梯式結構可為兩階式結構。階梯式結構可包括彼此相連的第一階與第二階。According to an embodiment of the present invention, in the stepped device, the stepped structure may be a two-stepped structure. The stepped structure may include first and second steps connected to each other.
依照本發明的一實施例所述，在上述階梯式元件中，更可包括閘極與介電層。閘極位在基底上。介電層位在閘極與基底之間。According to an embodiment of the present invention, the stepped device may further include a gate electrode and a dielectric layer. The gate is located on the substrate. The dielectric layer is between the gate and the substrate.
本發明提出一種階梯式元件的製造方法，包括以下步驟。提供基底。在基底中形成凹陷，而使得位在主動區中的基底具有階梯式結構。階梯式結構的高度在通道寬度方向上從主動區的一端至另一端逐步降低。The invention provides a method for manufacturing a stepped element, which includes the following steps. Provide a substrate. A depression is formed in the substrate, so that the substrate located in the active region has a stepped structure. The height of the stepped structure gradually decreases from one end of the active area to the other end in the channel width direction.
依照本發明的一實施例所述，在上述階梯式元件的製造方法中，凹陷的形成方法可包括以下步驟。在基底上形成墊層。在墊層兩側的基底中形成隔離結構。隔離結構可突出於基底且可高於墊層。在墊層與隔離結構上形成罩幕材料層。利用傾斜角離子植入法對部分罩幕材料層進行摻雜製程，而使得罩幕材料層具有摻雜部與未摻雜部。摻雜部與未摻雜部在蝕刻製程中的蝕刻速率不同。對罩幕材料層進行蝕刻製程，以移除摻雜部與未摻雜部中的一者，而形成暴露出部分墊層的罩幕層。移除由罩幕層所暴露出的部分墊層，而暴露出部分基底。移除由墊層所暴露出的部分基底，而在基底中形成凹陷。According to an embodiment of the present invention, in the method for manufacturing a stepped device, the method for forming a recess may include the following steps. A cushion layer is formed on the substrate. An isolation structure is formed in the substrate on both sides of the cushion layer. The isolation structure may protrude from the substrate and may be higher than the cushion layer. A mask material layer is formed on the cushion layer and the isolation structure. A doping process is performed on a part of the mask material layer by using a tilt angle ion implantation method, so that the mask material layer has a doped portion and an undoped portion. The etching rate of the doped portion and the undoped portion in the etching process is different. An etching process is performed on the mask material layer to remove one of the doped portion and the undoped portion to form a mask layer that exposes a part of the cushion layer. A portion of the cushion layer exposed by the cover layer is removed, and a portion of the substrate is exposed. A portion of the substrate exposed by the cushion layer is removed, and a depression is formed in the substrate.
依照本發明的一實施例所述，在上述階梯式元件的製造方法中，部分基底的移除方法例如是乾式蝕刻法。According to an embodiment of the present invention, in the method for manufacturing the stepped device, a method for removing a part of the substrate is, for example, a dry etching method.
依照本發明的一實施例所述，在上述階梯式元件的製造方法中，在移除部分基底的步驟中，可同時移除罩幕層。According to an embodiment of the present invention, in the stepped component manufacturing method described above, in the step of removing a part of the substrate, the cover layer can be removed at the same time.
依照本發明的一實施例所述，在上述階梯式元件的製造方法中，其中罩幕材料層的材料例如是非晶矽或多晶矽，且摻雜製程所使用的摻質例如是硼(B)離子或氟化硼(BF 2)離子。 According to an embodiment of the present invention, in the method for manufacturing the stepped device, a material of the mask material layer is, for example, amorphous silicon or polycrystalline silicon, and a dopant used in the doping process is, for example, boron (B) ion Or boron fluoride (BF 2 ) ion.
依照本發明的一實施例所述，在上述階梯式元件的製造方法中，蝕刻製程例如是濕式蝕刻製程，且濕式蝕刻製程所使用的蝕刻劑例如是稀釋的氨水(ammonia)或四甲基氫氧化銨(tetramethylammonium hydroxide，TMAH)。According to an embodiment of the present invention, in the method for manufacturing a stepped device, the etching process is, for example, a wet etching process, and the etchant used in the wet etching process is, for example, diluted ammonia or tetramethylammonium Tetramethylammonium hydroxide (TMAH).
依照本發明的一實施例所述，在上述階梯式元件的製造方法中，更可包括以下步驟。在基底上形成介電層。在介電層上形成閘極。According to an embodiment of the present invention, in the method for manufacturing a stepped device, the method may further include the following steps. A dielectric layer is formed on the substrate. A gate is formed on the dielectric layer.
基於上述，在本發明所提出的階梯式元件及其製造方法中，位在主動區中的基底具有階梯式結構，且階梯式結構的高度在通道寬度方向上從主動區的一端至另一端逐步降低。因此，可在不影響元件關鍵尺寸的前提下，增加通道寬度。此外，藉由通道寬度的增加，可提高飽和汲極電流，而使得設計的電路速度變快，進而提升元件性能。Based on the above, in the stepped component and the manufacturing method thereof proposed by the present invention, the substrate in the active area has a stepped structure, and the height of the stepped structure gradually increases from one end of the active area to the other end in the channel width direction. reduce. Therefore, the channel width can be increased without affecting the critical dimensions of the component. In addition, by increasing the channel width, the saturation drain current can be increased, which makes the designed circuit faster, thereby improving the performance of the device.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.
圖1A至圖1H為本發明一實施例的階梯式元件的製造流程剖面圖。圖2為圖1G的立體圖。圖3為圖1H的上視圖。1A to 1H are cross-sectional views of a manufacturing process of a stepped device according to an embodiment of the present invention. FIG. 2 is a perspective view of FIG. 1G. FIG. 3 is a top view of FIG. 1H.
請參照圖1A，提供基底100。基底100可為半導體基底，如矽基底。接著，可在基底100上形成墊材料層102。墊材料層102的材料例如是氧化矽。墊材料層102的形成方法例如是熱氧化法。然後，可在墊材料層102上形成墊材料層104。墊材料層104的材料例如是氮化矽。墊材料層104的形成方法例如是化學氣相沉積法。Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Next, a pad material layer 102 may be formed on the substrate 100. The material of the pad material layer 102 is, for example, silicon oxide. A method for forming the pad material layer 102 is, for example, a thermal oxidation method. Then, a pad material layer 104 may be formed on the pad material layer 102. The material of the pad material layer 104 is, for example, silicon nitride. A method for forming the pad material layer 104 is, for example, a chemical vapor deposition method.
請參照圖1B，可對墊材料層104與墊材料層102進行圖案化製程，而在基底100上形成墊層104a與墊層102a。舉例來說，上述圖案化製程可藉由微影製程與蝕刻製程對墊材料層104與墊材料層102進行圖案化。Referring to FIG. 1B, a patterning process may be performed on the pad material layer 104 and the pad material layer 102 to form a pad layer 104 a and a pad layer 102 a on the substrate 100. For example, the patterning process described above can pattern the pad material layer 104 and the pad material layer 102 by a lithography process and an etching process.
接下來，可在墊層102a兩側的基底100中形成隔離結構106。隔離結構106可突出於基底100且可高於墊層102a。隔離結構106的材料例如是氧化矽。隔離結構106例如是藉由淺溝渠隔離結構製程所形成的淺溝渠隔離結構。此外，更可根據需求對隔離結構106進行調平製程(leveling process)，以調整隔離結構106的高度。隔離結構106可在基底100中定義出主動區AA，且主動區AA可位在相鄰的隔離結構106之間。Next, an isolation structure 106 may be formed in the substrate 100 on both sides of the cushion layer 102a. The isolation structure 106 may protrude from the substrate 100 and may be higher than the cushion layer 102a. The material of the isolation structure 106 is, for example, silicon oxide. The isolation structure 106 is, for example, a shallow trench isolation structure formed by a shallow trench isolation structure process. In addition, a leveling process may be performed on the isolation structure 106 according to requirements to adjust the height of the isolation structure 106. The isolation structure 106 may define an active area AA in the substrate 100, and the active area AA may be located between adjacent isolation structures 106.
請參照圖1C，移除墊層104a。墊層104a的移除方法例如是濕式蝕刻法。Referring to FIG. 1C, the cushion layer 104a is removed. The method for removing the underlayer 104a is, for example, a wet etching method.
隨後，可在墊層102a與隔離結構106上形成罩幕材料層108。在本實施例中，罩幕材料層108可共形地形成在墊層102a與隔離結構106上，但本發明並不以此為限。此外，由於隔離結構106可突出於基底100且可高於墊層102a，因此可使得罩幕材料層108在相鄰的隔離結構106之間具有凹面CS。罩幕材料層108的材料可為矽材料，例如是非晶矽或多晶矽。罩幕材料層108的形成方法例如是化學氣相沉積法。Subsequently, a mask material layer 108 may be formed on the cushion layer 102 a and the isolation structure 106. In this embodiment, the mask material layer 108 can be conformally formed on the cushion layer 102a and the isolation structure 106, but the invention is not limited thereto. In addition, since the isolation structure 106 can protrude from the substrate 100 and can be higher than the cushion layer 102 a, the mask material layer 108 can have a concave surface CS between adjacent isolation structures 106. The material of the mask material layer 108 may be a silicon material, such as amorphous silicon or polycrystalline silicon. A method of forming the mask material layer 108 is, for example, a chemical vapor deposition method.
請參照圖1D，利用傾斜角離子植入法對部分罩幕材料層108進行摻雜製程200，而使得罩幕材料層108具有摻雜部P1與未摻雜部P2。詳細來說，在利用傾斜角離子植入法進行摻雜製程200時，由於隔離結構106突出於基底100的部分可對離子束產生遮蔽效應，因此可只對部分罩幕材料層108進行摻雜，而形成摻雜部P1與未摻雜部P2。此外，可藉由傾斜角離子植入法的植入角度來調整離子植入的範圍，因此可根據產品需求來調整摻雜部P1與未摻雜部P2的範圍。摻雜製程所使用的摻質例如是硼離子或氟化硼離子，但本發明並不以此為限。Referring to FIG. 1D, a doping process 200 is performed on a part of the mask material layer 108 by using an inclined angle ion implantation method, so that the mask material layer 108 has a doped portion P1 and an undoped portion P2. In detail, when the doping process 200 is performed using the tilt angle ion implantation method, since the part of the isolation structure 106 protruding from the substrate 100 can have a shielding effect on the ion beam, only a part of the mask material layer 108 can be doped To form a doped portion P1 and an undoped portion P2. In addition, the range of ion implantation can be adjusted by the implantation angle of the tilt angle ion implantation method, so the range of the doped portion P1 and the undoped portion P2 can be adjusted according to the product requirements. The dopant used in the doping process is, for example, boron ion or boron fluoride ion, but the invention is not limited thereto.
另外，摻質可改變摻雜部P1中的罩幕材料層108的蝕刻特性，而使得摻雜部P1與未摻雜部P2在蝕刻製程中的蝕刻速率不同。在一實施例中，摻質會使得蝕刻製程對摻雜部P1的蝕刻速率慢於對未摻雜部P2的蝕刻速率。在另一實施例中，摻質會使得蝕刻製程對摻雜部P1的蝕刻速率快於對未摻雜部P2的蝕刻速率。In addition, the dopant can change the etching characteristics of the mask material layer 108 in the doped portion P1, so that the etching rate of the doped portion P1 and the undoped portion P2 in the etching process is different. In one embodiment, the dopant causes the etching rate of the doped portion P1 to be slower than that of the undoped portion P2 in the etching process. In another embodiment, the dopant causes the etching process to etch the doped portion P1 faster than the undoped portion P2.
請參照圖1E，對罩幕材料層108進行蝕刻製程，以移除摻雜部P1與未摻雜部P2中的一者，而形成暴露出部分墊層102a的罩幕層108a。蝕刻製程例如是濕式蝕刻製程，且濕式蝕刻製程所使用的蝕刻劑例如是稀釋的氨水或四甲基氫氧化銨。Referring to FIG. 1E, an etching process is performed on the mask material layer 108 to remove one of the doped portion P1 and the undoped portion P2 to form a mask layer 108 a exposing a part of the pad layer 102 a. The etching process is, for example, a wet etching process, and the etchant used in the wet etching process is, for example, diluted ammonia or tetramethylammonium hydroxide.
在本實施例中，蝕刻製程對未摻雜部P2的移除速率可高於對摻雜部P1的移除速率，因此可移除未摻雜部P2，而由留下的摻雜部P1形成罩幕層108a，但本發明並不以此為限。在其他實施例中，蝕刻製程對摻雜部P1的移除速率可高於對未摻雜部P2的移除速率，因此可移除摻雜部P1，而由留下的未摻雜部P2形成罩幕層108a。In this embodiment, the removal rate of the undoped portion P2 by the etching process may be higher than the removal rate of the doped portion P1. Therefore, the undoped portion P2 may be removed, and the remaining doped portion P1 may be removed. The cover layer 108a is formed, but the invention is not limited thereto. In other embodiments, the removal rate of the doped portion P1 by the etching process may be higher than the removal rate of the undoped portion P2. Therefore, the doped portion P1 may be removed, and the remaining undoped portion P2 may be removed. A cover curtain layer 108a is formed.
此外，可藉由罩幕材料層108的材料、摻質種類及/或蝕刻劑種類的選擇，來決定蝕刻製程所要移除的對象。舉例來說，在罩幕材料層108的材料為非晶矽或多晶矽的情況下，可利用傾斜角離子植入法且以硼離子或氟化硼離子作為摻質，對部分罩幕材料層108進行摻雜製程，而使得摻雜部P1與未摻雜部P2在蝕刻製程中的蝕刻速率不同。此外，由於稀釋的氨水或四甲基氫氧化銨對摻雜硼離子或氟化硼離子的摻雜部P1的蝕刻速率較慢，且對未摻雜部P2的蝕刻速率較快，因此可使用稀釋的氨水或四甲基氫氧化銨對罩幕材料層108進行濕式蝕刻製程，以移除未摻雜部P2，而留下摻雜部P1。In addition, the selection of the material of the mask material layer 108, the type of dopant, and / or the type of etchant can determine the object to be removed in the etching process. For example, when the material of the mask material layer 108 is amorphous silicon or polycrystalline silicon, a tilt angle ion implantation method and boron ion or boron fluoride ion can be used as a dopant to partially mask material layer 108. A doping process is performed, so that the etching rates of the doped portion P1 and the undoped portion P2 in the etching process are different. In addition, since the etching rate of the doped portion P1 doped with boron ion or boron fluoride ion by the diluted ammonia or tetramethylammonium hydroxide is slow, and the etching rate of the undoped portion P2 is fast, it can be used The diluted ammonia or tetramethylammonium hydroxide is used to perform a wet etching process on the mask material layer 108 to remove the undoped portion P2 and leave the doped portion P1.
請參照圖1F，可移除由罩幕層108a所暴露出的部分墊層102a，而暴露出部分基底100。部分墊層102a的移除方法例如是濕式蝕刻法。Referring to FIG. 1F, a part of the cushion layer 102 a exposed by the cover layer 108 a may be removed, and a part of the substrate 100 may be exposed. A method of removing a part of the underlayer 102a is, for example, a wet etching method.
請參照圖1G與圖2，可移除由墊層102a所暴露出的部分基底100，而在基底100中形成凹陷110。部分基底100的移除方法例如是乾式蝕刻法。此外，在移除部分基底100的步驟中，可同時移除罩幕層108a。1G and FIG. 2, a part of the substrate 100 exposed by the cushion layer 102 a may be removed, and a recess 110 may be formed in the substrate 100. A method for removing part of the substrate 100 is, for example, a dry etching method. In addition, in the step of removing part of the substrate 100, the mask layer 108a may be removed at the same time.
藉此，可使得位在主動區AA中的基底100具有階梯式結構SS。階梯式結構SS的高度在通道寬度方向DW上從主動區AA的一端至另一端逐步降低。如此一來，可使得位在主動區AA中的通道112在通道寬度方向DW上呈現階梯狀，因此可有效地增加通道112的通道寬度W。通道寬度方向DW可相交於通道長度方向DL。在本實施例中，以通道寬度方向DW垂直於通道長度方向DL為例來進行說明，但本發明並不以此為限。一般而言，「通道長度方向DL」可定義為延伸通過源極區、通道區與汲極區的方向。此外，隔離結構106與主動區AA可在通道寬度方向DW上排列。Thereby, the substrate 100 located in the active area AA can have a stepped structure SS. The height of the stepped structure SS gradually decreases from one end to the other end of the active area AA in the channel width direction DW. In this way, the channel 112 located in the active area AA can be stepped in the channel width direction DW, so the channel width W of the channel 112 can be effectively increased. The channel width direction DW may intersect with the channel length direction DL. In this embodiment, the channel width direction DW is perpendicular to the channel length direction DL as an example for description, but the present invention is not limited thereto. In general, the “channel length direction DL” can be defined as a direction extending through the source region, the channel region, and the drain region. In addition, the isolation structure 106 and the active area AA may be arranged in the channel width direction DW.
舉例來說，階梯式結構SS可為兩階式結構。在此情況下，階梯式結構SS可包括彼此相連的第一階S1與第二階S2，且第一階S1的頂面可高於第二階S2的頂面。For example, the stepped structure SS may be a two-stage structure. In this case, the stepped structure SS may include a first order S1 and a second order S2 connected to each other, and a top surface of the first order S1 may be higher than a top surface of the second order S2.
然後，移除墊層102a。墊層102a的移除方法例如是濕式蝕刻法。此外，在移除墊層102a的步驟中，可同時移除部分隔離結構106，以調整隔離結構的高度。Then, the cushion layer 102a is removed. The method for removing the pad layer 102a is, for example, a wet etching method. In addition, in the step of removing the cushion layer 102a, a part of the isolation structure 106 may be removed at the same time to adjust the height of the isolation structure.
請參照圖1H與圖3，可在基底100上形成介電層114。介電層114可作為閘介電層。介電層114的材料例如是氧化矽。介電層114的形成方法例如是熱氧化法。Referring to FIGS. 1H and 3, a dielectric layer 114 may be formed on the substrate 100. The dielectric layer 114 may serve as a gate dielectric layer. The material of the dielectric layer 114 is, for example, silicon oxide. A method of forming the dielectric layer 114 is, for example, a thermal oxidation method.
接著，可在介電層114上形成閘極116。閘極116的材料例如是摻雜多晶矽。閘極116的形成方法例如是組合使用沉積製程、微影製程與蝕刻製程。閘極116可在通道寬度方向DW上延伸且經過通道112與隔離結構106的上方。Next, a gate electrode 116 may be formed on the dielectric layer 114. The material of the gate electrode 116 is, for example, doped polycrystalline silicon. The method for forming the gate electrode 116 is, for example, a combination of a deposition process, a lithography process, and an etching process. The gate electrode 116 may extend in the channel width direction DW and pass over the channel 112 and the isolation structure 106.
在本實施例中，階梯式元件10是以階梯式電晶體為例，且用以完成電晶體的其他製程步驟(如，形成源極與汲極的製程)為所屬技術領域具有通常知識者所周知，故於此省略其說明。In this embodiment, the stepped element 10 is a stepped transistor as an example, and other process steps for completing the transistor (such as a process of forming a source and a drain) are used by those having ordinary knowledge in the technical field to which the transistor belongs. It is well known, so its description is omitted here.
以下，藉由圖1H來說明本實施例的階梯式元件10。此外，雖然階梯式元件10的形成方法是以上述方法為例進行說明，但本發明並不以此為限。Hereinafter, the stepped element 10 of this embodiment will be described with reference to FIG. 1H. In addition, although the method for forming the stepped element 10 is described by taking the above method as an example, the present invention is not limited thereto.
請參照圖1H，階梯式元件10包括基底100，且更可包括閘極116與介電層114。位在主動區AA中的基底100具有階梯式結構SS。階梯式結構SS的高度在通道寬度方向DW上從主動區AA的一端至另一端逐步降低。閘極116位在基底100上。介電層114位在閘極與基底100之間。此外，階梯式元件10中的各構件的詳細內容已於上述實施例進行說明，於此不再說明。Referring to FIG. 1H, the stepped device 10 includes a substrate 100, and further includes a gate electrode 116 and a dielectric layer 114. The substrate 100 located in the active area AA has a stepped structure SS. The height of the stepped structure SS gradually decreases from one end to the other end of the active area AA in the channel width direction DW. The gate electrode 116 is located on the substrate 100. The dielectric layer 114 is located between the gate and the substrate 100. In addition, the detailed content of each component in the stepped element 10 has been described in the above embodiment, and will not be described here.
基於上述實施例可知，在上述實施例的階梯式元件10及其製造方法中，位在主動區AA中的基底100具有階梯式結構SS，且階梯式結構SS的高度在通道寬度方向DW上從主動區AA的一端至另一端逐步降低。因此，可在不影響元件關鍵尺寸的前提下，增加通道寬度。此外，藉由通道寬度的增加，可提高飽和汲極電流，而使得設計的電路速度變快，進而提升元件性能。Based on the above embodiments, it can be known that in the stepped element 10 and the manufacturing method thereof in the above embodiment, the substrate 100 located in the active area AA has a stepped structure SS, and the height of the stepped structure SS is from the channel width direction DW The active area AA gradually decreases from one end to the other end. Therefore, the channel width can be increased without affecting the critical dimensions of the component. In addition, by increasing the channel width, the saturation drain current can be increased, which makes the designed circuit faster, thereby improving the performance of the device.
在上述實施例中，階梯式元件10雖然是以階梯式電晶體為例，但本發明並不以此為限。在一些實施例中，階梯式元件可以只包括圖1G中的具有階梯式結構SS的基底100，且可用以作為具有階梯式結構SS的主動區AA。此外，上述具有階梯式結構SS的主動區AA可應用於各種不同半導體元件中。在一些實施例中，階梯式元件除了可包括圖1G中的具有階梯式結構SS的基底100之外，更可依據需求包括其他構件，而形成各種階梯式半導體元件。In the above embodiment, although the stepped element 10 is a stepped transistor as an example, the present invention is not limited thereto. In some embodiments, the stepped element may include only the substrate 100 with the stepped structure SS in FIG. 1G, and may be used as the active region AA with the stepped structure SS. In addition, the active area AA with the stepped structure SS can be applied to various semiconductor devices. In some embodiments, in addition to the stepped device may include the substrate 100 with the stepped structure SS in FIG. 1G, it may further include other components according to requirements to form various stepped semiconductor devices.
綜上所述，在上述實施例的階梯式元件及其製造方法中，可藉由具有階梯式結構的主動區來增加通道寬度，因此可提高飽和汲極電流，而使得設計的電路速度變快，進而提升元件性能。In summary, in the stepped component and the manufacturing method thereof of the above embodiments, the channel width can be increased by the active area having a stepped structure, so the saturated drain current can be increased, and the designed circuit speed can be made faster. , Which in turn improves component performance.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
10‧‧‧階梯式元件
100‧‧‧基底
102、104‧‧‧墊材料層
102a、104a‧‧‧墊層
106‧‧‧隔離結構
108‧‧‧罩幕材料層
108a‧‧‧罩幕層
110‧‧‧凹陷
112‧‧‧通道
114‧‧‧介電層
116‧‧‧閘極
200‧‧‧摻雜製程
AA‧‧‧主動區
CS‧‧‧凹面
DL‧‧‧通道長度方向
DW‧‧‧通道寬度方向
SS‧‧‧階梯式結構
S1‧‧‧第一階
S2‧‧‧第二階
W‧‧‧通道寬度
10‧‧‧ Ladder element
100‧‧‧ substrate
102, 104‧‧‧ cushion material layer
102a, 104a‧‧‧ cushion
106‧‧‧Isolation structure
108‧‧‧Mask material layer
108a‧‧‧ curtain layer
110‧‧‧ Sag
112‧‧‧channel
114‧‧‧ Dielectric layer
116‧‧‧Gate
200‧‧‧ doping process
AA‧‧‧Active Zone
CS‧‧‧ Concave
DL‧‧‧Channel length direction
DW‧‧‧Channel width direction
SS‧‧‧Stepped structure
S1‧‧‧first stage
S2‧‧‧Second Stage
W‧‧‧channel width
圖1A至圖1H為本發明一實施例的階梯式元件的製造流程剖面圖。
圖2為圖1G的立體圖。
圖3為圖1H的上視圖。
1A to 1H are cross-sectional views of a manufacturing process of a stepped device according to an embodiment of the present invention.
FIG. 2 is a perspective view of FIG. 1G.
FIG. 3 is a top view of FIG. 1H.
Claims (10)
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| TW426898B (en) * | 1999-10-11 | 2001-03-21 | United Microelectronics Corp | Method for making stepped transistor with improved short channel effects |
| WO2012055142A1 (en) * | 2010-10-29 | 2012-05-03 | 中国科学院微电子研究所 | Transistor and manufacturing method thereof |
| TW201423987A (en) * | 2012-12-07 | 2014-06-16 | Richtek Technology Corp | High electron mobility transistor and manufacturing method thereof |
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| TW426898B (en) * | 1999-10-11 | 2001-03-21 | United Microelectronics Corp | Method for making stepped transistor with improved short channel effects |
| WO2012055142A1 (en) * | 2010-10-29 | 2012-05-03 | 中国科学院微电子研究所 | Transistor and manufacturing method thereof |
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