KR0168119B1 - Method of manufacturing semiconductor devices - Google Patents
Method of manufacturing semiconductor devices Download PDFInfo
- Publication number
- KR0168119B1 KR0168119B1 KR1019940039472A KR19940039472A KR0168119B1 KR 0168119 B1 KR0168119 B1 KR 0168119B1 KR 1019940039472 A KR1019940039472 A KR 1019940039472A KR 19940039472 A KR19940039472 A KR 19940039472A KR 0168119 B1 KR0168119 B1 KR 0168119B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- gate electrode
- semiconductor device
- region
- epitaxial layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 238000002513 implantation Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로, 실리콘 에피텍셜층을 이용하여 반도체 소자를 제조하므로써, 반도체 소자의 전기적 특성을 향상시킬 뿐만 아니라 칩 사이즈를 감소시킬 수 있는 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device by using a silicon epitaxial layer to improve the electrical characteristics of the semiconductor device and to reduce the chip size.
Description
제1도 종래의 반도체 소자 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a conventional semiconductor device manufacturing method.
제2도는 제1도를 설명하기 위한 레이아웃도.FIG. 2 is a layout diagram for describing FIG. 1.
제3a도 내지 제3d 도는 본 발명에 따른 반도체 소자 제조방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.3A to 3D are cross-sectional views of devices sequentially shown to illustrate a method of manufacturing a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film
3 및 11 : 게이트 산화막 4 및 12 : 게이트 전극3 and 11: gate oxide film 4 and 12: gate electrode
5 : 저농도 불순물 영역 6 : 산화막 스페이서5: low concentration impurity region 6: oxide film spacer
7 : 고농도 불순물 영역 8 : 희생 산화막7: high concentration impurity region 8: sacrificial oxide film
10 : 에피텍셜층 40 : Arc층10: epitaxial layer 40: arc layer
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 실리콘 에피텍셜층을 이용하여 반도체 소자를 제조하므로써, 반도체 소자의 전기적 특성을 향상시킬 뿐만 아니라 칩 사이즈를 감소시킬 수 있는 반도체 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a silicon epitaxial layer, which can improve the electrical characteristics of the semiconductor device and reduce the chip size.
종래의 반도체 소자 제조방법을 제1도 및 제2도를 참조하여 설명하기로 한다.A conventional semiconductor device manufacturing method will be described with reference to FIGS. 1 and 2.
실리콘 기판(1)상에 소자 분리를 위한 필드 산화막(2)이 형성된다. 실리콘 기판(1) 상부의 선택된 영역에 게이트 산화막(3), 게이트 전극(4) 및 Arc층(40)이 순차적으로 형성되어 게이트 전극 구조가 형성된다. 필드 산화막(2)과 게이트 전극구조 사이의 실리콘 기판(1)에 저농도 불순물 영역(5)이 형성된 후 게이트 전극 구조 측벽에 산화막 스페이서(6)가 형성된다. 그후 실리콘 기판(1)에 고농도 불순물 영역(7)이 형성된다.A field oxide film 2 for device isolation is formed on the silicon substrate 1. The gate oxide film 3, the gate electrode 4, and the arc layer 40 are sequentially formed in a selected region on the silicon substrate 1 to form a gate electrode structure. After the low concentration impurity region 5 is formed in the silicon substrate 1 between the field oxide film 2 and the gate electrode structure, the oxide film spacer 6 is formed on the sidewall of the gate electrode structure. Thereafter, a high concentration impurity region 7 is formed in the silicon substrate 1.
상술한 종래 기술은 필드 산화막(2) 형성 후에 게이트 전극(4) 형성을 위한 패턴 공정을 실시하면 액티브 영역과 필드 영역의 단차 때문에 심한 노칭(Notching)문제가 유발된다. 이것은 반사도를 줄이는 Arc층(40)을 사용하면 어느정도 막을 수 있지만 제2도에 도시된 바와 같이 디자인 룰이 작아짐에 따라 a와 b의 크기가 줄어들게 되어 마스크 공정에서의 노칭 문제는 더욱 심각해진다. 또한 폴리사이드와 같이 반사도가 큰 실리사이드층을 사용할 경우에는 더욱더 심각해진다. 참고로, 제2도에서 A는 소오스/드레인 영역(액티브 영역)을 나타내고, B는 게이트 영역을 나타내며 C는 필드 영역을 나타낸다.In the above-described conventional technique, when the pattern process for forming the gate electrode 4 is performed after the field oxide film 2 is formed, a severe notching problem is caused due to the step difference between the active region and the field region. This can be prevented to some extent by using the Arc layer 40 which reduces the reflectivity, but the size of a and b decreases as the design rule becomes smaller as shown in FIG. In addition, the use of a highly reflective silicide layer, such as polyside, becomes more serious. For reference, in FIG. 2, A represents a source / drain region (active region), B represents a gate region, and C represents a field region.
따라서, 본 발명은 필드 산화막 형성 후에 액티브 영역 상부에 실리콘 엑피텍셜층을 형성시킨 후 게이트 패턴을 형성하므로써 상술한 단점을 해소할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of solving the above-mentioned disadvantages by forming a gate pattern after forming a silicon epitaxial layer on an active region after forming a field oxide film.
상술한 목적을 달성하기 위한 본 발명은 필드 산화막이 형성된 실리콘 기판상에 실리콘 에피텍셜층을 형성하는 단계와, 상기 실리콘 에피텍셜층상에 게이트 전극을 형성하는 단계와, 불순물 주입공정으로 상기 게이트 전극의 주변부에 불순물 영역을 형성하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to form a silicon epitaxial layer on a silicon substrate on which a field oxide film is formed, forming a gate electrode on the silicon epitaxial layer, and impurity implantation process of the gate electrode And forming an impurity region in the peripheral portion.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3a도 내지 제3d도는 본 발명에 따른 반도체 소자 제조방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.3A to 3D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a semiconductor device according to the present invention.
제3a도는 필드 산화막(2)을 형성하여 액티브 영역과 필드 영역을 확정한 후 액티브 영역의 실리콘 기판(1) 상부에 희생 산화막(8)을 형성한 상태의 단면도 이다.3A is a cross-sectional view of a state in which the sacrificial oxide film 8 is formed on the silicon substrate 1 in the active region after the field oxide film 2 is formed to determine the active region and the field region.
제3b도와 관련하여, 희생 산화막(8)을 제거한 후 실리콘 에피텍셜 공정을 실하여 에피텍셜층(10)을 형성한다. 이 에피텍셜층(10)은 실리콘 기판(1)의 일부가 되며, 액티브 영역과 필드 영역간의 단차를 제거하여 게이트 패턴 형성시 노칭(Notching) 현상을 방지하는 역할을 한다. 따라서, 액티브 영역과 필드 영역간의 단차를 제거하기 위한 목적을 달성하기 위하여, 에피텍셜층(10)은 필드 산화막(2)의 상부면을 고려하여 그 형성 두께를 결정한다.3B, the epitaxial layer 10 is formed by removing the sacrificial oxide film 8 and then performing a silicon epitaxial process. The epitaxial layer 10 becomes part of the silicon substrate 1 and serves to prevent notching when forming a gate pattern by removing a step between an active region and a field region. Therefore, in order to achieve the purpose of eliminating the step between the active region and the field region, the epitaxial layer 10 determines its formation thickness in consideration of the top surface of the field oxide film 2.
제3c도와 관련하여, 에피텍셜층(10)의 상부에 스크린 산화막(도시안됨)을 성장시킨 후 문턱전압 조절을 위한 불순물 주입공정을 실시한다. 그후, 스크린 산화막을 제거한다. 에피텍셜층(10) 상부에 게이트 산화막(11)을 형성하고, 게이트 산화막(11)상에 다결정 실리콘을 증착한 후 불순물 도핑공정 및 게이트 마스크를 사용한 식각공정으로 게이트 전극(12)을 형성한다.Referring to FIG. 3C, after the screen oxide film (not shown) is grown on the epitaxial layer 10, an impurity implantation process for adjusting the threshold voltage is performed. Thereafter, the screen oxide film is removed. A gate oxide layer 11 is formed on the epitaxial layer 10, polycrystalline silicon is deposited on the gate oxide layer 11, and the gate electrode 12 is formed by an impurity doping process and an etching process using a gate mask.
여기서, 게이트 전극(12)은 폴리사이드층으로 형성되어도 무방하다. 또한 실리콘 에피텍셜층(10)을 이용하여 단차를 제거했기 때문에 노칭 방지를 위한 Arc층은 사용하지 않아도 된다.Here, the gate electrode 12 may be formed of a polyside layer. In addition, since the step is removed using the silicon epitaxial layer 10, the arc layer for preventing notching may not be used.
제3d도와 관련하여, 게이트 전극(12)과 필드 산화막(2) 사이의 실리콘 기판(1)에 저농도 불순물 영역(5)을 형성한 후 게이트 전극(12) 측벽에 산화막 스페이서(6)를 형성한다. 이후, 산화막 스페이서(6)가 형성된 게이트 전극(12)과 필드 산화막(2) 사이의 실리콘 기판(1)에 고농도 불순물 영역(7)을 형성한다. 한편, 고농도 불순물 영역(7)의 엣지 부분(D)이 종래 기술에 비하여 액티브 영역쪽으로 당겨서 형성되므로, 즉 필드 산화막(2)의 가장자리부터 게이트 전극(12) 사이의 실리콘 기판(1)에 형성되어 접합 항복 전압(Junction Breakdown Voltage)을 높일 수 있다.Regarding FIG. 3D, a low concentration impurity region 5 is formed in the silicon substrate 1 between the gate electrode 12 and the field oxide film 2, and then an oxide spacer 6 is formed on the sidewall of the gate electrode 12. . Thereafter, a high concentration impurity region 7 is formed in the silicon substrate 1 between the gate electrode 12 on which the oxide film spacer 6 is formed and the field oxide film 2. On the other hand, since the edge portion D of the highly concentrated impurity region 7 is formed by pulling toward the active region as compared with the prior art, that is, it is formed on the silicon substrate 1 between the edge of the field oxide film 2 and the gate electrode 12. The junction breakdown voltage can be increased.
또한, 엣지 부분(D)이 종래의 기술에 비하여 액티브 영역 쪽으로 형성됨으로 인하여 필드 영역을 통한 펀치 쓰루우 현상을 방지할 수 있다. 그로 인하여 필드 영역의 최소폭을 줄일 수 있다.In addition, since the edge portion D is formed toward the active region as compared with the prior art, a punch through phenomenon through the field region can be prevented. Thereby, the minimum width of the field area can be reduced.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940039472A KR0168119B1 (en) | 1994-12-30 | 1994-12-30 | Method of manufacturing semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940039472A KR0168119B1 (en) | 1994-12-30 | 1994-12-30 | Method of manufacturing semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960026121A KR960026121A (en) | 1996-07-22 |
| KR0168119B1 true KR0168119B1 (en) | 1999-02-01 |
Family
ID=19405570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940039472A KR0168119B1 (en) | 1994-12-30 | 1994-12-30 | Method of manufacturing semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0168119B1 (en) |
-
1994
- 1994-12-30 KR KR1019940039472A patent/KR0168119B1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| KR960026121A (en) | 1996-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5087581A (en) | Method of forming vertical FET device with low gate to source overlap capacitance | |
| KR940002400B1 (en) | Manufacturing method of semiconductor device with recess gate | |
| KR940006702B1 (en) | Manufacturing method of mosfet | |
| US5073519A (en) | Method of fabricating a vertical FET device with low gate to drain overlap capacitance | |
| US4373965A (en) | Suppression of parasitic sidewall transistors in locos structures | |
| KR19990057943A (en) | Contact hole formation method of semiconductor device | |
| KR100272527B1 (en) | Semiconductor device and method for fabricating the same | |
| US5523250A (en) | Method of manufacturing a MOSFET with LDD regions | |
| KR0168119B1 (en) | Method of manufacturing semiconductor devices | |
| KR100429873B1 (en) | MOS transistor and forming method thereof | |
| CN111435680B (en) | Stepped element and method for manufacturing the same | |
| KR100307541B1 (en) | Manufacturing method for mos transistor | |
| KR100244411B1 (en) | Method for manufacturing semiconductor device | |
| KR20050015714A (en) | MOS transistor and fabrication method thereof | |
| KR100223795B1 (en) | Manufacturing method of semiconductor memory device | |
| KR100239455B1 (en) | Method for fabricating semiconductor device | |
| KR0167605B1 (en) | Mos-transistor fabrication method | |
| KR0166506B1 (en) | Manufacture of a semiconductor device | |
| KR100241540B1 (en) | Method for forming transistor of semiconductor device | |
| KR100224783B1 (en) | Method of forming an element isolation region in a semiconductor device | |
| KR100460704B1 (en) | Method for fabricating bottom gate-type tft of sram to increase capacitance of node | |
| KR930001565B1 (en) | Manufacturing method of c-mos transistor | |
| KR950002199B1 (en) | Making method of ldd for mosfet | |
| KR100248510B1 (en) | Method for manufacturing a semiconductor device | |
| KR100223333B1 (en) | Method for forming a contact of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20120924 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20130916 Year of fee payment: 16 |