KR100224783B1 - Method of forming an element isolation region in a semiconductor device - Google Patents
Method of forming an element isolation region in a semiconductor device Download PDFInfo
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- KR100224783B1 KR100224783B1 KR1019960080224A KR19960080224A KR100224783B1 KR 100224783 B1 KR100224783 B1 KR 100224783B1 KR 1019960080224 A KR1019960080224 A KR 1019960080224A KR 19960080224 A KR19960080224 A KR 19960080224A KR 100224783 B1 KR100224783 B1 KR 100224783B1
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- device isolation
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- 238000002955 isolation Methods 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000002019 doping agent Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- 239000003963 antioxidant agent Substances 0.000 claims description 4
- 230000003078 antioxidant effect Effects 0.000 claims description 4
- 230000003064 anti-oxidating effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000000843 powder Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 4
- 230000007423 decrease Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 241000219122 Cucurbita Species 0.000 description 1
- 235000009852 Cucurbita pepo Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
본 발명은 반도체 소자의 반도체 소자의 소자분리막 형성방법에 관한 것으로, 소자 분리막이 형성될 부분의 실리콘 기판을 일정깊이만큼 식각하여 단차를 만들고 전체구조 상부에 다결정실리콘을 증착한 다음 도펀트를 도핑하고, 이후 소자분리 산화막의 중심부위가 될 다결정실리콘 지역을 보호하기 위해 식각방지 산화막을 증착한뒤 전면식각하고, 또한 다결정실리콘을 전면식각하고 잔류한 식각방지 산화막을 제거한 뒤 소자분리 산화막 형성을 위한 산화를 실시함으로써, 소자분리막의 모서리부에서는 산화속도를 줄여 버즈빅을 줄이도록 하고, 소자분리 산화막의 중심 부에서는 평탄화게 성장되도록하여 반도체 소자의 집적도를 증가시키고 소자 제조 공정 수율 및 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method of forming a device isolation film of a semiconductor device of a semiconductor device, by etching a silicon substrate of a portion where the device isolation film is to be formed to a certain depth to make a step, depositing polysilicon on the entire structure, and then doping the dopant, After that, in order to protect the polysilicon region that will be on the center of the device isolation oxide film, an etch-resistant oxide film is deposited and then etched. Then, the polycrystalline silicon is etched and the remaining etch-resistant oxide film is removed, followed by oxidation to form a device isolation oxide film. By reducing the oxidation rate at the corners of the device isolation film to reduce buzz big, and at the center of the device isolation oxide film to grow flattened, the integration degree of the semiconductor device can be increased and the device manufacturing process yield and reliability can be improved. Technology.
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 특히 소자 분리막의 미성장을 방지하고 버즈빅(Bird's Beak)을 줄여 반도체 소자의 제조공정 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and in particular, to prevent the growth of the device isolation film and reduce the Bird's Beak, thereby forming a device isolation film of a semiconductor device capable of improving the yield and reliability of the manufacturing process of the semiconductor device. It is about a method.
종래의 소자분리 기술에 있어서, 반도체 디바이스의 집적도가 증가하면 소자 분리막의 크기도 함께 감소하게 되는데, 상기와 같이 소자분리막이 형성될 부위가 좁은 지역에서는 소자분리 산화막이 거의 형성되지 않아 소자의 고집적도를 높이는데 큰 제약이 되고 있다.In the conventional device isolation technology, as the degree of integration of a semiconductor device increases, the size of the device isolation film also decreases. However, in the region where the device isolation film is to be formed, the device isolation oxide film is hardly formed and thus high integration of the device is achieved. There is a big constraint to increase.
또한 버즈빅 현상을 줄이기 위한 종래의 기술에 있어서는 버즈빅이 생성되는 부위에 스트레스(Stress)를 증가시켜 주는 방법을 사용하는데, 이는 차후에 진행되는 게이트 산화막의 신뢰성을 떨어뜨리고 셀간 누설전류 경로를 야기하는 문제가 있다.In addition, the conventional technique for reducing the buzz big phenomenon is to use a method to increase the stress at the site where the buzz is generated, which decreases the reliability of the gate oxide film that is going on in the future and causes a leakage current path between cells there is a problem.
또한 종래에는 산화방지막이 실리콘기판 위로 성장함으로써 후속공정에서 평판화 문제와 더불어 마스크 패턴형성문제등을 야기하는 문제가 있다.In addition, conventionally, since the antioxidant film is grown on the silicon substrate, there is a problem that causes a problem of flattening and mask pattern formation in a subsequent process.
따라서 본 발명은 상기와 같은 문제점을 해결하기 위해서 소자 분리막의 에지부분에서의 스트레스를 완화하기 위해 다결정실리콘 측벽을 형성하고, 또한 버즈빅을 줄이고 소자 분리막의 원할한 성장을 위한 일련의 공정을 수행함으로써 반도체 소자의 제조공정 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 소자분리막 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention is to solve the above problems by forming a polysilicon sidewall to relieve stress at the edge portion of the device isolation layer, and also by performing a series of processes for reducing the buzz big and smooth growth of the device isolation layer It is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device capable of improving the manufacturing process yield and reliability of the semiconductor device.
제1도 내지 제9도는 본 발명의 방법에 따른 반도체 소자의 소자분리막 제조공 정도.1 to 9 are views showing the device isolation film manufacturing hole of the semiconductor device according to the method of the present invention.
제10도는 본 발명의 다른 실시예에 따른 반도체 소자의 소자분리막 공정단계 를 도시한 단면도 .10 is a cross-sectional view illustrating a device isolation film processing step of a semiconductor device in accordance with another embodiment of the present invention.
* 도면의 주요부분에 대한 설명* Description of the main parts of the drawings
11 : 반도체 기판 12 : 패드 산화막11 semiconductor substrate 12 pad oxide film
13 : 질화막 14 : 감광막13: nitride film 14: photosensitive film
15 : 다결정실리콘 16 : 식각방지 산화막15 polycrystalline silicon 16: etching prevention oxide film
17 : 필드 산화막 18 : 측벽 질화막17 field oxide film 18 sidewall nitride film
상기 목적을 달성하기 위하여 본 발명에서는, 실리콘 기판위에 패드 산화막과 질화막을 소정두께로 형성하는 단계와, 소자분리 마스크를 사용하여 소자분리막이 형성될 영역을 패터닝하는 단계와, 노출된 실리콘을 소정깊이만큼 식각하는 단계와, 전체구조 상부에 다결정실리콘을 소정두께로 증착하는 단계와, 전체구조 상부에 도펀트를 도핑하는 단계와, 전체구조 상부에 식각장벽물질을 소정두께 증착한 후 전면식각하여 상기 식각장벽물질이 실리콘 기판의 식각홈내에 잔류하도록하는 단계와, 상기 다결정실리콘을 전면식각하여 상기 식각장벽물질의 측면부위까지 잔류 하도록 하는 단계와, 상기 잔류한 다결정실리콘 상부의 식각장벽물질을 제거하는 단계와, 상기 잔류한 다결정실리콘을 산화하여 식각된 소자 분리막을 형성하는 단계로 구성되는 반도체소자의 소자분리막 형성방법을 제공한다.In order to achieve the above object, in the present invention, forming a pad oxide film and a nitride film on a silicon substrate to a predetermined thickness, patterning a region where the device isolation film is to be formed by using a device isolation mask, and a predetermined depth of the exposed silicon Etching, depositing polycrystalline silicon on the entire structure to a predetermined thickness, doping a dopant on the entire structure, depositing an etch barrier material on the entire structure, and then etching the entire surface to etch the etching. Allowing the barrier material to remain in the etch groove of the silicon substrate, etching the entire polysilicon to the side of the etch barrier material, and removing the etch barrier material on the remaining polysilicon. And oxidizing the remaining polysilicon to form an etched device isolation layer. It provides a device isolation method for forming a semiconductor device.
이하 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제1도 내지 제9도는 본 발명의 방법에 따른 반도체 소자의 소자분리막 형성 제조 공정도이다.1 through 9 are process charts for forming a device isolation film of a semiconductor device according to the method of the present invention.
제1도을 참조하면, 실리콘 기판(11) 위에 패드 산화막(12)과 산화 방지 질화막(13)을 증착한 후 전체 구조 상부에 감광막을 증착하여 소자분리막이 형성될 영역을 소자분리 마스크를 사용하여 패턴닝한다.Referring to FIG. 1, after the pad oxide layer 12 and the anti-oxidation nitride layer 13 are deposited on the silicon substrate 11, a photoresist layer is deposited on the entire structure to pattern an area where the device isolation layer is to be formed using a device isolation mask. Ning.
이때 상기 패드 산화막(12)은 질화막(13)의 스트레스가 실리콘 기판(11)에 전 달되는 것을 완화시켜 주는 역할을 한다.In this case, the pad oxide film 12 serves to relieve the stress of the nitride film 13 from being transferred to the silicon substrate 11.
제2도를 참조하면, 상기 감광막 패턴(14)을 식각 마스크로 하여 하부의 질화막(13) 및 패드 산화막(12)을 식각하며, 또한 실리콘 기판(11)을 일정 깊이로 식각한다.Referring to FIG. 2, the lower nitride layer 13 and the pad oxide layer 12 are etched using the photoresist pattern 14 as an etch mask, and the silicon substrate 11 is etched to a predetermined depth.
제3도를 참조하면, 전체구조 상부에 다결정실리콘을 소정두께 만큼 증착하고 도펀트를 도핑한다.Referring to FIG. 3, polycrystalline silicon is deposited to a predetermined thickness on the entire structure and doped with a dopant.
제4도를 참조하면, 상기 제3도의 단계에서 단차가 있는 다결정실리콘(13)에 도펀트를 도핑하면 소자분리 산화막이 형성될 지역의 바깥구석에는 단차로 인하여 도핑이 덜되어 산화속도가 느리게되고 이러한 영향으로 버즈빅이 작게 자라는 효과를 얻을 수 있다.Referring to FIG. 4, when the dopant is doped into the stepped polysilicon 13 in the step of FIG. 3, the doping is reduced in the outer corner of the region where the device isolation oxide film is to be formed, resulting in a slower oxidation rate. The effect is that Buzzvik grows smaller.
또한 중심부위는 도핑이 많이 되어 소자분리 산화막이 쉽게 성장되어 고집적 반도체소자에서의 소자분리 산화막의 비성장을 방지할 수 있게 된다.In addition, since the doping is much on the center, the device isolation oxide film is easily grown, thereby preventing the non-growth of the device isolation oxide film in the highly integrated semiconductor device.
상기 공정후 게이트 산화막의 신뢰성을 떨어뜨리고 셀사이의 누설전류의 원인이 되는 소자분리막 구석에 집중되는 스트레스를 완화하기 위해 소자 분리막의 모서리부에 해당하는 지역을 다결정실리콘(15) 측벽모양으로 만들기 위해서 골이 진 지역을 식각 장벽물질 예컨데 식각방지용 산화막(16)으로 채운 다음 이를 전면식각 한다.In order to reduce the reliability of the gate oxide film after the process and to relieve stress concentrated in the corners of the device isolation layer causing leakage current between the cells, the area corresponding to the corner of the device isolation layer is formed into the polysilicon 15 sidewall shape. The ribbed area is filled with an etch barrier material such as an etch-resistant oxide layer 16 and then etched entirely.
그 후 다결정실리콘(15)을 전면식각하여 다결정실리콘 측벽모양으로 만든다. 고자분리막 구석이 될 지역을 다결정실리론측벽모양으로 만들기 위해서 골이 진 지역을 식각장벽물질로 채운다. 제5도를 참조하면, 산화막이 잘 성장되도록 고농도로 도핑된 소자분리산화막 중심부위가 될 다결정실리콘(15) 지역을 보호하기 위해 산화막(16)을 증착한 뒤 이를 전면식각한다.Thereafter, the polysilicon 15 is etched entirely to form a polysilicon sidewall. In order to make the polysilicon sidewall shape into the corner of the gourd separator, the ribbed area is filled with the etch barrier material. Referring to FIG. 5, after the oxide layer 16 is deposited, the entire surface is etched to protect the region of the polysilicon 15 that will be on the center of the heavily doped device isolation oxide layer so that the oxide layer is well grown.
제6도를 참조하면, 다결정실리콘(15)을 전면식각하여 다결정실리콘 측벽모양 으로 만든다.Referring to FIG. 6, polysilicon 15 is etched entirely to form polysilicon sidewalls.
제7도를 참조하면, 이후 다결정실리콘(15) 위에 남아 있는 식각장벽물질 즉 식각방지 산화막(16)을 제거한다.Referring to FIG. 7, the etch barrier material remaining on the polysilicon 15, that is, the anti-etching oxide layer 16, is removed.
즉, 상기 제7도는 다결정실리콘(15) 위에 남아 있는 식각장벽물질(16)을 제거 한 상태의 단면도이며, 산화막이 형성될 지역이 입체적으로 열리게 되어 산화막이 쉽게 형성 된다.That is, FIG. 7 is a cross-sectional view of the etching barrier material 16 remaining on the polysilicon 15, and the region in which the oxide film is to be formed is three-dimensionally opened to easily form the oxide film.
제8도를 참조하면, 노출된 다결정실리콘(15)을 산화시켜 소자분리 산화막(17) 을 형성한다.Referring to FIG. 8, the exposed polycrystalline silicon 15 is oxidized to form an isolation oxide layer 17.
제9도를 참조하면, 이후 약간의 산화막(17)을 제거하고 잔류한 질화막(13)을 제거하면 도시된 바와같은 최종 소자분리 산화막(17)을 얻게 된다.Referring to FIG. 9, after removing some of the oxide film 17 and removing the remaining nitride film 13, the final device isolation oxide film 17 as shown is obtained.
상기 제9도에서 볼 수 있는 것처럼, 소자분리 산화막(17)이 형성되는 곳이 실리콘기판(11)보다 아래이며 따라서 활성소자가 형성될 부분은 산화공정시에 생기는 버즈빅등의 영향을 받지 않게 된다. 또한 소자 분리막(17) 구석에 집중되는 스트레스도 완화되며, 소자분리막의 모양도 급격하지 않은 완만한 형상으로 형성된다.As can be seen in FIG. 9, the place where the element isolation oxide film 17 is formed is lower than the silicon substrate 11 so that the portion where the active element is to be formed is not affected by the buzz big, etc. generated during the oxidation process. do. In addition, stress concentrated in the corners of the device isolation layer 17 is also alleviated, and the shape of the device isolation layer is also formed in a gentle shape with no abruptness.
그리고 실리콘기판(11) 위의 산화막 또한 평탄하게 성장되어 반도체 디바이스 제조의 집적도를 증가시키고 안정성 및 신뢰성이 높은 소자분리막을 형성할 수가 있게 된다.In addition, the oxide film on the silicon substrate 11 is also grown to increase the degree of integration of semiconductor device manufacturing and to form a device isolation film having high stability and reliability.
한편 본 발명의 다른 실시예로서, 제10도를 참조하면, 상기 본 발명의 제7도 공정이후, 즉 다결정실리콘(15)을 전면식각하고서 산화방지 질화막(18)을 증착하고서 이를 전면식각한 뒤 산화방지막을 제거하여 질화막의 측벽을 형성하고 상기 제7도 이후 공정을 실시하면 버즈빅을 더욱 더 줄일 수 있는 소자분리 산화막을 형성할 수가 있게 된다.Meanwhile, as another embodiment of the present invention, referring to FIG. 10, after the process of FIG. 7 of the present invention, that is, after the polysilicon 15 is etched, the antioxidant nitride film 18 is deposited and then etched. By removing the antioxidant film to form the sidewall of the nitride film and performing the process after FIG. 7, it is possible to form a device isolation oxide film which can further reduce the Buzz Big.
이상 상기한 바와같이, 본 발명의 방법은 소자 분리막의 에지부분에서의 스트레스를 완화하기 위해 다결정실리콘 측벽을 형성하고, 또한 버즈빅을 줄이고 소자 분리막의 원할한 성장을 위한 일련의 공정을 수행함으로써 반도체 소자의 제조공정 수율 및 신뢰성을 향상시킬 수 있다.As described above, the method of the present invention provides a semiconductor by forming a polysilicon sidewall to relieve stress at the edge of the device isolation layer, and also performing a series of processes for reducing buzz and reducing the growth of the device isolation layer. It is possible to improve the manufacturing process yield and reliability of the device.
Claims (7)
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