KR960014449B1 - Forming method of field oxide in a semiconductor device - Google Patents
Forming method of field oxide in a semiconductor device Download PDFInfo
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- KR960014449B1 KR960014449B1 KR1019930028115A KR930028115A KR960014449B1 KR 960014449 B1 KR960014449 B1 KR 960014449B1 KR 1019930028115 A KR1019930028115 A KR 1019930028115A KR 930028115 A KR930028115 A KR 930028115A KR 960014449 B1 KR960014449 B1 KR 960014449B1
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- South Korea
- Prior art keywords
- oxide film
- field oxide
- forming
- semiconductor substrate
- silicon nitride
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920001296 polysiloxane Polymers 0.000 abstract 4
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 210000003323 beak Anatomy 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
제1a도 내지 제1b도는 종래의 필드 산화막 제조 공정도.1A to 1B show a conventional field oxide film production process.
제2a도 내지 제2d도는 본 발명에 다른 필드 산화막 제조 공정도.2A to 2D show a process for producing a field oxide film according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 패드(Pad) 산화막DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Pad oxide film
3 : 실리콘 질화막 4 : 스페이서(Spacer)3: silicon nitride film 4: spacer
5 : 필드(Field) 산화막 6 : 트렌치5: field oxide film 6: trench
본 발명은 반도체 제조 공정중 반도체 소자의 필드 산화막 제조 방법에 관한 것이다.The present invention relates to a method for producing a field oxide film of a semiconductor device during a semiconductor manufacturing process.
일반적으로, 반도체 소자의 집적도가 증가함에 따라 단위 셀(Cell)의 크기도 점점 작아지게 되며, 따라서 소자와 소자사이를 절연시켜 주는 소자분리막인 필드 산화막의 크기도 작아지게 된다.In general, as the degree of integration of semiconductor devices increases, the size of a unit cell becomes smaller, and thus, the size of a field oxide film, which is an isolation layer that insulates between devices, also becomes smaller.
제1a도 내지 제1b도는 종래의 필드 산화막 제조 공정도로서, 먼저, 제1a도에 도시된 바와 같이 반도체 기판(1) 상부에 이후에 증착되는 증착막에 대한 스트레스(Stress)를 감소시켜 주기 위하여 패드 산화막(2)을 형성한 후 상기 패드 산화막(2)상에 반도체 기판의 산화를 막아주는 역할을 하는 실리콘 질화막(3)을 형성한 후 예정된 부위(도면의 M)의 상기 실리콘 질화막(3)을 식각한다.1A to 1B are conventional process diagrams for manufacturing a field oxide film. First, as shown in FIG. 1A, a pad oxide film is formed so as to reduce stress on a deposited film which is subsequently deposited on a semiconductor substrate 1. (2) and then forming a silicon nitride film 3 on the pad oxide film 2 to prevent oxidation of the semiconductor substrate, and then etching the silicon nitride film 3 at a predetermined site (M in the drawing). do.
계속해서, 제1b도와 같이 상기 식각하고 남아 있는 실리콘 질화막(3)을 산화 방지막으로 웨이퍼를 산화 시키므로써 필드 산화막(5)을 형성한다.Subsequently, as shown in FIG. 1B, the etched and remaining silicon nitride film 3 is oxidized with the anti-oxidation film to form a field oxide film 5.
그러나, 도면에 도시된 바와 같이 필드 산화막의 크기(도면의 L)는 새부리(Bir's Beak) 모양에 의해 예정된 필드 산화막의 패턴 크기(제1a도의 M)보다 커지게 되며, 그렇기 때문에 활성(Actice) 영역의 크기는 상대적으로 줄어든다. 또한 필드 산화막의 높이도 활성영역보다 높아지게 되는(도면의 H2) 문제점이 있었다.However, as shown in the figure, the size of the field oxide film (L in the drawing) becomes larger than the pattern size of the field oxide film (M in FIG. 1a), which is predetermined due to the shape of the bird's beak, and thus the active area. The size of is reduced relatively. In addition, there is a problem that the height of the field oxide film is also higher than the active region (H 2 in the drawing).
따라서, 본 발명은 스페이서 및 트렌치 공정을 이용하여 필드 산화막의 새부리 모양에 의한 활성영역의 감소를 줄이고 또한 활성영역과의 단차도 줄일 수 있는 반도체 소자의 필드 산화막 제조 방법을 제공함을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a method for manufacturing a field oxide film of a semiconductor device, which can reduce the active region due to the beak shape of the field oxide film and also reduce the step difference with the active region by using a spacer and a trench process.
상기 목적을 달성하기 위하여 안출된 본 발명은 반도체 기판 상부에 패드 산화막을 형성하는 단계, 상기 패드 산화막 상부에 실리콘 질화막을 형성한 후 이후에 필드 산화막이 형성될 예정된 부위에 해당하는 상기 실리콘 질화막을 식각하는 단계, 웨이퍼 구조 전체 상부에 실리콘 질화막을 증착한 후 다시 전면식각하여 이미 형성되어 있던 상기 실리콘 질화막 측벽에 스페이서를 형성하는 단계, 상기 스페이서 사이의 반도체 기판에 트렌치를 형성하는 단계, 상기 웨이퍼를 산화시켜 필드 산화막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention devised to achieve the above object is to form a pad oxide film on the semiconductor substrate, the silicon nitride film formed on the pad oxide film after the etching the silicon nitride film corresponding to the site where the field oxide film is to be formed later Depositing a silicon nitride film over the entire wafer structure, and then etching the entire surface to form a spacer on a sidewall of the silicon nitride film that is already formed; forming a trench in a semiconductor substrate between the spacers; and oxidizing the wafer. To form a field oxide film.
이하, 첨부한 도면 제2a도 내지 제2d도를 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings 2A to 2D.
제2a도 내지 제2d도는 본 발명에 따른 필드 산화막 제조 공정도로서, 먼저, 제2a도는 반도체 기판(1) 상부에 이후에 증착되는 증착막에 대한 스트레스(Stress)를 감소시켜 주기 위하여 패드 산화막(2)을 형성한 후 상기 패드 산화막(2)상에 반도체 기판의 산화를 막아주는 역할을 하는 실리콘 질화막(3)을 형성한 후 예정된부위(도면의 M)의 상기 실리콘 질화막(3)은 실리콘 산화막을 사용하거나 실리콘 산화막과 다결정 실리콘의 이중구조를 사용할 수 있다.2A to 2D are process charts for manufacturing a field oxide film according to the present invention. First, FIG. 2A is a diagram illustrating a pad oxide film 2 in order to reduce stress on a deposited film which is subsequently deposited on a semiconductor substrate 1. After forming a silicon nitride film (3) that serves to prevent the oxidation of the semiconductor substrate on the pad oxide film (2) after the silicon nitride film (3) of the predetermined portion (M in the drawing) using a silicon oxide film Alternatively, a dual structure of a silicon oxide film and polycrystalline silicon can be used.
이어서, 제2b도에 도시된 바와 같이 웨이퍼 구조 전체 상부에 실리콘 질화막을 증착한 후 다시 전면식각하여 이미 형성되어 있던 상기 실리콘 질화막(3) 측벽에 스페이서(4)를 형성한다.Subsequently, as shown in FIG. 2B, a silicon nitride film is deposited on the entire wafer structure and then etched back to form a spacer 4 on the sidewall of the silicon nitride film 3 that has already been formed.
이와 같이 스페이서(4)를 형성하는 것은 이후에 형성될 필드 산화막의 크기를 소정크기(도면의 2m)만큼 줄이기 위해서이다.The formation of the spacers 4 in this way is to reduce the size of the field oxide film to be formed later by a predetermined size (2 m in the figure).
계속해서, 제2c도와 같이 상기 스페이서(4) 사이의 반도체 기판(1)에 트렌치(6)를 형성한다.Subsequently, as shown in FIG. 2C, a trench 6 is formed in the semiconductor substrate 1 between the spacers 4.
이와 같이 트렌치(6)를 형성하는 것은 이후 형성되는 필드 산화막의 두께를 낮추어 활성영역과의 단차를 없애기 위해서이다.The trench 6 is formed in this way in order to reduce the thickness of the field oxide film to be formed later, thereby eliminating the step with the active region.
그리고, 상기 트렌치(6)는 등방성 식각을 통하여 얻을 수도 있고 필드산화공정후 얻은 두꺼운 산화막을 다시 제거함으로써 얻을 수도 있다.The trench 6 may be obtained through isotropic etching or by removing the thick oxide film obtained after the field oxidation process again.
끝으로, 제2d도는 도시된 바와 같이 웨이퍼를 산화시켜 필드 산화막(5)을 형성한다.Finally, FIG. 2D oxidizes the wafer to form the field oxide film 5 as shown.
이때 필드 산화막(5)의 크기(도면의 L')는 예정된 필드 산화막의 패턴의 크기(제2a도의 M)보다 작아지게 된다. 또한 기존의 제조 방법에 따른 필드 화막의 두께(제1b도의 H1+H2)보다 두께가 낮추져(H1'H1+H2)활성 영역과의 단차도 없어지게 된다.At this time, the size (L 'of the figure) of the field oxide film 5 becomes smaller than the size (M of FIG. 2a) of the pattern of the predetermined field oxide film. In addition, the thickness of the field flame according to the conventional manufacturing method (H 1 + H 2 of FIG. 1b) is lower (H 1 'H 1 + H 2 ) is also eliminated the step with the active region.
상기와 같이 이루어지는 본 발명은 필드 산화막의 형성시에 발생하는 새부리 모양에 의한 활성영역의 감소를 줄이므로써 반도체 소자의 크기를 줄일 수 있으며, 또한 필드 산화막과 주변의 활성영역과의 단차를 줄이므로써 고집적 반도체 공정을 용이하게 하는 효과가 있다.According to the present invention as described above, the size of the semiconductor device can be reduced by reducing the decrease of the active region due to the beak shape generated when the field oxide film is formed, and the step difference between the field oxide film and the active region around the field can be reduced. Therefore, there is an effect of facilitating a highly integrated semiconductor process.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930028115A KR960014449B1 (en) | 1993-12-16 | 1993-12-16 | Forming method of field oxide in a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930028115A KR960014449B1 (en) | 1993-12-16 | 1993-12-16 | Forming method of field oxide in a semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR950021358A KR950021358A (en) | 1995-07-26 |
| KR960014449B1 true KR960014449B1 (en) | 1996-10-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930028115A KR960014449B1 (en) | 1993-12-16 | 1993-12-16 | Forming method of field oxide in a semiconductor device |
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| KR (1) | KR960014449B1 (en) |
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