KR100198620B1 - Manufacturing method of isolation film using trench - Google Patents
Manufacturing method of isolation film using trench Download PDFInfo
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- KR100198620B1 KR100198620B1 KR1019950058887A KR19950058887A KR100198620B1 KR 100198620 B1 KR100198620 B1 KR 100198620B1 KR 1019950058887 A KR1019950058887 A KR 1019950058887A KR 19950058887 A KR19950058887 A KR 19950058887A KR 100198620 B1 KR100198620 B1 KR 100198620B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Abstract
본 발명은 DRAM 셀의 소자 격리막 형성공정에 관한 것으로, 반도체 기판에 제1 산화막, 질화막을 차례로 증착하고, 상기 질화막층을 포토리소그래피 공정으로 선택적으로 제거하여 소자격리 영역을 정의하는 공정과, 상기 질화막층이 제거된 소자격리 영역의 반도체 기판에 건식각(Dry Etch)으로 트랜치를 형성하는 공정과, 전면에 제2 산화막을 증착하고 에치백 하여 트렌치 측면에 측벽을 형성하는 공정과, 상기 측벽이 형성된 트렌치 하부영역을 습식식각으로 넓혀 충분한 소자격리 영역을 확보하는 공정과, 상기 확장된 트렌치 하부영역에 열산화막을 성장시키고, 상기 트렌치 영역을 포함하는 전면에 충분히 두꺼운 제3 산화막층을 형성하는 공정과, 상기 제3 산화막층은 활성영역에 남아 있는 질화막과 동일 높이로 식각한 후, 상기 질화막을 제거하는 공정과, 상기 반도체 기판의 표면에 돌출되어 있는 제1, 2, 3 산화막을 에치백 하여 소자 격리층을 형성하는 공정으로 이루어져 격리 산화막의 버즈빅 현상을 막고, 누설전류를 효율적으로 제어할 수 있는 트렌치를 이용한 소자 격리막 형성방법에 관한 것이다.The present invention relates to a device isolation film forming process of a DRAM cell, comprising: depositing a first oxide film and a nitride film on a semiconductor substrate in order, and selectively removing the nitride film layer by a photolithography process to define a device isolation region; Forming a trench by dry etching on the semiconductor substrate of the device isolation region from which the layer is removed, forming a sidewall on the side of the trench by depositing and etching back a second oxide layer on the front surface, and forming the sidewall Widening the trench lower region by wet etching to secure a sufficient device isolation region; growing a thermal oxide film in the extended trench lower region; and forming a sufficiently thick third oxide layer on the entire surface including the trench region; The third oxide layer is etched at the same height as the nitride layer remaining in the active region, and then the nitride layer is removed. And forming a device isolation layer by etching back the first, second and third oxide films protruding from the surface of the semiconductor substrate, thereby preventing the buzzing phenomenon of the isolation oxide film and efficiently controlling the leakage current. It relates to a device isolation film forming method using.
Description
제1도 (a) 내지 (h)는 종래의 소자 격리층 형성을 위한 공정단면도.1 (a) to (h) are process cross-sectional views for forming a conventional device isolation layer.
제2도 (a) 내지 (k)는 본 발명의 소자 격리층 형성을 위한 공정단면도.2 (a) to (k) are process cross-sectional views for forming a device isolation layer of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20 : 반도체 기판 21 : 제1 산화막20 semiconductor substrate 21 first oxide film
22 : 질화막 23 : 제2 산화막22 nitride film 23 second oxide film
24 : 트렌치 측벽 25 : 열산화막24 trench sidewall 25 thermal oxide film
26 : 제3 산화막 27 : 소자격리 산화막26: third oxide film 27: device isolation oxide film
본 발명은 DRAM 셀의 소자 격리층 형성공정에 관한 것으로, 격리 산화막의 버즈빅(Bird's Beak) 현상을 막고, 누설전류를 효율적으로 제어할 수 있는 트렌치를 이용한 소자 격리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a device isolation layer forming process of a DRAM cell, and more particularly, to a method of forming a device isolation layer using a trench which can prevent a bird's beak phenomenon of an isolation oxide film and efficiently control leakage current.
이하 첨부된 도면을 참조하여 종래의 소자 격리막 형성공정에 대하여 설명하면 다음과 같다.Hereinafter, a device isolation layer forming process according to the related art will be described with reference to the accompanying drawings.
제1도 (a) 내지 (h)는 종래의 소자 격리층 형성을 위한 공정단면도이다.1 (a) to (h) are process cross-sectional views for forming a conventional device isolation layer.
종래 기술은 트렌치 LOCOS 형성기술 중에서 NSL 방법을 나타낸 것으로, 먼저, 제1 (a)에서와 같이, 반도체 기판(1) 상에 산화막(2), 제1 질화막(3)층을 차례대로 형성한 후에 제1도 (b)에서와 같이, 전면에 포토레지스트(4)를 도포하고, 소자 격리층이 형성될 부분만 제거되도록 패터닝한다.The prior art shows the NSL method in the trench LOCOS forming technique. First, as in the first (a), the oxide film 2 and the first nitride film 3 are sequentially formed on the semiconductor substrate 1. As shown in FIG. 1 (b), the photoresist 4 is applied to the entire surface and patterned so that only the portion where the device isolation layer is to be formed is removed.
이어, 제1도 (c)에서와 같이, 상기 포토레지스트(4)층을 마스크로 하여 상기 제1 질화막(3)층을 선택적으로 제거한다.Subsequently, as in FIG. 1C, the first nitride film 3 layer is selectively removed using the photoresist 4 layer as a mask.
그리고 제1도 (d)(e)에서와 같이, 전면에 제2 질화막(5)을 증착하고, 에치백 하여 측벽(6)을 형성한다.As shown in FIG. 1 (d) (e), the second nitride film 5 is deposited on the entire surface and etched back to form the sidewall 6.
이어, 제1도 (f)에서와 같이, 상기 측벽(6)이 형성된 제1 질화막(3)(선택적으로 제거된)층을 마스크로 하여 반도체 기판(1)을 일정 깊이 식각하여 트렌치를 형성한다.Next, as shown in FIG. 1 (f), the semiconductor substrate 1 is etched to a certain depth to form a trench using the first nitride film 3 (optionally removed) layer having the sidewalls 6 formed thereon as a mask. .
그리고 제1도 (g)(h)에서와 같이, 상기 트렌치 영역 내에 소자격리 산화막(8)을 성장시키고, 마스크로 사용된 측벽을 포함하는 질화막층을 제거한다.Then, as in FIG. 1 (g) (h), the device isolation oxide film 8 is grown in the trench region, and the nitride film layer including sidewalls used as a mask is removed.
이어, 상기 소자격리 산화막(8)의 상부를 성장시켜 소자 격리막을 완성하고, 상기 산화막(2)을 제거한다.Subsequently, an upper portion of the device isolation oxide film 8 is grown to complete the device isolation film, and the oxide film 2 is removed.
그러나 상기와 같은 종래의 소자 격리막 형성에 있어서는 다음과 같은 문제점이 있었다.However, in the conventional device isolation film formation as described above, there are the following problems.
활성영역을 정의한 후에, 측벽(Side Wall)을 형성하여 소자격리 영역을 확보하므로 디퓨젼(Diffusion)에 의해 격리영역의 깊이(Isolation Depth)가 작아지게 된다.After defining the active region, a side wall is formed to secure the device isolation region so that the isolation depth becomes smaller due to diffusion.
그러므로 누설전류의 발생을 억제하지 못한다.Therefore, the occurrence of leakage current cannot be suppressed.
그리고 소자 격리층 하부의 버즈빅(Bird's Beak) 현상에 의해 실제 활성영역이 줄어들게 되고, 또한 소자의 특성이 저하된다.In addition, due to the Bird's Beak phenomenon under the device isolation layer, the actual active area is reduced and the device characteristics are deteriorated.
본 발명은 상기와 같은 종래의 소자 격리막 형성공정의 문제점을 해결하기 위하여 안출된 것으로, 격리산화막의 버즈빅(Bird's Beak) 현상을 막고, 누설전류를 효율적으로 제어할 수 있는 트렌치를 이용한 소자 격리막 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the conventional device isolation film formation process as described above, forming a device isolation film using a trench that can prevent the Bird's Beak phenomenon of the isolation oxide film and efficiently control the leakage current. The purpose is to provide a method.
상기의 목적을 달성하기 위한 본 발명의 트렌치를 이용한 소자 격리막 형성방법은 반도체 기판에 제1 산화막, 질화막을 차례로 증착하고, 상기 질화막층을 포토리소그래피 공정으로 선택적으로 제거하여 소자격리 영역을 정의하는 공정과, 상기 질화막층이 형성된 상기 소자격리 영역의 반도체 기판에 건식각(Dry Etch)으로 트렌치를 형성하는 공정과, 전면에 제2 산화막을 증착하고 에치백하여 트렌치 측면에 측벽을 형성하는 공정과, 상기 측벽이 형성된 트렌치 하부영역을 습식식각으로 넓혀 충분한 소자격리 영역을 확보하는 공정과, 상기 확장면 트렌치 하부영역에 열산화막을 성장시키고, 상기 트렌치 영역을 포함하는 전면에 충분히 두꺼운 제3 산화막층을 형성하는 공정과, 상기 제3 산화막층은 활성영역에 남아 있는 질화막과 동일 높이로 식각한 후, 상기 질화막을 제거하는 공정과, 상기 반도체 기판의 표면에 돌출되어 있는 제 1, 2, 3 산화막을 에치백 하여 소자 격리층을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.A device isolation film forming method using a trench of the present invention for achieving the above object is a step of defining a device isolation region by sequentially depositing a first oxide film, a nitride film on a semiconductor substrate, and selectively removing the nitride film layer by a photolithography process. And forming a trench in the semiconductor substrate in the device isolation region in which the nitride layer is formed by dry etching, depositing and etching back a second oxide layer on the entire surface, and forming sidewalls on the sidewalls of the trench; Widening the trench lower region in which the sidewalls are formed by wet etching to secure a sufficient device isolation region; and growing a thermal oxide film in the extended trench lower region, and forming a sufficiently thick third oxide layer on the entire surface including the trench region. And the third oxide layer is etched at the same height as the nitride layer remaining in the active region. Characterized the yirueojim, including the step of the step of removing the nitride film by etching back the first, second, and third oxide layer which protrude on the surface of the semiconductor substrate to form a device isolation layer.
이하, 첨부된 도면을 참고하여 본 발명의 트렌치를 이용한 소자 격리막 형성방법에 대하여 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a device isolation layer using a trench of the present invention will be described in detail with reference to the accompanying drawings.
제2도 (a) 내지 (k)는 본 발명의 소자 격리층 형성을 위한 공정단면도이다.2 (a) to (k) are process cross-sectional views for forming a device isolation layer of the present invention.
본 발명은 소자 격리층을 형성하기 위한 트렌치의 내부에 산화막에 의한 측벽을 형성하여 버즈빅 현상의 발생을 억제한 것으로, 먼저, 제2도 (a)에서와 같이, 반도체 기판(20) 상에 제1 산화막(21), 질화막(22)을 차례로 증착하고, 제2도(b)에서와 같이, 포토리소그래피 공정으로 상기 질화막(22)을 선택적으로 제거하여 소자격리 영역을 정의한다.According to the present invention, the sidewalls formed by the oxide film are formed inside the trench for forming the device isolation layer, thereby suppressing the occurrence of the buzz big phenomenon. First, as shown in FIG. The first oxide film 21 and the nitride film 22 are sequentially deposited, and as illustrated in FIG. 2B, the nitride film 22 is selectively removed by a photolithography process to define an isolation region.
그리고 제2도 (c)(d)에서와 같이, 상기 질화막(22)이 제거된 소자격리 영역의 반도체 기판(20)을 건식각(Dry Etch) 하여 트렌치(Trench)를 형성하고 전면에 제2 산화막을 형성한다.As shown in FIG. 2 (c) (d), a trench is formed by dry etching the semiconductor substrate 20 in the device isolation region from which the nitride layer 22 is removed to form a trench, and to form a trench on the front surface thereof. An oxide film is formed.
이어, 제2도(e)에서와 갈이, 상기 제2 산화막(23)을 에치백(Eteh Back) 하여 상기 트렌치 측면에 트렌치 측벽(Trench Side Wall)(24)을 형성한다.Next, as shown in FIG. 2E, the second oxide layer 23 is etched back to form a trench side wall 24 on the side of the trench.
그리고 제2도 (f)(g)에서와 같이, 상기 트렌치 하부영역을 습식식각으로 확장시키고, 상기 확장된 트랜치 하부영역에 열산화 공정으로 열산화막(25)을 형성한다.As shown in FIG. 2 (f) (g), the lower trench region is expanded by wet etching, and a thermal oxide layer 25 is formed in the extended trench lower region by a thermal oxidation process.
이어, 제2도 (h)에서와 같이, 상기 트렌치 영역을 포함하는 전면에 충분히 두꺼운 제3 산화막(26)을 형성하고, 제2도 (i)(j)에서와 같이, 상기 제3 산화막(26)을 활성영역에 남아 있는 질화막(22)과 동일 높이로 식각한 후, 상기 질화막(22)을 제거한다.Subsequently, as shown in FIG. 2 (h), a sufficiently thick third oxide film 26 is formed on the entire surface including the trench region, and as shown in FIG. 2 (i) (j), the third oxide film ( 26) is etched at the same height as the nitride film 22 remaining in the active region, and then the nitride film 22 is removed.
그리고 제2도 (k)에서와 같이, 상기 반도체 기판(20)의 표면에 돌출되어 있는 제1, 2, 3 산화막(21)(23)(26)을 에치백 하여 소자 격리막을 형성한다.As shown in FIG. 2 (k), the device isolation film is formed by etching back the first, second and third oxide films 21, 23 and 26 which protrude from the surface of the semiconductor substrate 20. FIG.
상기와 같은 본 발명의 트렌치를 이용한 소자 격리막 형성방법은 소자 격리막을 형성시키기 위한 트랜치의 깊이가 커져 효율적으로(누설전류의 차단) 소자를 격리시킬 수 있으며, 최초로 정의된 소자격리 영역보다 확장된 소자 격리층을 형성할 수 있게 된다.The device isolation film forming method using the trench of the present invention as described above can increase the depth of the trench for forming the device isolation film to isolate the device efficiently (blocking leakage current), and extend the device than the first defined device isolation region It is possible to form an isolation layer.
그리고 트렌치 하부영역에 열산화막을 성장시키므로 기판에 주는 손상을 줄이고, 버즈빅 현상의 발생을 억제하므로 소자의 특성을 향상시킬 수 있다.In addition, the thermal oxide film is grown in the lower region of the trench, thereby reducing damage to the substrate and suppressing the occurrence of the buzz big phenomenon, thereby improving device characteristics.
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| KR1019950058887A KR100198620B1 (en) | 1995-12-27 | 1995-12-27 | Manufacturing method of isolation film using trench |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR19990073644A (en) * | 1998-03-02 | 1999-10-05 | 김영환 | Manufacturing Method of Semiconductor Device |
| KR100469763B1 (en) * | 2003-02-03 | 2005-02-02 | 매그나칩 반도체 유한회사 | Method for forming isolation of semiconductor device |
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| KR100319625B1 (en) * | 1999-05-28 | 2002-01-05 | 김영환 | Fabricating method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990073644A (en) * | 1998-03-02 | 1999-10-05 | 김영환 | Manufacturing Method of Semiconductor Device |
| KR100469763B1 (en) * | 2003-02-03 | 2005-02-02 | 매그나칩 반도체 유한회사 | Method for forming isolation of semiconductor device |
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