KR0156149B1 - Method of forming isolation area of semiconductor device - Google Patents
Method of forming isolation area of semiconductor device Download PDFInfo
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- KR0156149B1 KR0156149B1 KR1019950020363A KR19950020363A KR0156149B1 KR 0156149 B1 KR0156149 B1 KR 0156149B1 KR 1019950020363 A KR1019950020363 A KR 1019950020363A KR 19950020363 A KR19950020363 A KR 19950020363A KR 0156149 B1 KR0156149 B1 KR 0156149B1
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- insulating film
- forming
- semiconductor device
- film
- device isolation
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- 238000002955 isolation Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims 1
- 241000293849 Cordylanthus Species 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
본 발명은 반도체 소자 격리영역형성에 관한 것으로, 특히 필드산화막 형성시 발생되는 버즈믹(Bird's Beak)현상을 제거하여 고집적 반도체 소자의 격리에 적합하도록 한 반도체 소자 격리영역 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of semiconductor device isolation regions, and more particularly, to a method of forming a semiconductor device isolation region suitable for isolation of highly integrated semiconductor devices by eliminating the Bird's Beak phenomenon generated during field oxide film formation.
본 발명의 반도체 소자격리영역 형성방법은 기판상에 제1절연막과 제2절연막을 차례로 형성하는 공정, 상기 제2절연막을 선택적으로 제거하여 액티브영역에만 남도록 패터닝하는 공정, 상기 액티브영역이외의 격리영역에 필드 이온주입을 하는 공정, 상기 전면에 제3절연막을 형성하는 공정, 상기 제3절연막을 에치백하는 공정, 상기 제2, 제3절연막을 마스크로 이용하여 상기 제1절연막을 식각하는 공정, 상기 노출된 기판에 필드산화막을 형성함을 특징으로 한다.The method of forming a semiconductor device isolation region of the present invention comprises the steps of sequentially forming a first insulating film and a second insulating film on a substrate, selectively removing the second insulating film and patterning the second insulating film so as to remain only in the active region, and an isolation region other than the active region. Forming a third insulating film on the entire surface; etching back the third insulating film; etching the first insulating film using the second and third insulating films as a mask; Forming a field oxide film on the exposed substrate.
Description
제1도는 종래의 소자격리영역 형성 공정단면도.1 is a cross-sectional view of a conventional device isolation region forming process.
제2도는 본 발명의 소자격리영역 형성 공정단면도.Figure 2 is a cross-sectional view of the device isolation region forming process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 기판 22, 23, 25 : 제1, 제2, 제3절연막21: substrate 22, 23, 25: first, second, third insulating film
24 : 감광막 23a : 제2절연막패턴24 photosensitive film 23a second insulating film pattern
24a : 감광막패턴 25a : 측벽스페이서24a: photosensitive film pattern 25a: sidewall spacer
26 : 필드산화막 27 : 이온주입후 생긴 정선26: field oxide film 27: selection line after ion implantation
본 발명은 반도체 소자격리영역 형성에 관한 것으로, 특히 필드산화막 형성시 발생되는 버즈 빅(Bird's Beak)현상을 제거하여 고집적 반도체 소자의 격리에 적합하도록 한 반도체 소자격리영역 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of semiconductor device isolation regions, and more particularly, to a method of forming a semiconductor device isolation region suitable for isolation of highly integrated semiconductor devices by removing the Bird's Beak phenomenon generated during field oxide film formation.
이하, 첨부된 도면을 참조하여 종래의 기술을 설명하면 다음과 같다.Hereinafter, a conventional technology will be described with reference to the accompanying drawings.
제1도는 종래의 격리영역 형성 공정단면도로써, 먼저 제1도 (a)에서와 같이 기판(1)상에 산화막(2)과 질화막(3)을 차례로 성장과 증착한 후 감광막(4)를 도포한다.FIG. 1 is a cross-sectional view of a conventional isolation region forming process. First, as shown in FIG. do.
이어서 제1도 (b)에서와 같이 격리영역(필드영역)을 정의하기 위하여 노광 및 현상 공정을 통해 선택적으로 액티브(active) 영역에만 감광막이 남도록 패터닝한다.Subsequently, in order to define an isolation region (field region) as shown in FIG.
상기 패터닝된 감광막(4a)을 마스크로 이용하여 상기 절연막(3)을 선택적으로 식각하여 절연막 패턴(3a)을 형성한다.The insulating film 3 is selectively etched using the patterned photoresist 4a as a mask to form an insulating film pattern 3a.
이어서 상기 절연막 패턴(3a)을 마스크로 하여 채털스톱형성을 위한 이온 주입공정을 수행하여 노출된 기판(1)상에 불순물을 주입한 후 상기 남아있는 감광막패턴 (4a)을 제거한다.Subsequently, an ion implantation process for forming a hair stop is performed by using the insulating layer pattern 3a as a mask to implant impurities on the exposed substrate 1, and then the remaining photoresist layer pattern 4a is removed.
이어서 제1도 (c)에서와 같이 O2분위기에서 열처리를 행하여 소자분리를 위한 필드산화막(5)을 형성한다.Subsequently, as in FIG. 1 (c), heat treatment is performed in an O 2 atmosphere to form a field oxide film 5 for device isolation.
다음에 제1도 (d)에서와 같이 상기 절연막패턴(3a)을 제거하면 소자의 격리막(필드산화막)(5) 형성공정이 완료된다.Next, as shown in FIG. 1 (d), when the insulating film pattern 3a is removed, the process of forming the isolation film (field oxide film) 5 of the device is completed.
이때 필드산화막(5) 하단에는 이온 주입후 생긴 정선(6)이 형성된다.At this time, the line 6 formed after ion implantation is formed at the bottom of the field oxide film 5.
상기와 같이 종래의 소자격리형성방법에 있어서는 버즈빅(Bird's Beak)현상이 발생한다.As described above, in the conventional device isolation method, a bird's beak phenomenon occurs.
이는 열산화막 성장시 O2의 등방성 확산(Isotropic Diffusion)으로 인해 액티브(active)영역이 되어야 할 부분까지 열산화막이 성장되어 액티브(active) 영역의 감소를 초래하여 고집적회로에 적용할 경우 액티브(active) 영역을 정의할 수 없는 문제점이 있었다.This is due to the isotropic diffusion of O 2 during the growth of the thermal oxide film, which causes the thermal oxide film to grow to the active area, resulting in a reduction of the active area, and when applied to a high integrated circuit ) There was a problem that cannot define the area
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 버즈 빅(Bird's Beak) 현상을 방지하여 고집적회로에 적당하도록 하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to prevent a Bird's Beak phenomenon to be suitable for a high integrated circuit.
이와같은 목적을 달성하기 위한 본 발명의 반도체 소자격리영역 형성방법은 기판(21)상에 제1절연막(SiO2)(22)과 제2절연막(SiNx)(23)을 차례로 형성하여 상기 전노출면에 감광막(24)을 도포하는 공정과, 상기 감광막(24)을 노광 및 현상공정으로 액티브영역을 패터닝하는 공정, 상기 패터닝된 감광막(24a)을 마스크로 사용하여 제2절연막을 패터닝하는 공정, 상기 전면에 필드이온주입을 하는 공정, 상기 패터닝된 감광막(24a)을 제거하는 공정, 상기 전면에 제3절연막(SiNx)(25)을 증착하는 공정, 상기 제3절연막을 에치백하는 공정, 상기 노출된 제1절연막(SiO2)을 식각하는 공정, 상기 노출된 기판에 열산화막(26)을 형성하고 상기 남아있는 제2, 제3 절연막(23a)(25a)을 모두 삭각하는 공정을 포함하여 이루어짐을 특징으로 한다.In the semiconductor device isolation region forming method of the present invention for achieving the above object, the first insulating film (SiO 2 ) 22 and the second insulating film (SiNx) 23 are sequentially formed on the substrate 21 to expose the entire exposure. A process of applying the photoresist film 24 to the surface, a step of patterning the active region by the exposure and development process of the photoresist film 24, a process of patterning a second insulating film using the patterned photoresist film 24a as a mask, Performing field ion implantation on the front surface, removing the patterned photosensitive film 24a, depositing a third insulating film (SiNx) 25 on the front surface, etching back the third insulating film, and Etching the exposed first insulating film SiO 2 , forming a thermal oxide film 26 on the exposed substrate, and cutting off the remaining second and third insulating films 23a and 25a. Characterized in that made.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명의 소자격리영역 형성공정단면도로써, 먼저 제2도 (a)에서와 같이 기판(21)상에 제1절연막(SiO2)(22)과 제2절연막(23)(SiNx)을 차례로 성장과 증착을 한 후 상기 전면에 감광막(24)을 도포한다.FIG. 2 is a cross-sectional view of the device isolation region forming process according to the present invention. First, as shown in FIG. 2 (a), first insulating film SiO 2 and second insulating film 23 (SiNx) are formed on the substrate 21. After the growth and deposition in turn, the photosensitive film 24 is applied to the entire surface.
이어서 제2도 (b)에서와 같이 격리영역을 정의하기 위하여 노광 및 현상공정을 통해 선택적으로 액티브 영역에만 감광막(24a)이 남도록 패터닝한다.Subsequently, in order to define the isolation region as shown in FIG.
상기 남아있는 감광막(24a)을 마스크로 사용하여 상기 제2절연막(23)을 선택적으로 제거하여 제2절연막패턴(23a)을 형성한다.The second insulating layer 23 is selectively removed by using the remaining photoresist layer 24a as a mask to form a second insulating layer pattern 23a.
상기 패터닝된 제2절연막(23a)을 마스크로 하여 소자격리영역 하단에 채털스톱을 형성하기 위한 필드 이온주입공정을 수행하여 제2절연막 및 패턴에 의해 노출된 기판상에 필드이온주입을 한다.A field ion implantation process is performed to form a channel stop at the bottom of the device isolation region by using the patterned second insulating layer 23a as a mask to perform field ion implantation on a substrate exposed by the second insulating layer and the pattern.
이어서 상기 남아있는 감광막(24a)을 제거한다.Then, the remaining photosensitive film 24a is removed.
그 다음 제2도 (c)에서와 같이 상기 전면에 제3절연막(25)을 형성한 뒤 제2도 (d)에서와 같이 상기 제3절연막(25)을 에치 백(Etch Back)하여 상기 제2절연막 측벽에 측벽스페이서(25a)를 잔류시킨다.Next, as shown in FIG. 2 (c), a third insulating film 25 is formed on the entire surface, and the third insulating film 25 is etched back as shown in FIG. The sidewall spacers 25a are left on the sidewalls of the insulating film.
이어서 제2도 (e)에서와 같이 상기 제3절연막에 의해 노출된 부분의 제1절연막(SiO2)을 HF로 습식 식각한다.Subsequently, as shown in FIG. 2E, the first insulating layer SiO 2 of the portion exposed by the third insulating layer is wet-etched with HF.
이어서 제2도 (f)에서와 같이 O2분위기에서 열처리하여 소자분리를 위한 필드산화막(26)를 형성한 후 제2도 (g)에서와 같이 상기 남아있는 제2, 제3절연막(23a)(25a)을 모두 식각함으로써 소자의 격리막(필드산화막)(26) 형성공정이 완료된다.Subsequently, as shown in FIG. 2 (f), heat treatment is performed in an O 2 atmosphere to form a field oxide film 26 for device isolation, and the remaining second and third insulating films 23a as shown in FIG. By etching all of (25a), the process of forming the isolation film (field oxide film) 26 of the device is completed.
이때 필드산화막 하단에는 이온 주입후 생긴 정선(27)이 형성된다.At this time, a bottom line 27 formed after ion implantation is formed at the bottom of the field oxide film.
상기와 같이 설명한 본 발명의 소자격리형성방법에 있어서는 절연막측에 측벽절연막을 형성함으로써 열산화막 형성시 O2의 액티브영역에로의 환산(즉 lateral extent)을 막아 버즈빅(Bird's Beak)현상을 방지하여 반도체 소자의 고집적화에 따른 액티브영역을 증가시킬수 있는 효과가 있다.In the device isolation formation method of the present invention as described above, by forming a sidewall insulating film on the insulating film side, the conversion of O 2 into the active region (that is, the lateral extent) is prevented when the thermal oxide film is formed to prevent the Bird's Beak Therefore, there is an effect of increasing the active area due to the high integration of the semiconductor device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950020363A KR0156149B1 (en) | 1995-07-11 | 1995-07-11 | Method of forming isolation area of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950020363A KR0156149B1 (en) | 1995-07-11 | 1995-07-11 | Method of forming isolation area of semiconductor device |
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| KR970008475A KR970008475A (en) | 1997-02-24 |
| KR0156149B1 true KR0156149B1 (en) | 1998-12-01 |
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| KR1019950020363A KR0156149B1 (en) | 1995-07-11 | 1995-07-11 | Method of forming isolation area of semiconductor device |
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