KR0179147B1 - Forming method of contact hole in semiconductor device - Google Patents
Forming method of contact hole in semiconductor device Download PDFInfo
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- KR0179147B1 KR0179147B1 KR1019950025940A KR19950025940A KR0179147B1 KR 0179147 B1 KR0179147 B1 KR 0179147B1 KR 1019950025940 A KR1019950025940 A KR 1019950025940A KR 19950025940 A KR19950025940 A KR 19950025940A KR 0179147 B1 KR0179147 B1 KR 0179147B1
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- Prior art keywords
- contact hole
- forming
- semiconductor device
- bpsg film
- insulating layer
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 25
- 238000001039 wet etching Methods 0.000 claims abstract description 20
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000001312 dry etching Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- -1 phosphorus ions Chemical class 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007598 dipping method Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체장치의 콘택홀 형성방법에 관한 것으로, 반도체장치의 콘택홀 형성시 콘택홀이 형성되는 BPSG막에 이온을 주입함으로써 습식식각만으로 습식 및 건식식각을 함께 진행한 경우와 같은 효과를 얻을 수 있도록 한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and by implanting ions into a BPSG film in which a contact hole is formed when forming a contact hole in a semiconductor device, the same effects as when wet and dry etching are performed by wet etching alone are obtained. I would have to.
본 발명은 반도체기판위에 절연층을 형성하는 공정과, 상기 절연층에 선택적으로 불순물 이온을 주입하는 공정, 및 상기 불순물 이온이 주입된 절연층 부분을 선택적으로 습식식각하여 콘택홀을 형성하는 공정으로 이루어지는 반도체장치의 콘택홀 형성방법을 제공한다.The present invention provides a process of forming an insulating layer on a semiconductor substrate, selectively implanting impurity ions into the insulating layer, and selectively wet etching a portion of the insulating layer into which the impurity ions are implanted to form contact holes. A contact hole forming method of a semiconductor device is provided.
Description
제1도는 종래기술에 의한 반도체장치의 콘택홀 형성방법을 도시한 공정순서도.1 is a process flowchart showing a method for forming a contact hole in a semiconductor device according to the prior art.
제2도는 본 발명에 의한 반도체장치의 콘택흘 형성방법을 도시한 공정순서.2 is a process sequence showing the contact flow forming method of a semiconductor device according to the present invention.
제3도는 이온주입후의 습식식각에 의한 콘택홀의 스텝커버리지 개선 효과를 실험한 결과를 도시한 도면.3 is a diagram showing the results of experiments on the step coverage improvement effect of the contact hole by wet etching after ion implantation.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : LTO1: semiconductor substrate 2: LTO
3 : BPSG막 4 : 포토레지스트3: BPSG film 4: Photoresist
5 : 금속막5: metal film
본 발명은 반도체장치의 콘택홀 형성방법에 관한 것으로, 특히 반도체장치의 콘택흘 형성시 콘택홀이 형성되는 BPSG(Borophospho silicate glass)막에 이온을 주입함으로써 습식식각만으로 습식 및 건식식각을 함께 진행한 경우와 같은 효과를 얻을 수 있도록 한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and in particular, wet and dry etching are performed by wet etching only by implanting ions into a BPSG (Borophospho silicate glass) film in which a contact hole is formed when forming a contact hole of a semiconductor device. This is to achieve the same effect as the case.
종래기술에 의한 반도체장치의 콘택홀 형성방법을 제1도를 참조하여 설명하면 다음과 같다.A method for forming a contact hole in a semiconductor device according to the prior art will now be described with reference to FIG.
먼저, 제1도(a)에 도시된 바와 같이 반도체기판(1)위에 절연층으로서 LTO(Low Temperature Oxide)(2)를 형성하고 이위에 BPSG막(3)을 일정두께로 형성한 후, 포토레지스트(4)를 도포하고 이를 선택적으로 노광 및 현상하여 콘택홀 형성을 위한 포토레지스트패턴(4)을 형성한다.First, as shown in FIG. 1A, a low temperature oxide (LTO) 2 is formed as an insulating layer on the semiconductor substrate 1, and a BPSG film 3 is formed thereon to a predetermined thickness. The resist 4 is applied and selectively exposed and developed to form a photoresist pattern 4 for forming contact holes.
이어서 제1도(b)에 도시된 바와 같이 후속 공정인 금속 스퍼터링공정에서의 스텝 커버리지(step coverage)를 향상시키기 위해 먼저 상기 포토레지스트패턴을 마스크로 하여 상기 BPSG막(3)을 버퍼드 HF(buffered Hydrofluoric acid)로 일정두께 습식식각한다.Subsequently, in order to improve step coverage in a subsequent metal sputtering process as shown in FIG. 1 (b), first, the BPSG film 3 is buffered HF (using the photoresist pattern as a mask). Wet-etched to a certain thickness with buffered hydrofluoric acid.
다음에 제1도(c)에 도시된 바와 같이 콘택홀 형성영역에 잔존하는 BPSG막(3)을 건식식각하고 이에 따라 노출되는 LTO(2)를 식각함으로써 콘택홀을 형성한다.Next, as shown in FIG. 1C, the contact hole is formed by dry etching the BPSG film 3 remaining in the contact hole forming region and etching the exposed LTO 2.
이어서 제1도(d)에 도시된 바와 같이 상기 포토레지스트패턴을 제거한 후, 기판 전면에 금속막(5)을 스퍼터링에 의해 증착한다.Subsequently, after removing the photoresist pattern as shown in FIG. 1 (d), the metal film 5 is deposited on the entire surface of the substrate by sputtering.
상기한 종래기술에 있어서, 상기 BPSG막은 보론(boron)과 인(phosphorus)이 일정량 함유된 막이므로 습식식각시 그 식각속도가 일정하나, 포토레지스트와 BPSG막의 계면으로 식각용액이 침투하여 애스펙트비(aspect ratio)를 감소시킴에 따라 인접한 콘택홀과의 중첩이 발생하는 경우가 있기 때문에 습식식각에 의해 일정두께의 BPSG막을 제거한 다음에 건식식각을 행하여 콘택홀을 형성하였다.In the above conventional technique, since the BPSG film is a film containing a certain amount of boron and phosphorus, the etching rate is constant during wet etching, but the etching solution penetrates into the interface between the photoresist and the BPSG film, resulting in an aspect ratio ( As the aspect ratio is reduced, overlapping with adjacent contact holes may occur, so that the BPSG film having a predetermined thickness is removed by wet etching, followed by dry etching to form the contact hole.
따라서 습식식각만으로는 원하는 바대로 콘택흘을 형성할 수 없어 동일막질에 대해 습식식각과 건식식각을 병행하여 실시해야 하므로 식각시간이 증가하는등 공정상의 번거로움이 초래된다.Therefore, wet etching alone can not form a contact flow as desired, so wet etching and dry etching must be performed in parallel on the same film quality, resulting in process inconvenience such as an increase in etching time.
본 발명은 이와 같은 문제를 해결하기 위한 것으로, 습식식각만으로 콘택홀을 형성할 수 있는 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a contact hole by wet etching only.
상기 목적을 달성하기 위한 본 발명의 반도체장치의 콘택흘 형성방법은 반도체기판위에 절연층을 형성하는 공정과, 상기 절연층에 선택적으로 불순물 이온을 주입하는 공정, 및 상기 불순물 이온이 주입된 절연층 부분을 선택적으로 습식식각하여 콘택홀을 형성하는 공정으로 이루어진다.The contact flow forming method of the semiconductor device of the present invention for achieving the above object comprises the steps of forming an insulating layer on a semiconductor substrate, selectively implanting impurity ions into the insulating layer, and the insulating layer implanted with the impurity ions Selectively wet etching portions to form contact holes.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명에 의한 반도체장치의 콘택흘 형성방법을 공정순서에 따라 도시하였다.2 shows a contact flow forming method of a semiconductor device according to the present invention according to the process sequence.
먼저, 제2도(a)에 도시된 바와 갈이 반도체기판(1)위에 절연층으로서 LTO(Low Temperature Oxide)(2)와 BPSG막(3)을 일정두께로 차례로 형성한 후, 포토레지스트(4)를 도포하고 이를 선택적으로 노광 및 현상하여 콘택홀 형성을 위한 포토레지스트패턴(4)을 형성한 다음, 인(phosphorus) 이온을 상기 콘택홀 영역의 노출된 BPSG막(3)에 주입한다.First, a low temperature oxide (LTO) 2 and a BPSG film 3 are sequentially formed on the ground semiconductor substrate 1 as shown in FIG. 2A as an insulating layer, and then a photoresist ( 4) is applied and selectively exposed and developed to form a photoresist pattern 4 for forming contact holes, and then phosphorus ions are implanted into the exposed BPSG film 3 in the contact hole region.
이어서 제2도(b)에 도시된 바와 같이 상기 포토레지스트패턴을 마스크로 하여 상기 이온이 주입된 BPSG막(3)을 버퍼드 HF(buffered Hydrofluoric acid)로 습식식각한다. 이때, 콘택홀이 형성될 영역의 BPSG막에 인(P) 이온을 주입한 후 습식식각을 행하므로 이온이 주입된 부분의 식각속도가 향상되어 애스팩트비가 감소되는 일없이 습식식각만으로 BPSG막을 식각할 수 있으며, 이온주입량 및 에너지를 조절함으로써 식각시간을 조절하는 것이 가능하게 된다. 또한, 식각된 BPSG막의 표면이 곡선형태를 가지게 됨에 따라 후속의 금속 스퍼터링공정시 스텝 커버리지가 향상된다.Subsequently, as shown in FIG. 2B, the BPSG film 3 into which the ions are implanted is wet-etched with buffered hydrofluoric acid (HF) using the photoresist pattern as a mask. At this time, the phosphorus (P) ion is implanted into the BPSG film in the region where the contact hole is to be formed, and then wet etching is performed, thereby improving the etching rate of the implanted portion, thereby etching the BPSG film by wet etching alone without reducing the aspect ratio. It is possible to control the etching time by adjusting the ion implantation amount and energy. In addition, as the surface of the etched BPSG film has a curved shape, step coverage is improved in a subsequent metal sputtering process.
다음에 제2도(c)에 도시된 바와 같이 BPSG막(3)의 식각에 따라 노출되는 LTO(2)를 건식식각함으로써 콘택홀을 형성한다.Next, as shown in FIG. 2C, a contact hole is formed by dry etching the LTO 2 exposed by the etching of the BPSG film 3.
이어서 제2도(d)에 도시된 바와 같이 상기 포토레지스트패턴을 제거한 후, 기판 전면에 금속막(5)을 스퍼터링에 의해 증착한다.Subsequently, the photoresist pattern is removed, as shown in FIG.
제3도는 이온주입후의 습식식각에 의한 콘택홀의 스텝커버리지 개선 효과를 실험한 결과를 나타낸 것으로, 제3도(a)는 BPSG막(3)에 이온주입을 행하지 않고 20:1의 BOE(Buffered Oxide Etchant)에 8분간 디핑(dipping)한 경우를 나타낸 것이고, 제3도(b)는 BPSG막(3)에 인 이온을 도우즈량 5.0×1015주입에너지 100eV 조건으로 주입한 후, 20:1의 BOE에 8분간 디핑한 경우를 나타낸 것으로, 이온주입후 습식식각을 행한 제3도(b)의 경우가 스텝커버리지가 향상된 결과를 나타내는 것을 알 수 있다.FIG. 3 shows the results of experiments on the step coverage improvement effect of the contact hole by wet etching after ion implantation. FIG. 3 (a) shows a BOE (Buffered Oxide) of 20: 1 without ion implantation into the BPSG film 3. 8 minutes of dipping (Etchant), and FIG. 3 (b) shows that the phosphorus ion is injected into the BPSG film 3 at a dose of 5.0 × 10 15 implantation energy of 100 eV and then 20: 1 In the case of dipping into BOE for 8 minutes, it can be seen that the step coverage (b) of wet etching after ion implantation shows an improved step coverage.
이와 같이 본 발명에 의하면, 습식식각만으로 콘택홀 형성을 위한 BPSG막의 식각을 행할 수 있으며, 식각속도를 향상시킬 수 있다.As described above, according to the present invention, the BPSG film for forming the contact hole can be etched only by wet etching, and the etching rate can be improved.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950025940A KR0179147B1 (en) | 1995-08-22 | 1995-08-22 | Forming method of contact hole in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950025940A KR0179147B1 (en) | 1995-08-22 | 1995-08-22 | Forming method of contact hole in semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR970013039A KR970013039A (en) | 1997-03-29 |
| KR0179147B1 true KR0179147B1 (en) | 1999-04-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950025940A KR0179147B1 (en) | 1995-08-22 | 1995-08-22 | Forming method of contact hole in semiconductor device |
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| KR (1) | KR0179147B1 (en) |
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1995
- 1995-08-22 KR KR1019950025940A patent/KR0179147B1/en not_active IP Right Cessation
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