KR960003001B1 - Fabrication method of mask rom in semiconductor device - Google Patents

Fabrication method of mask rom in semiconductor device Download PDF

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Publication number
KR960003001B1
KR960003001B1 KR1019920014982A KR920014982A KR960003001B1 KR 960003001 B1 KR960003001 B1 KR 960003001B1 KR 1019920014982 A KR1019920014982 A KR 1019920014982A KR 920014982 A KR920014982 A KR 920014982A KR 960003001 B1 KR960003001 B1 KR 960003001B1
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South Korea
Prior art keywords
film
gate
forming
lto
bpsg
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KR1019920014982A
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Korean (ko)
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KR940004810A (en
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이병일
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금성일렉트론주식회사
문정환
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Priority to KR1019920014982A priority Critical patent/KR960003001B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

forming a gate oxide film(3) and a gate(4) in a channel region on a substrate(1) in turn, and forming a source/drain region(6) by selective ion implantation; depositing a BPSG film(8) over the surface, and forming a LTO film(8) of 1,000 angstrom over the surface after patterning a metal(9) on the source/drain region(6); forming a selective photosensitive film(12) according to data of an user, and preventing the exposure of the gate by dry-etching the LTO film(11) and the BPSG film(8) of the gate(4) region using the photosensitive film(12) as mask; carrying out an ROM coding after exposing the gate(4) surface by removing the LTO film(11) and the BPSG film(8) positioned at inside of the metal(9). The method can reduce demage of the silicon substrate and a turn around time(TAT).

Description

반도체 장치의 마스크롬 제조방법Method for manufacturing mask ROM of semiconductor device

제1도는 종래 마스크롬 제조의 일실시예를 설명하기 위한 단면도.1 is a cross-sectional view for explaining an embodiment of the conventional mask rom production.

제2도는 종래 마스크롬 제조의 다른 실시예를 설명하기 위한 공정단면도.Figure 2 is a cross-sectional view for explaining another embodiment of the conventional mask rom production.

제3도는 본 발명 마스크롬 제조의 일실시예를 설명하기 위한 공정단면도.Figure 3 is a process cross-sectional view for explaining an embodiment of the present invention manufacturing a mask.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 필드산화막1 substrate 2 field oxide film

3 : 게이트 산화막 4,5 : 게이트3: gate oxide film 4,5 gate

6 : 소오스/드레인 8 : BPSG막6 source / drain 8 BPSG film

9 : 금속 11 : LTO막9: metal 11: LTO film

7,10,12 : 감광막7,10,12: photoresist

본 발명은 반도체 장치(Semiconductor Device)의 마스크롬(Mask Read Only Memory)에 관한 것으로, 특히 TAT(Turn Around Time)를 줄일 수 있는 반도체 장치의 마스크롬 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask rom of a semiconductor device, and more particularly to a method of manufacturing a mask rom of a semiconductor device capable of reducing TAT (Turn Around Time).

종래의 마스크롬 제조의 일실시예는 제1도와 같은 기판(규소)(1) 상부에 필드산화막(Field Oxide)(2)을 성장 패터닝(Patterning)하여 소자 영역과 격리영역을 정의하고, 전표면에 게이트 산화막(3)을 성장한 후 게이트(다결정 규소)(5)를 패터닝 하여 형성한다.According to an exemplary embodiment of the conventional mask rom fabrication, a pattern of a field oxide film 2 is grown and patterned on a substrate (silicon) 1 as shown in FIG. 1 to define a device region and an isolation region. After the gate oxide film 3 is grown, the gate (polycrystalline silicon) 5 is patterned.

다음, 이온을 주입하여 소오스/드레인(6)을 형성하고, BPSG(Boron Phosphous Silicate Glass)막을 형성하기 전에 수요자의 Data 내용에 따라 감광막(7)을 이용하여 선택적으로 롬코드 이온을 주입한다.Next, ions are implanted to form the source / drain 6, and before the formation of the BPSG (Boron Phosphous Silicate Glass) film, the romcode ions are selectively implanted using the photosensitive film 7 according to the data content of the consumer.

종래 마스크롬 제조의 다른 실시예는 제2a도와 같이 기판(1) 상부에 필드산화막(2)을 성장하는 공정부터 소오스/드레인(6)을 형성하는 공정까지는 제1도와 같고, 전표면에 BPSG막(8)을 증착한 후 소오스/드레인(6) 영역의 표면에 금속(9)을 패터닝하고, 수요자의 Data 내용에 따라 감광막(10)을 형성하고 a도와 같이 아주 높은 에너지로 이온을 주입하여 롬코드화 하거나 b도와 같이 감광막(10)을 마스크로 하여 BPSG막(8)선택적으로 제거하고 이온을 주입하여 롬코드화 한다.Another embodiment of the conventional mask rom fabrication is as shown in FIG. 2A, from the process of growing the field oxide film 2 on the substrate 1 to the process of forming the source / drain 6, and the BPSG film on the entire surface. (8) and then patterning the metal (9) on the surface of the source / drain (6) region, forming a photosensitive film 10 according to the data content of the consumer and injecting ions with very high energy as shown in a Coded or bPSG film 8 is selectively removed using photosensitive film 10 as a mask as shown in FIG.

그러나, 이와 같은 종래의 기술에 있어서는 다음과 같은 결점이 있다.However, this conventional technique has the following drawbacks.

첫째, 제1도의 경우 롬코드화 후의 공정이 길기 때문에 TAT를 단축하기가 어렵다.First, in the case of FIG. 1, it is difficult to shorten the TAT since the process after romcoding is long.

둘째, 제2a도의 경우 높은 에너지로 이온을 주입하기 위한 고가의 이온주입기가 필요하다.Secondly, in FIG. 2a, an expensive ion implanter is needed to implant ions with high energy.

셋째, 제2b도에서 BPSG막(8)을 제거할 때, 기판(1)의 손상(Damage)을 방지하기 위해 건식(Dry) 및 습식(Wet) 식각을 하므로써 습식 식각시 BPSG막(8)의 내측이 일부 제거되어 빈공간이 발생하므로 신뢰성이 저하된다.Third, when the BPSG film 8 is removed in FIG. 2B, dry and wet etching are performed to wet the BPSG film 8 in order to prevent damage of the substrate 1. Part of the inner side is removed to create an empty space, thereby reducing the reliability.

본 발명은 이와 같은 종래의 결점을 감안하여 안출한 것으로, BPSG막의 내측으로의 식각(under cutting)을 방지하고 TAT 및 신뢰성을 개선할 수 있는 반도체 장치의 마스크롬 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and an object thereof is to provide a method for manufacturing a mask rom of a semiconductor device which can prevent under cutting of the BPSG film to the inside and improve TAT and reliability. .

이하에서 이와 같은 목적을 달성하기 위한 본 발명의 일실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter will be described in detail with reference to the accompanying drawings an embodiment of the present invention for achieving the above object.

제3도는 본 발명의 공정 단면도로, a도와 같이 기판(1)위에 필드 산화막(2), 게이트 산화막(3), 게이트(4), 소오스/드레인(6), BPSG막(8), 금속(9)을 형성하는 것은 종래의 제2도와 같고, 전표면에 화학증착법(Chemical Vapour Deposition)으로 LTO (Low Temperature Oxide Deposition) 막(11)을 약 1000옹스트롬(Angstrom) 정도의 두께만큼 형성한다.3 is a cross-sectional view of a process of the present invention, in which a field oxide film 2, a gate oxide film 3, a gate 4, a source / drain 6, a BPSG film 8, a metal ( 9) is the same as that of the second conventional art, and the LTO (Low Temperature Oxide Deposition) film 11 is formed on the entire surface by a thickness of about 1000 Angstroms by chemical vapor deposition.

다음, b도와 같이 게이트(4) 영역을 제외한 표면에 감광막(12)을 패터닝하고, 감광막(12)을 마스크로 하여 게이트(4) 영역의 LTO막(11) 및 BPSG막(8)을 게이트(4) 드러나지 않도록 건식식각(Anisotropic Etch)한 후 c도와 같이 1000옹스트롬 두께만큼 습식 식각하여 금속(9) 내측의 LTO막(11)과 BPSG막(8)을 제거해서 게이트(4) 표면에 드러나도록 한다.Next, as shown in b, the photosensitive film 12 is patterned on the surface except for the gate 4 region, and the LTO film 11 and the BPSG film 8 in the gate 4 region are gated using the photosensitive film 12 as a mask. 4) Anisotropic etching is performed so as not to be exposed, and then wet etching by 1000 angstroms as shown in c to remove the LTO film 11 and the BPSG film 8 inside the metal 9 to be exposed on the surface of the gate 4. do.

이어서, 이온을 주입하여 롬코드화를 실시한다.Subsequently, ions are implanted to perform romcoding.

이상에서 설명한 바와 같이 본 발명은 전표면에 화학증착법으로 LTO막(11)을 형성한 후 감광막(12)을 이용하여 롬코드화를 위한 식각 공정을 하므로써 Si-기판의 손상을 줄이고, BPSG의 내부 식각을 방지할 수 있으며 롬코드 이온주입을 금속공정 뒤에 하므로 TAT 를 단축시킬 수 있다.As described above, the present invention forms the LTO film 11 on the entire surface by chemical vapor deposition and then reduces the damage of the Si-substrate by performing the etching process for the romcoding using the photosensitive film 12, and internal etching of the BPSG. And romcode ion implantation after the metal process can reduce the TAT.

Claims (1)

기판(1)위 채널 영역에 게이트 산화막(3), 게이트(4)를 차례로 형성하고, 선택적 이온주입으로 소오스/드레인(6)을 형성하는 단계와, 전표면에 BPSG막(8)을 증착하고, 소오스/드레인(6) 영역의 표면에 금속(9)을 패터닝 한 후 전표면에 LTO막(11)을 1000 옹스트롬의 두께 만큼 형성하는 단계와, 주문자의 data에 따른 선택적 감광막(12)을 형성하고, 이를 마스크로 하여 게이트(4) 영역의 LTO막(11) 및 BPSG막(8)을 건식 식각하여 게이트(4)가 드러나지 않도록 하는 단계와, 상기 감광막(12)을 마스크로 하여 습식 식각해서 금속(9) 내측의 LTO막(11)과 BPSG막(8)을 제거하여 게이트(4) 표면이 드러나도록 한 후 롬코드화 하는 단계를 차례로 실시하여 이루어지는 반도체 장치의 마스크롬 제조방법.Forming a gate oxide film 3 and a gate 4 in the channel region on the substrate 1, forming a source / drain 6 by selective ion implantation, and depositing a BPSG film 8 on the entire surface. Patterning the metal (9) on the surface of the source / drain (6) region, and then forming the LTO film 11 on the entire surface by a thickness of 1000 angstroms, and forming the selective photoresist film 12 according to the orderer's data. Dry etching the LTO film 11 and the BPSG film 8 in the region of the gate 4 so that the gate 4 is not exposed, and wet etching using the photosensitive film 12 as a mask. A method of manufacturing a mask rom in a semiconductor device, which is performed by sequentially removing the LTO film (11) and the BPSG film (8) inside the metal (9) to expose the surface of the gate (4), and then performing romcoding.
KR1019920014982A 1992-08-20 1992-08-20 Fabrication method of mask rom in semiconductor device KR960003001B1 (en)

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KR1019920014982A KR960003001B1 (en) 1992-08-20 1992-08-20 Fabrication method of mask rom in semiconductor device

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KR960003001B1 true KR960003001B1 (en) 1996-03-02

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