KR100203911B1 - Method of forming an element isolation region in a semiconductor device - Google Patents
Method of forming an element isolation region in a semiconductor device Download PDFInfo
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- KR100203911B1 KR100203911B1 KR1019960025714A KR19960025714A KR100203911B1 KR 100203911 B1 KR100203911 B1 KR 100203911B1 KR 1019960025714 A KR1019960025714 A KR 1019960025714A KR 19960025714 A KR19960025714 A KR 19960025714A KR 100203911 B1 KR100203911 B1 KR 100203911B1
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- 238000002955 isolation Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 239000011149 active material Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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Abstract
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 1차 게이트 전극을 질화막 하부에 형성하고 소자분리를 한 다음 필드 산화막을 성장시킨 후 게이트 전극을 형성함으로써, 소자 분리공정중 필드 산화막이 여러 단계에 걸쳐 제거됨으로 인해 필드 산화막의 활성영역과 접한 부위에서 필드 산화막의 양측면부가 하부로 단이져 턱이 형성되는 현상을 방지하는 반도체 소자의 소자분리막 형성 방법이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, by forming a primary gate electrode under a nitride film, separating a device, and then growing a field oxide film, and then forming a gate electrode. It is a method of forming a device isolation film of a semiconductor device to prevent the phenomenon that the jaw is formed by the both side portions of the field oxide film is lowered in the portion in contact with the active region of the field oxide film by being removed over.
Description
제1a도 내지 제1c도는 종래의 기술에 따른 필드 산화막과 활성영역 경계부에서 단이 형성되는 상태를 도시한 도면.1A to 1C are diagrams showing a state in which a stage is formed at a boundary between a field oxide film and an active region according to the prior art.
제2a도 내지 제2i도는 본 발명의 방법에 따른 반도체 소자의 소자 분리막 제조공정 단계를 도시한 단면도.2A to 2I are cross-sectional views illustrating a process of fabricating an isolation layer of a semiconductor device in accordance with the method of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 21 : 실리콘 기판 12, 27 : 필드 산화막11, 21: silicon substrate 12, 27: field oxide film
13, 22 : 게이트 산화막 14, 24 : 1차 질화막13, 22: gate oxide film 14, 24: primary nitride film
23 : 1차 게이트 전극 25 : 감광막23 primary gate electrode 25 photosensitive film
26 : 2차 질화막 26' : 질화막 스페이서26: secondary nitride film 26 ': nitride film spacer
28 : 2차 게이트 전극28: secondary gate electrode
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 특히 1차 게이트 전극을 질화막 하부에 형성하고 소자분리를 한 다음 필드 산화막을 성장시킨 후 게이트 전극을 형성함으로써, 소자 분리공정중 필드 산화막이 여러 단계에 걸쳐 제거됨으로 인해 필드 산화막의 활성영역과 접한 부위에서 필드 산화막의 양측면부가 하부로 단이 져 턱이 형성되는 현상을 방지하여 반도체 소자의 신뢰성을 향상시키는 반도체 소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, by forming a primary gate electrode under a nitride film, separating a device, growing a field oxide film, and then forming a gate electrode. The present invention relates to a method of forming a device isolation layer of a semiconductor device, which improves reliability of a semiconductor device by preventing a phenomenon in which both side portions of the field oxide film are stepped downward in a portion in contact with the active region of the field oxide film due to the step removal. .
일반적으로 고집적 반도체 소자를 형성하기 위해서는 소자분리막의 새부리모양(bird's beak)의 산화막이 액티브내에로 적게 치고 들어가야 하고, 또한 소자분리 산화막 형성후에도 게이트 산화막에 어떠한 악영향도 미치지 않아야한다.In general, in order to form a highly integrated semiconductor device, the bird's beak oxide film of the device isolation film needs to be squeezed into the active material, and the gate oxide film should not be adversely affected even after the device isolation oxide film is formed.
제1a도 내지 제1c도는 종래의 기술에 따른 소자분리막 제조공정단계의 일부를 도시한 단면도로서, 제1a도는 필드 산화막(12) 형성후의 상태를 도시한 단면도이고, 제1b도는 상부의 질화막(13)을 제거한 상태의 단면도이고, 제1c도는 게이트 산화막 성장후의 상태를 도시한 단면도이다.1A to 1C are cross-sectional views showing a part of a device isolation film manufacturing process step according to the prior art, and FIG. 1A is a cross-sectional view showing a state after the field oxide film 12 is formed, and FIG. 1B is a nitride film 13 of the upper portion. Fig. 1C is a cross sectional view showing the state after the gate oxide film growth.
상기 도시된 도면에서 알 수 있는 바와 같이, 게이트 산화막(12)성장후의 필드 산화막(12) 상태는 양측 단부 즉, 활성영역과의 인접 부에서는 필드 산화막(12)이 소정깊이 아래로 파여진 형태로 단이 져있다(제1c도의 A부).As can be seen in the figure shown above, the field oxide film 12 after the growth of the gate oxide film 12 is formed in a form in which the field oxide film 12 is dug down to a predetermined depth at both ends, that is, adjacent to the active region. The stage is cut (part A of Fig. 1c).
따라서 상기 종래기술에 따른 일반적인 반도체 소자분리막 제조방법에 있어서는, 필드 산화막(12) 성장후 게이트 형성까지 산화막이 제거되는 단계가 여러번 있음으로 인해 필드 산화막(12)의 활성영역 모서리 부분에서 단차가 형성되는, 예컨데 필드 산화막(12) 단부의 상부부위가 액티브영역보다 더 아래로 내려간 위치에서 형성되어 후공정인 게이트 산화막 형성시 소자분리 산화막과 액티브의 수직 단차 부분에서 게이트 산화막이 비정상적으로 성장하거나 또는 스트레스로 인해 질적 저하를 초래하게 되고, 이는 결국 반도체 소자의 신뢰성을 저하시키는 요인으로 작용하는 문제점이 있다.Therefore, in the method of manufacturing a conventional semiconductor device isolation film according to the related art, a step is formed at the corner of the active region of the field oxide film 12 because the oxide film is removed several times from the growth of the field oxide film 12 to the gate formation. For example, the upper portion of the end portion of the field oxide layer 12 is formed at a position lower than the active region so that when the gate oxide layer is formed later, the gate oxide layer may be abnormally grown or stressed at the vertical step portion of the device isolation oxide layer and the active layer. This results in a qualitative deterioration, which in turn has a problem of acting as a factor that lowers the reliability of the semiconductor device.
따라서 본 발명은 상기의 문제점을 해결하기 위한 것으로, 본 발명의 목적은 1차 게이트 전극을 질화막 하부에 형성하고 소자분리를 한 다음 필드 산화막을 성장시킨 후 게이트 전극을 형성함으로써, 소자 분리공정중 필드 산화막이 여러 단계에 걸쳐 제거됨으로 인해 필드 산화막의 활성영역과 접한 부위에서 필드 산화막의 양측면부가 하부로 단이져 턱이 형성되는 현상을 방지하여 반도체 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 소자분리학 형성방법을 제공함에 있다.Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to form a gate electrode after forming a primary gate electrode under a nitride film, separating a device, and then growing a field oxide film. Device isolation of semiconductor devices that can improve the reliability of semiconductor devices by preventing the formation of jaws due to both side portions of the field oxide films being lowered in the areas in contact with the active region of the field oxide films due to the removal of the oxide films in several steps. It is to provide a formation method.
상기 목적을 달성하기 위한 본 발명에 의하면, 실리콘 기판 상부에 게이트 산화막, 1차 게이트 전극, 1차 질화막을 차례로 상부에 형성하는 단계와, 소자분리용 마스크를 사용하여 상기 1차 질화막 상부에 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 식각 마스크로 하여 그 하부의 1차 질화막, 1차 게이트 전극, 게이트 산화막을 차례로 식각하는 단계와, 상부의 감광막을 제거하는 단계와, 상기 1차 게이트 전극의 측벽을 일정두께 산화시키는 단계와, 상기 산화에 의해 형성된 산화막을 식각하여 하부의 실리콘 기판 상부면이 노출되게 하는 단계와, 전체구조 상부에 소정두께의 2차 질화막을 형성하는 단계와 상기 2차 질화막을 식각하여 상기 산화막과 1차 질화막의 양측벽에 걸쳐지는 질화막 스페이서를 형성하는 단계와, 필드 산화막을 성장시키는 단계와 상기제2질화막 스페이서를 제거하는 단계와, 전체구조 상부에 2차 게이트 전극을 형성하는 단계로 구성되는 것을 특징으로 한다.According to the present invention for achieving the above object, a step of forming a gate oxide film, a primary gate electrode, a primary nitride film on the silicon substrate in order, and using a device isolation mask, the photoresist film pattern on the primary nitride film Forming a photoresist pattern, etching the lower first nitride film, the first gate electrode, and the gate oxide film, using the photoresist pattern as an etch mask, removing the upper photoresist film, and Oxidizing the sidewalls to a predetermined thickness, etching the oxide film formed by the oxidation to expose a lower silicon substrate upper surface, forming a second nitride film having a predetermined thickness on the entire structure, and the second nitride film Etching to form nitride spacers that extend across both sidewalls of the oxide layer and the primary nitride layer; Step and the second is characterized in that consisting of the step of removing the second nitride film and the spacer, forming a second gate electrode on the entire upper structure.
이하, 첨부된 도면을 참조하여 본 발명의 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a도 내지 제2i도는 본 발명의 방법에 따른 반도체 소자의 소자 분리 산화막 제조공정 단계를 도시한 단면도이다.2A to 2I are cross-sectional views illustrating the steps of fabricating an isolation oxide film of a semiconductor device according to the method of the present invention.
제2a도를 참조하면, 실리콘 기판(21) 상부에 게이트 산화막(22), 1차 게이트 전극(23), 1차 질화막(24)을 차례로 상부에 형성한후 소자분리용 마스크를 사용하여 감광막 패턴(25)을 형성한다.Referring to FIG. 2A, the gate oxide layer 22, the primary gate electrode 23, and the primary nitride layer 24 are sequentially formed on the silicon substrate 21, and then the photoresist pattern is formed using a device isolation mask. To form 25.
이때 상기 1차 게이트 전극(23)의 두께는 100Å∼1500Å로 하고, 1차 게이트 전극 형성물질은 산소와 반응이 가능한 물질로 한다.At this time, the thickness of the primary gate electrode 23 is 100 kPa to 1500 kPa, and the primary gate electrode forming material is a material capable of reacting with oxygen.
제2b도를 참조하면, 상기 감광막 패턴(25)을 식각 마스크로 하여 그 하부의 1차 질화막(24), 1차 게이트 전극(23), 게이트 산화막(22)을 순서대로 식각한 후, 상부의 감광막(25)을 제거한다.Referring to FIG. 2B, the first nitride film 24, the first gate electrode 23, and the gate oxide film 22 are sequentially etched using the photoresist pattern 25 as an etch mask, and then the upper portion of the photoresist pattern 25 is etched. The photosensitive film 25 is removed.
제2c도를 참조하면, 상기 1차 게이트 전극(23)의 측벽을 일정두께 산화시킨다.Referring to FIG. 2C, a sidewall of the primary gate electrode 23 is oxidized to a predetermined thickness.
이때, 상기 1차 게이트 전극(23)을 일정 두께 산화시킴으로써 도면에 도시된 바와같이 1차 게이트 전극(23)은 그길이가 짧아지게 된다. 즉 게이트 전극이 필드 산화막 밖에 존재하게 되므로(제2i도 참조) 상기 제1c도에 도시된 종래의 필드 산화막과는 달리 소자의 질적 저하를 막게된다.At this time, by oxidizing the primary gate electrode 23 by a predetermined thickness, the length of the primary gate electrode 23 is shortened as shown in the drawing. That is, since the gate electrode is outside the field oxide film (see also FIG. 2i), unlike the conventional field oxide film shown in FIG. 1c, the quality of the device is prevented.
상기 1차 게이트 전극의 산화되는 두께는 20Å∼1000Å로 하며, 상기 게이트 전극(23)의 산화속도는 하부의 실리콘보다 빠르다.The oxidized thickness of the primary gate electrode is 20 kPa to 1000 kPa, and the oxidation rate of the gate electrode 23 is faster than that of the lower silicon.
제2d도를 참조하면, 상기 형성된 산화막(25)을 식각하여 하부의 실리콘 기판(21)이 노출되게 한다.Referring to FIG. 2D, the formed oxide layer 25 is etched to expose the lower silicon substrate 21.
제2e도를 참조하면, 전체구조 상부에 소정두께의 2차 질화막(26)을 형성한다.Referring to FIG. 2E, a secondary nitride film 26 having a predetermined thickness is formed on the entire structure.
제2f도를 참조하면, 상기 2차 질화막(26)을 블랭킷 식각하여 산화막(25)과 1차 질화막(24)의 양측면에 걸쳐지는 질화막 스페이서(26')를 형성한다.Referring to FIG. 2F, the second nitride film 26 is blanket-etched to form nitride film spacers 26 ′ that extend across both sides of the oxide film 25 and the primary nitride film 24.
이때 질화막(26) 증착두께의 균일도 및 식각 균일도를 감안하여 상기 블랭킷 식각시 증착된 두께보다 과도하게 식각한다.At this time, in consideration of the uniformity and etching uniformity of the deposition thickness of the nitride layer 26, the etching is excessively more than the thickness deposited during the blanket etching.
제2g도를 참조하면, 노출된 실리콘 기판(21)을 산화시켜 필드산화막(27)을 형성한다.Referring to FIG. 2G, the exposed silicon substrate 21 is oxidized to form a field oxide film 27.
제2h도를 참조하면, 상부의 제2질화막 스페이서(26')를 제거한다.Referring to FIG. 2H, the upper second nitride film spacer 26 ′ is removed.
제2i도를 참조하면, 전체구조 상부에 2차 게이트 전극(28)을 형성한다.Referring to FIG. 2I, the secondary gate electrode 28 is formed on the entire structure.
이때, 상기 2차 게이트 전극(28)은 실리사이드 또는 폴리사이드로 형성한다.In this case, the secondary gate electrode 28 is formed of silicide or polyside.
이상 상기한 바와같은 본 발명의 방법에 따르면, 종래의 기술과는 달리 질화막(26) 제거후 게이트 도체를 형성하므로 하부의 산화막이 제거되어지는 단계가 없어 단차가 형성되는 현상을 방지할 수 있다.According to the method of the present invention as described above, unlike the prior art, since the gate conductor is formed after the nitride film 26 is removed, there is no step in which the lower oxide film is removed, thereby preventing a phenomenon in which a step is formed.
따라서 상기한 본 발명의 방법에 의해 필드 산화막의 활성영역과의 경계부에 위치한 모서리부가 단이 지는 현상이 없어져 결국 반도체 소자의 제조수율 및 신뢰성을 향상시킬 수 있고, 또한 질화막 제거후 게이트 전극을 형성하므로 공정의 단순화를 기할 수 있다.Therefore, the above-described method of the present invention eliminates the phenomenon that the edge portion located at the boundary with the active region of the field oxide film is shortened, thereby improving the manufacturing yield and reliability of the semiconductor device, and also forming the gate electrode after removing the nitride film. The process can be simplified.
Claims (5)
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| KR1019960025714A KR100203911B1 (en) | 1996-06-29 | 1996-06-29 | Method of forming an element isolation region in a semiconductor device |
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| KR1019960025714A KR100203911B1 (en) | 1996-06-29 | 1996-06-29 | Method of forming an element isolation region in a semiconductor device |
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