TWI691000B - Semiconductor process - Google Patents
Semiconductor process Download PDFInfo
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- TWI691000B TWI691000B TW107142433A TW107142433A TWI691000B TW I691000 B TWI691000 B TW I691000B TW 107142433 A TW107142433 A TW 107142433A TW 107142433 A TW107142433 A TW 107142433A TW I691000 B TWI691000 B TW I691000B
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- 238000000034 method Methods 0.000 title claims abstract description 78
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 238000005468 ion implantation Methods 0.000 claims abstract description 33
- 230000004888 barrier function Effects 0.000 claims description 76
- 238000004519 manufacturing process Methods 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 6
- 238000005496 tempering Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000002019 doping agent Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 105
- 125000006850 spacer group Chemical group 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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Abstract
Description
本發明是有關於一種半導體製程,且特別是有關於一種可用於調整半導體元件的臨界電壓的半導體製程。The present invention relates to a semiconductor manufacturing process, and in particular to a semiconductor manufacturing process that can be used to adjust the threshold voltage of a semiconductor device.
在邏輯產品中,對半導體元件常有不同臨界電壓(threshold voltage,Vt)的應用需求,如增加靜態隨機存取記憶體(static random-access memory,SRAM)或其他應用。一般常使用多片通道摻雜用光罩(channel doping mask)來對不同半導體元件的通道進行不同濃度的摻雜製程,進而製作出具有不同臨界電壓的多種半導體元件。然而,由於上述方法會增加光罩的數量以及製程複雜度,進而造成製造成本增加且製造周期變長。In logic products, there are often different threshold voltage (Vt) application requirements for semiconductor devices, such as adding static random-access memory (SRAM) or other applications. Generally, a multi-channel channel doping mask is used to dope a process of different concentrations of channels of different semiconductor devices, and then produce a variety of semiconductor devices with different threshold voltages. However, the above method increases the number of photomasks and the complexity of the manufacturing process, which in turn increases manufacturing costs and lengthens the manufacturing cycle.
本發明提供一種半導體製程,其可減少製程所需的光罩數量,進而可降低製造成本且可縮短製造周期。The invention provides a semiconductor manufacturing process, which can reduce the number of photomasks required in the manufacturing process, thereby reducing manufacturing cost and shortening manufacturing cycle.
本發明提出一種半導體製程,包括以下步驟。提供基底。基底包括主動區。在主動區中的基底上形成閘極。閘極與基底彼此隔離。在基底上形成阻擋層。阻擋層位在主動區中。在阻擋層與閘極之間具有間距。使用阻擋層作為罩幕,對基底進行傾斜角離子植入製程,而在閘極兩側的基底中形成口袋摻雜區(pocket region)。藉由阻擋層與閘極之間的間距,來調整傾斜角離子植入製程所形成的口袋摻雜區的摻雜濃度。The present invention provides a semiconductor manufacturing process, including the following steps. Provide a base. The substrate includes an active area. Gates are formed on the substrate in the active area. The gate and the substrate are isolated from each other. A barrier layer is formed on the substrate. The barrier layer is located in the active area. There is a gap between the barrier layer and the gate. Using the barrier layer as a mask, an oblique angle ion implantation process is performed on the substrate, and a pocket doped region is formed in the substrate on both sides of the gate. The doping concentration of the pocket doped region formed by the tilt angle ion implantation process is adjusted by the distance between the barrier layer and the gate electrode.
依照本發明的一實施例所述,在上述半導體製程中,阻擋層的材料例如是光阻、非晶碳、氮化矽、硼磷矽玻璃(BPSG)或其組合。According to an embodiment of the invention, in the above semiconductor process, the material of the barrier layer is, for example, photoresist, amorphous carbon, silicon nitride, borophosphosilicate glass (BPSG), or a combination thereof.
依照本發明的一實施例所述,在上述半導體製程中,阻擋層的上視圖案的線條可為實線狀或虛線狀。According to an embodiment of the invention, in the above-mentioned semiconductor manufacturing process, the line of the top-view pattern of the barrier layer may be solid or dashed.
依照本發明的一實施例所述,在上述半導體製程中,阻擋層的高度例如是閘極的高度的10倍以下。According to an embodiment of the invention, in the above semiconductor process, the height of the barrier layer is, for example, 10 times or less the height of the gate.
依照本發明的一實施例所述,在上述半導體製程中,阻擋層的寬度例如是閘極的長度的5倍以下。According to an embodiment of the present invention, in the above semiconductor manufacturing process, the width of the barrier layer is, for example, 5 times or less than the length of the gate.
依照本發明的一實施例所述,在上述半導體製程中,阻擋層與閘極之間的間距為閘極的長度的3倍以下。According to an embodiment of the present invention, in the above semiconductor manufacturing process, the distance between the barrier layer and the gate electrode is less than 3 times the length of the gate electrode.
依照本發明的一實施例所述,在上述半導體製程中,更包括在基底上形成圖案化罩幕層。圖案化罩幕層暴露出主動區。可使用圖案化罩幕層與阻擋層作為罩幕,對基底進行傾斜角離子植入製程,而在閘極兩側的基底中形成口袋摻雜區。According to an embodiment of the present invention, in the above semiconductor manufacturing process, it further includes forming a patterned mask layer on the substrate. The patterned mask curtain layer exposes the active area. The patterned mask layer and the barrier layer can be used as masks to perform an oblique angle ion implantation process on the substrate, and pocket doped regions are formed in the substrate on both sides of the gate.
依照本發明的一實施例所述,在上述半導體製程中,更可包括使用阻擋層作為罩幕,對基底進行離子植入製程,而在閘極兩側的基底中形成輕摻雜汲極(lightly doped drain,LDD)。According to an embodiment of the present invention, in the above semiconductor process, it may further include using a barrier layer as a mask to perform an ion implantation process on the substrate, and forming a lightly doped drain in the substrate on both sides of the gate ( lightly doped drain (LDD).
依照本發明的一實施例所述,在上述半導體製程中,用於形成輕摻雜汲極的離子植入製程的植入角度例如是小於用於形成的口袋摻雜區的傾斜角離子植入製程的植入角度。According to an embodiment of the present invention, in the semiconductor process described above, the implantation angle of the ion implantation process used to form the lightly doped drain is, for example, less than the inclined angle ion implantation used to form the pocket doped region The implantation angle of the process.
依照本發明的一實施例所述,在上述半導體製程中,更可包括對輕摻雜汲極進行回火製程。According to an embodiment of the invention, the above semiconductor process may further include a tempering process for the lightly doped drain.
基於上述,在本發明所提出的半導體製程中,藉由阻擋層與閘極之間的間距,來調整傾斜角離子植入製程所形成的口袋摻雜區的摻雜濃度。藉此,可利用口袋摻雜區的摻雜濃度來調整半導體元件的臨界電壓。如此一來,在需要製作出具有不同臨界電壓的半導體元件時,可利用同一片光罩形成不同半導體元件的不同臨界電壓,藉此可減少製程所需的光罩數量,進而可降低製造成本且可縮短製造周期。Based on the above, in the semiconductor process proposed by the present invention, the doping concentration of the pocket doped region formed by the tilt angle ion implantation process is adjusted by the distance between the barrier layer and the gate electrode. In this way, the doping concentration of the pocket doped region can be used to adjust the threshold voltage of the semiconductor device. In this way, when semiconductor devices with different threshold voltages need to be fabricated, the same piece of photomask can be used to form different threshold voltages for different semiconductor devices, thereby reducing the number of photomasks required in the manufacturing process, thereby reducing manufacturing costs and Can shorten the manufacturing cycle.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.
圖1A至圖1D為本發明一實施例的半導體製程的剖面圖。圖2A至圖2D為圖1A的上視圖。圖3為本發明一實施例在形成不同半導體元件的口袋摻雜區的步驟的上視圖。1A to 1D are cross-sectional views of a semiconductor manufacturing process according to an embodiment of the invention. 2A to 2D are top views of FIG. 1A. FIG. 3 is a top view of the step of forming pocket doped regions of different semiconductor devices according to an embodiment of the invention.
請參照圖1A、圖2A至圖2D,提供基底100。基底100可包括主動區AA。主動區AA可在第一方向D1上延伸。舉例來說,在基底100中可具有隔離結構102,且可藉由隔離結構102在基底100中定義出主動區AA。基底100例如是矽基底等半導體基底。Please refer to FIGS. 1A and 2A to 2D to provide a
接著,在主動區AA中的基底100上形成閘極104。閘極104的材料例如是摻雜多晶矽等導體材料。閘極104的形成方法例如是先在基底100上形成閘極材料層(未示出),再藉由微影製程與蝕刻製程對閘極材料層進行圖案化。閘極材料層的形成方法例如是化學氣相沉積法。此外,閘極104與基底100彼此隔離。舉例來說,可在閘極104與基底100之間形成介電層106,以將閘極104與基底100進行隔離。介電層106的材料例如是氧化矽等介電材料。Next, a
此外,閘極104可在第二方向D2上延伸(圖2A至圖2D),且第二方向D2相交於第一方向D1。在本實施例中,第二方向D2是以垂直於第一方向D1為例來進行說明,但本發明並不以此為限。在本實施例中,將閘極104的長度L定義為閘極104與主動區AA重疊的部分在第一方向D1上的長度。In addition, the
然後,在基底100上形成阻擋層108a,且更可在基底100上形成圖案化罩幕層108b。圖案化罩幕層108b可暴露出主動區AA。阻擋層108a位在主動區AA中。此外,阻擋層108a可沿著第二方向D2延伸至隔離結構102上(圖2A至圖2D)。阻擋層108a的高度HB例如是閘極104的高度HG的10倍以下,如1倍至10倍。阻擋層108a的寬度WB例如是閘極104的長度L的5倍以下。在阻擋層108a與閘極104之間具有間距S1。阻擋層108a與閘極104之間的間距S1為閘極104的長度L的3倍以下。Then, a
阻擋層108a與圖案化罩幕層108b可為單層結構或多層結構。阻擋層108a與圖案化罩幕層108b的材料例如是光阻、非晶碳、氮化矽、硼磷矽玻璃或其組合。舉例來說,阻擋層108a與圖案化罩幕層108b可以是材料為光阻的單層結構,但本發明並不以此為限。阻擋層108a與圖案化罩幕層108b可藉由相同製程所形成,但本發明並不以此為限。The
舉例來說,在阻擋層108a與圖案化罩幕層108b的材料為光阻的情況下,阻擋層108a與圖案化罩幕層108b可藉由進行微影製程而形成。For example, in the case where the materials of the
在阻擋層108a與圖案化罩幕層108b的材料包括非晶碳、氮化矽、硼磷矽玻璃或其組合的情況下,阻擋層108a與圖案化罩幕層108b的形成方法可包括以下步驟。首先,藉由沉積製程形成罩幕層(未示出)。罩幕層可為單層結構或多層結構。罩幕層的材料可包括非晶碳、氮化矽、硼磷矽玻璃或其組合。接著,藉由微影製程與蝕刻製程對罩幕層進行圖案化,而形成阻擋層108a與圖案化罩幕層108b。此外,在進行上述蝕刻製程之後,可依照製程需求來決定是否移除上述圖案化製程中所使用的圖案化光阻層。在不移除圖案化光阻層的情況下,圖案化光阻層可作為阻擋層108a與圖案化罩幕層108b的一部分。在此情況下,阻擋層108a與圖案化罩幕層108b的材料更可包括光阻。In the case where the materials of the
此外,在阻擋層108a的材料包括非晶碳、氮化矽、硼磷矽玻璃或其組合的情況下,可製作出具有較大高寬比(aspect ratio)的阻擋層108a,且不會產生倒塌的問題。In addition, in the case where the material of the
另外,阻擋層108a的佈局設計方法例如是自動布局設計或人工布局設計。在利用自動布局設計來形成阻擋層108a的佈局的情況下,可進一步降低製程複雜度。In addition, the layout design method of the
請參照圖2A與圖2C,阻擋層108a的上視圖案可環繞閘極104而形成環狀圖案,但本發明並不以此為限。如圖2B與圖2D所示,阻擋層108a的上視圖案亦可為位在閘極104的兩側的條狀圖案。此外,阻擋層108a的上視圖案的線條可為實線狀(圖2A與圖2B)或虛線狀(圖2C與圖2D)。2A and 2C, the top-view pattern of the
請參照圖1B,可使用阻擋層108a與圖案化罩幕層108b作為罩幕,對基底100進行傾斜角離子植入製程IP1,而在閘極104兩側的基底100中形成口袋摻雜區110。口袋摻雜區110可用來防止短通道效應(short channel effect)。口袋摻雜區110更可延伸至閘極104下方。此外,口袋摻雜區110可為P型摻雜區或N型摻雜區。在本實施例中,口袋摻雜區110是以P型摻雜區為例來進行說明。傾斜角離子植入製程IP1的植入角度可為15度至60度,如15度至45度。Referring to FIG. 1B, the
此外,藉由阻擋層108a與閘極104之間的間距S1,來調整傾斜角離子植入製程IP1所形成的口袋摻雜區110的摻雜濃度。在進行傾斜角離子植入製程IP1時,阻擋層108a的遮蔽效應(shield effect)會影響離子植入到基底100的摻雜濃度。此外,根據阻擋層108a與閘極104之間的間距S1的不同,對於摻雜濃度的影響也會有所不同。藉此,可利用口袋摻雜區110的摻雜濃度來調整半導體元件的臨界電壓。如此一來,在需要製作出具有不同臨界電壓的半導體元件時,可利用同一片光罩形成不同半導體元件的不同臨界電壓,藉此可減少製程所需的光罩數量,進而可降低製造成本且可縮短製造周期。In addition, the doping concentration of the pocket doped
請參照圖3,以形成半導體元件10、20、30的不同臨界電壓為例來進行說明。半導體元件10、20、30的閘極104可具有相同的長度L,但本發明並不以此為限。在一些實施例中,半導體元件10、20、30的閘極104亦可具有不同的長度L。半導體元件10中的阻擋層108a與閘極104之間的間距S1大於半導體元件20中的阻擋層108a與閘極104之間的間距S2,且在半導體元件30中不具有阻擋層108a。因此,在對基底100進行傾斜角離子植入製程IP1之後,半導體元件30中的口袋摻雜區310的摻雜濃度會大於半導體元件10中的口袋摻雜區110的摻雜濃度,且半導體元件10中的口袋摻雜區110的摻雜濃度會大於半導體元件20中的口袋摻雜區210的摻雜濃度。如此一來,半導體元件30的臨界電壓會大於半導體元件10的臨界電壓,且半導體元件10的臨界電壓會大於半導體元件20的臨界電壓。然而,本發明並不以此為限,只要是藉由本實施例的半導體製程來形成不同半導體元件的不同臨界電壓,即屬於本發明所保護的範圍。Please refer to FIG. 3 to illustrate the different threshold voltages for forming the
在一些實施例中,在阻擋層108a的高度HB越高的情況下,對於口袋摻雜區110的摻雜濃度的調整可具有更大的製程彈性。亦即,在阻擋層108a的高度HB越高的情況下,可以產生更多種臨界電壓的組合。此外,在阻擋層108a的上視圖案的線條為虛線狀的情況下,可藉由調整虛線的間隙尺寸而形成多種不同摻雜濃度的口袋摻雜區110,進而可產生多種臨界電壓。另外,藉由組合使用上視圖案的線條為實線狀與虛線狀的多種阻擋層108a,可形成更多種不同摻雜濃度的口袋摻雜區110,進而可產生更多種臨界電壓。In some embodiments, in the case that the height HB of the
請參照圖1C,可使用阻擋層108a與圖案化罩幕層108b作為罩幕,對基底100進行離子植入製程IP2,而在閘極104兩側的基底100中形成輕摻雜汲極112。在一些實施例中,「輕摻雜汲極(LDD)」亦可稱為「源極/汲極延伸區(source/drain extension,SDE)」)。輕摻雜汲極112可用來防止熱載子效應(hot carrier effect)。此外,輕摻雜汲極112可位在口袋摻雜區110中。輕摻雜汲極112可為N型摻雜區或P型摻雜區。在本實施例中,輕摻雜汲極112是以N型摻雜區為例來進行說明。用於形成輕摻雜汲極112的離子植入製程IP2的植入角度例如是小於用於形成的口袋摻雜區110的傾斜角離子植入製程IP1的植入角度。舉例來說,離子植入製程IP2的植入角度可為0度至7度。Referring to FIG. 1C, the
此外,如圖1C所示,在所選用的離子植入製程IP2的植入角度較小(如,0度)的情況下,可能會因為阻擋層108a的阻擋,而無法在阻擋層108a下方的基底100中形成輕摻雜汲極112,但本發明並不以此為限。在一些實施例中,即使離子植入製程IP2的植入角度為0度,所植入的離子亦有可能會因為撞擊而橫向擴散到阻擋層108a下方的基底100中,而在阻擋層108a下方的基底100中形成輕摻雜汲極112。此外,可藉由加大離子植入製程IP2的植入角度(如,7度),來防止無法在阻擋層108a下方的基底100中形成輕摻雜汲極112的情況。In addition, as shown in FIG. 1C, when the implantation angle of the selected ion implantation process IP2 is small (eg, 0 degrees), it may not be able to be below the
在本實施例中,雖然是先形成口袋摻雜區110,再形成輕摻雜汲極112,但本發明並不以此為限。在一些實施例中,亦可先形成輕摻雜汲極112,再形成口袋摻雜區110。In this embodiment, although the pocket doped
請參照圖1D,可移除阻擋層108a與圖案化罩幕層108b。阻擋層108a與圖案化罩幕層108b的移除方法可根據其材料來進行選擇,例如是乾式去光阻法(dry striping)、濕式去光阻法(wet striping)、乾式蝕刻法、濕式蝕刻法或其組合。1D, the
接著,可選擇性地對輕摻雜汲極112進行回火製程。回火製程可使得輕摻雜汲極112中的摻質擴散到阻擋層108a下方的基底100中,因此輕摻雜汲極112可延伸至阻擋層108a下方的基底100中。在本實施例中,在移除阻擋層108a與圖案化罩幕層108b之後,進行上述回火製程,但本發明並不以此為限。在一些實施例中,上述回火製程亦可與後續製程進行整合。此外,在所進行的離子植入製程IP2已在阻擋層108a下方的基底100中形成輕摻雜汲極112的情況下,可以不另外對輕摻雜汲極112進行回火製程。Then, the lightly doped
然後,可在閘極104的側壁上形成間隙壁114。間隙壁114可為單層結構或多層結構。間隙壁114的材料例如是氮化矽、氧化矽或其組合。間隙壁114的形成方法例如是先在閘極104上形成間隙壁材料層(未示出),再對間隙壁材料層進行回蝕刻製程。Then, a
此外,用以完成金氧半導體電晶體的後續製程為所屬技術領域具有通常知識者所週知,於此不再說明。在本實施例中,雖然半導體製程是以製作金氧半導體電晶體為例來進行說明,但本發明並不以此為限。只要半導體製程是藉由阻擋層與閘極之間的間距,來調整傾斜角離子植入製程所形成的口袋摻雜區的摻雜濃度以及半導體元件的臨界電壓,即屬於本發明所保護的範圍。In addition, the subsequent process for completing the metal oxide semiconductor transistor is well known to those skilled in the art and will not be described here. In this embodiment, although the semiconductor manufacturing process is described by taking the metal oxide semiconductor transistor as an example, the present invention is not limited thereto. As long as the semiconductor process is to adjust the doping concentration of the pocket doped region formed by the tilt angle ion implantation process and the critical voltage of the semiconductor device by the distance between the barrier layer and the gate electrode, it falls within the scope of the invention .
綜上所述,在上述實施例的半導體製程中,藉由阻擋層與閘極之間的間距,來調整傾斜角離子植入製程所形成的口袋摻雜區的摻雜濃度,藉此可調整半導體元件的臨界電壓。如此一來,在需要製作出具有不同臨界電壓的半導體元件時,可藉由同一片光罩形成不同半導體元件的不同臨界電壓,藉此可減少製程所需的光罩數量,進而可降低製造成本且可縮短製造周期。In summary, in the semiconductor manufacturing process of the above embodiment, the doping concentration of the pocket doping region formed by the tilt angle ion implantation process is adjusted by the distance between the barrier layer and the gate electrode, thereby adjusting The critical voltage of semiconductor devices. In this way, when semiconductor devices with different threshold voltages need to be manufactured, different threshold voltages of different semiconductor devices can be formed by the same piece of photomask, thereby reducing the number of photomasks required in the manufacturing process, and thereby reducing manufacturing costs And can shorten the manufacturing cycle.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.
10、20、30:半導體元件
100:基底
102:隔離結構
104:閘極
106:介電層
108a:阻擋層
108b:圖案化罩幕層
110、210、310:口袋摻雜區
112:輕摻雜汲極
114:間隙壁
AA:主動區
L:長度
HB、HG:高度
IP1:傾斜角離子植入製程
IP2:離子植入製程
S1、S2:間距
WB:寬度10, 20, 30: Semiconductor components
100: base
102: Isolation structure
104: Gate
106:
圖1A至圖1D為本發明一實施例的半導體製程的剖面圖。 圖2A至圖2D為圖1A的上視圖。 圖3為本發明一實施例在形成不同半導體元件的口袋摻雜區的步驟的上視圖。1A to 1D are cross-sectional views of a semiconductor manufacturing process according to an embodiment of the invention. 2A to 2D are top views of FIG. 1A. FIG. 3 is a top view of the step of forming pocket doped regions of different semiconductor devices according to an embodiment of the invention.
100:基底 100: base
102:隔離結構 102: Isolation structure
104:閘極 104: Gate
106:介電層 106: dielectric layer
108a:阻擋層 108a: barrier
108b:圖案化罩幕層 108b: patterned mask curtain layer
110:口袋摻雜區 110: pocket doped area
IP1:傾斜角離子植入製程 IP1: tilt angle ion implantation process
L:長度 L: length
HB、HG:高度 HB, HG: height
S1:間距 S1: pitch
WB:寬度 WB: width
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