KR100540332B1 - Method for fabricating pattern of semiconductor device - Google Patents

Method for fabricating pattern of semiconductor device Download PDF

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KR100540332B1
KR100540332B1 KR1020030101592A KR20030101592A KR100540332B1 KR 100540332 B1 KR100540332 B1 KR 100540332B1 KR 1020030101592 A KR1020030101592 A KR 1020030101592A KR 20030101592 A KR20030101592 A KR 20030101592A KR 100540332 B1 KR100540332 B1 KR 100540332B1
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pattern
forming
semiconductor device
ion implantation
channel
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KR1020030101592A
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Korean (ko)
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KR20050070956A (en
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고광영
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

본 발명은 반도체 소자를 형성하기 위해 마스크 작업시 최외곽의 패턴에 추가로 더미 패턴을 삽입하여 포토레지스트의 최외곽 패턴의 경사 발생을 방지하는 패턴 형성 방법에 관한 것이다.The present invention relates to a pattern forming method for preventing the occurrence of the inclination of the outermost pattern of the photoresist by inserting a dummy pattern in addition to the outermost pattern during the mask operation to form a semiconductor device.

본 발명의 반도체 소자의 패턴 형성 방법은 소정의 소자가 형성된 기판상에 LDMOS 소자의 채널을 형성하기 위한 실제 패턴 외부에 더미 패턴을 형성하는 단계; 및 상기 패턴을 이용하여 이온 주입하는 단계를 포함하여 이루어짐에 기술적 특징이 있다.The pattern forming method of the semiconductor device of the present invention comprises the steps of: forming a dummy pattern outside the actual pattern for forming a channel of the LDMOS device on a substrate on which a predetermined device is formed; And an ion implantation using the pattern.

따라서, 본 발명의 반도체 소자의 패턴 형성 방법은 패턴의 경사에 의해 발생하는 Vt 변화나 Gm 곡선의 왜곡이 생기는 것을 방지하는 효과가 있다.Therefore, the pattern formation method of the semiconductor element of this invention has the effect which prevents the Vt change and the distortion of the Gm curve which generate | occur | produce by the inclination of a pattern.

더미 패턴, 이온 주입Dummy pattern, ion implantation

Description

반도체 소자의 패턴 형성 방법{Method for fabricating pattern of semiconductor device} Method for fabricating pattern of semiconductor device             

도 1a 내지 도 1b는 종래기술에 의한 반도체 소자의 패턴 형성 방법의 공정 단면도.1A to 1B are cross-sectional views of a method for forming a pattern of a semiconductor device according to the prior art.

도 2a 내지 도 2b는 본 발명에 의한 반도체 소자의 패턴 형성 방법의 공정 단면도.2A to 2B are cross-sectional views of a method for forming a pattern of a semiconductor device according to the present invention.

본 발명은 반도체 소자의 패턴 형성 방법에 관한 것으로, 보다 자세하게는 LDMOS(Lateral Diffusion Metal Oxide Semiconductor, 이하 LDMOS) 소자의 채널 형성하기 위한 패터닝 공정시 포토레지스트 패턴의 최외곽에 더미 패턴을 추가로 형성하는 패턴 형성 방법에 관한 것이다.The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly, to further form a dummy pattern on the outermost side of a photoresist pattern during a patterning process for forming a channel of an LDMOS device. It relates to a pattern formation method.

반도체 소자를 형성하기 위해 박막층을 증착한 후, 상기 박막층을 식각하기 위한 패턴을 형성하게 되는데 이러한 공정은 세 가지 공정 중에 하나의 방법을 이 용한다.After depositing a thin film layer to form a semiconductor device, a pattern for etching the thin film layer is formed. This process uses one of three processes.

첫째, 포토리소그래피(Photolithography)는 반도체 웨이퍼 위에 감광 성질을 가지고 있는 포토레지스트(Photoresist)를 얇게 바른 후, 원하는 마스크 패턴을 올려 놓고 빛을 가하여 사진을 찍는 것과 같은 방법으로 회로를 구성한다. 회로선폭 0.2㎛ 이상의 회로를 형상화할 수 있어 현재 반도체 제조산업에서 반도체 칩생산에 사용하고 있다. First, in photolithography, a photoresist having a photosensitive property is applied thinly on a semiconductor wafer, and then a circuit is formed by taking a desired mask pattern and applying a light. Since circuits having a circuit line width of 0.2 μm or more can be shaped, they are currently used for semiconductor chip production in the semiconductor manufacturing industry.

둘째, 전자빔리소그라피(Eletron Beam Lithography)는 반도체 웨이퍼 위에 전자에 예민한 성질을 가지고 있는 레지스트(resist)를 얇게 바른 후, 원하는 패턴을 마스크 없이 직접 전자빔을 가하여 그림을 그리거나 글씨를 쓰는 것과 같은 방법으로 회로를 구성한다. 회로선폭 0.02㎛ 이하의 회로를 형상화할 수 있어 집적회로 개발을 위한 연구장비로 사용하고 있으나 속도가 매우 느린 단점으로 생산용 장비로는 사용하지 못하고 있다. 현재 이런 단점을 보완할 방법을 연구하여 개발중이다. Second, electron beam lithography is applied to a circuit in the same way as drawing or writing letters by applying an electron beam directly to a desired pattern without a mask after applying a thin resist on the semiconductor wafer. Configure It can be used as a research equipment for integrated circuit development because it can shape a circuit with a width of 0.02㎛ or less, but it is not used as a production equipment due to its slow speed. We are currently researching and developing ways to make up for these shortcomings.

셋째, X선 리소그라피(X-ray Lithography)는 반도체 웨이퍼 위에 감광(X-ray) 성질을 가지고 있는 포토레지스트를 얇게 바른 후, 원하는 마스크 패턴을 올려 놓고 X 선을 가하여 사진을 찍는 것과 같은 방법으로 회로를 구성한다. 회로선폭 0.1㎛ 이하의 회로를 형상화할 수 있어 생산 장비로 개발하고 있으나 기술적 어려움이있다.Third, X-ray lithography is applied to the circuit in the same way as taking a photo by applying a X-ray with a desired mask pattern after applying a thin photoresist having an X-ray property on the semiconductor wafer. Configure Although circuits with a circuit line width of 0.1 μm or less can be shaped, they are being developed as production equipment, but there are technical difficulties.

한편, LDMOS 소자의 채널을 형성하기 위해 패턴 형성을 통하여 패터닝 작업을 하게 된다. 이때 포토리소그래피 작업의 특성상, 도 1a에서 보는 바와 같이 최 외곽의 포토레지스트 패턴(11)에서는 원하지 않는 포토레지스트 패턴의 경사(12)가 발생하게 된다. 이후 채널 형성을 위한 이온 주입 공정에서 표면의 채널 형성을 위하여 붕소이온과 비소이온을 저에너지로 주입하고 웰을 형성하기 위하여 고에너지의 붕소 이온을 주입하게 되는데 고에너지로 주입된 이온이 포토레지스트 패턴을 통과하지 못하도록 충분히 두꺼운 포토레지스트 패턴을 사용하게 된다. 하지만, 포토레지스트에 경사가 있는 곳에서는 실제 포토레지스트 패턴의 두께가 감소하는 효과가 발생하여 도 1b에서 보는 바와 같이 고에너지로 주입된 이온(13)이 얇아진 포토레지스트 패턴을 통과하여 원하지 않는 영역에 이온이 주입(14)되어 채널이 형성되는 지역에 불순물 농도에 변화를 주어 Vt(threshold voltage, 이하 Vt) 변화나 Gm(Transconduction) 곡선의 왜곡을 가져와 소자 특성을 열화시킬 수 있는 문제점이 있다.Meanwhile, patterning is performed through pattern formation to form a channel of the LDMOS device. At this time, due to the characteristics of the photolithography operation, as shown in FIG. 1A, the inclination 12 of the unwanted photoresist pattern is generated in the outermost photoresist pattern 11. Subsequently, in the ion implantation process for channel formation, boron ions and arsenic ions are implanted at low energy to form a channel on the surface, and high energy boron ions are implanted to form a well. Use a photoresist pattern that is thick enough to not pass through. However, where the inclination of the photoresist is inclined, the effect of reducing the thickness of the actual photoresist pattern occurs, and as shown in FIG. 1B, the ions 13 injected at high energy pass through the thinned photoresist pattern to an unwanted area. There is a problem that the characteristics of the device may be degraded by changing the impurity concentration in the region where the ions are implanted 14 to form the impurity concentration, resulting in a change in the threshold voltage (Vt) or the distortion of the Gm (Transconduction) curve.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 형성하고자 하는 채널 패턴의 최외곽에 더미 패턴을 형성하여 정상적인 포토레지스트 패턴의 경사를 방지함으로써 이온 주입 후 소자의 Vt 변화나 Gm 곡선의 왜곡이 생기는 것을 방지하는 패턴 형성 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by forming a dummy pattern on the outermost side of the channel pattern to be formed to prevent the inclination of the normal photoresist pattern to change the Vt or Gm of the device after ion implantation SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern forming method for preventing distortion of a curve.

본 발명의 상기 목적은 소정의 소자가 형성된 기판상에 LDMOS 소자의 채널을 형성하기 위한 실제 패턴 외부에 더미 패턴을 형성하는 단계; 및 상기 패턴을 이용하여 이온 주입하는 단계를 포함하여 이루어진 반도체 소자의 패턴 형성 방법에 의해 달성된다.The object of the present invention is to form a dummy pattern outside the actual pattern for forming a channel of the LDMOS device on a substrate on which a predetermined device is formed; And ion implantation using the pattern.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

도 2a 내지 도 2b는 본 발명에 의한 반도체 소자의 패턴 형성 방법의 공정 단면도이다.2A to 2B are cross-sectional views of a process for forming a pattern of a semiconductor device according to the present invention.

먼저, 도 2a는 소정의 소자가 형성된 기판상에 LDMOS 소자의 채널을 형성하기 위한 실제 패턴 외부에 더미 패턴을 형성하는 단계이다. 도에서 보는 바와 같이 N형 또는 P형으로 도핑된 기판(21)상에 기판의 불순물과 반대의 타입으로 도핑된 웰(well)(22)에 LDMOS의 채널을 형성하기 위해 포토레지스트 패턴(23)을 형성한다. 이때 이온 주입을 위한 정상적인 포토레지스트 패턴(24)뿐만 아니라 포토레지스트 패턴의 최외곽 패턴에서 발생하는 패턴의 경사에 의한 문제점을 해결하기 위해 더미 패턴(25)을 형성한다. 상기 더미 패턴은 상기 포토레지스트 패턴의 최외곽에 발생할 수밖에 없는 패턴의 경사를 형성하여 발생하지 말아야 하는 정상적인 포토레지스트 패턴을 보호하는 역할을 한다.First, FIG. 2A is a step of forming a dummy pattern outside an actual pattern for forming a channel of an LDMOS device on a substrate on which a predetermined device is formed. As shown in the figure, a photoresist pattern 23 is formed on the substrate 21 doped with N-type or P-type to form a channel of LDMOS in a well 22 doped with a type opposite to that of the substrate. To form. In this case, the dummy pattern 25 is formed to solve the problem caused by the inclination of the pattern generated in the outermost pattern of the photoresist pattern as well as the normal photoresist pattern 24 for ion implantation. The dummy pattern serves to protect a normal photoresist pattern that should not occur by forming a slope of a pattern that must occur on the outermost side of the photoresist pattern.

다음, 도 2b는 상기 패턴을 이용하여 이온 주입하는 단계이다. 도에서 보는 바와 같이 채널 형성을 위해 이온 주입 공정(26)을 진행하여 기판상에 불순물 이온(27)을 주입한다. 이때 최외곽의 더미 패턴에만 경사진 패턴(28)이 형성되고 채널을 형성하는 정상적인 포토레지스트 패턴(24)에는 정상적으로 형성되어 원하지 않는 영역에 이온 주입되어 채널이 형성되는 것을 방지한다.Next, FIG. 2B is a step of ion implantation using the pattern. As shown in the figure, an ion implantation process 26 is performed to form a channel to implant impurity ions 27 onto the substrate. At this time, the inclined pattern 28 is formed only in the outermost dummy pattern and is normally formed in the normal photoresist pattern 24 forming the channel, thereby preventing the channel from being formed by ion implantation in an unwanted region.

상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

따라서, 본 발명의 반도체 소자의 패턴 형성 방법은 형성하고자 하는 채널 패턴의 최외곽에 더미 패턴을 형성하여 정상적인 포토레지스트 패턴의 경사를 방지함으로써 이온 주입 후 소자의 Vt 변화나 Gm 곡선의 왜곡이 생기는 것을 방지하는 효과가 있다.Therefore, the pattern forming method of the semiconductor device of the present invention forms a dummy pattern at the outermost part of the channel pattern to be formed to prevent the inclination of the normal photoresist pattern, thereby preventing the change of the Vt or the Gm curve of the device after ion implantation. It is effective to prevent.

Claims (1)

반도체 소자의 패턴 형성 방법에 있어서,In the pattern formation method of a semiconductor element, 소정의 소자가 형성된 기판상에 LDMOS 소자의 채널을 형성하기 위한 실제 패턴 외부에 더미 패턴을 형성하는 단계; 및Forming a dummy pattern outside the actual pattern for forming a channel of the LDMOS device on the substrate on which the predetermined device is formed; And 상기 패턴을 이용하여 이온 주입하는 단계Ion implantation using the pattern 를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 패턴 형성 방법.Pattern forming method of a semiconductor device, characterized in that comprises a.
KR1020030101592A 2003-12-31 2003-12-31 Method for fabricating pattern of semiconductor device KR100540332B1 (en)

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