KR20040006490A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20040006490A
KR20040006490A KR1020020040783A KR20020040783A KR20040006490A KR 20040006490 A KR20040006490 A KR 20040006490A KR 1020020040783 A KR1020020040783 A KR 1020020040783A KR 20020040783 A KR20020040783 A KR 20020040783A KR 20040006490 A KR20040006490 A KR 20040006490A
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South Korea
Prior art keywords
forming
nmos
polysilicon layer
opening
region
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KR1020020040783A
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Korean (ko)
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류혁현
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주식회사 하이닉스반도체
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Priority to KR1020020040783A priority Critical patent/KR20040006490A/en
Publication of KR20040006490A publication Critical patent/KR20040006490A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of solving the CD(Critical Dimension) bias problem of an NMOS(N channel Metal Oxide Semiconductor) and a PMOS(P channel Metal Oxide Semiconductor) due to an N pre-doping process. CONSTITUTION: An isolation layer(23) is formed at the inner portion of a semiconductor substrate(21). After forming an HLD oxide layer at the upper portion of the semiconductor substrate, opening portions are formed at the HLD oxide layer for exposing each gate portion of an NMOS and PMOS region. After forming a gate oxide layer(27) at the upper surface of the substrate through the opening portion, polysilicon patterns(29a,29b) are formed at the opening portions. An N pre-doping process is carried out at the polysilicon pattern of the NMOS region. After removing the HLD oxide layer, a source/drain region are formed at both sides of each polysilicon pattern in the substrate.

Description

반도체소자의 제조방법{Method for fabricating semiconductor device}Method for fabricating semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 폴리 다마신 공정을 이용한 폴리실리콘 배선 형성 및 패터닝후에 N 프리도핑(predoping)을 진행하여 N 프리도핑에 따른 N, PMOS의 CD 바이어스 문제를 해결하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to preform N N doping after forming and patterning polysilicon wires using a poly damascene process, a CD bias problem of N and PMOS due to N predoping. The present invention relates to a method for manufacturing a semiconductor device.

현재 CMOS를 이용한 로직 디바이스 제조방법에 있어, NMOS 형성시에 폴리 게이트 도핑효율을 높이기 위하여 PMOS와는 달리 NMOS 폴리게이트지역만 인(phosphorus) 도펀트를 이용한 임플란트 공정을, 도 1에서와 같이, 폴리 게이트 식각전에 실시하고 있다. 이때, 상기 임플란트 공정시에 PMOS지역은 감광막(미도시)으로 덮은 상태에서 실시한다. 이때, 상기 프리도핑을 진행하기 전에 반도체기판(11)내에 트렌치소자분리막(13)과 게이트산화막(15) 및 폴리실리콘층(17)을 적층한다.In the current method of manufacturing a logic device using CMOS, in order to increase poly gate doping efficiency when forming an NMOS, an implant process using a phosphorus dopant in only the NMOS polygate region is different from that of PMOS, as shown in FIG. 1. We do before. At this time, the PMOS region is covered with a photoresist film (not shown) during the implant process. In this case, the trench isolation layer 13, the gate oxide layer 15, and the polysilicon layer 17 are stacked in the semiconductor substrate 11 before the predoping is performed.

그다음, 도 2에 도시된 바와같이, NMOS 및 PMOS의 폴리게이트 패터닝공정을 진행하여 폴리게이트(17a)(17b) 및 게이트산화막(15a)(15b)을 형성한다.Next, as shown in FIG. 2, polygate patterning processes of NMOS and PMOS are performed to form polygates 17a and 17b and gate oxide films 15a and 15b.

이후 소오스/드레인 임플란트 공정을 PMOS와 NMOS에 대해 각각 진행시켜 폴리게이트와 접합 형성부분을 도핑시킨다.A source / drain implant process is then performed for the PMOS and NMOS, respectively, to dope the polygate and junction formation.

이와 같이 NMOS 폴리게이트지역(17)만을 미리 도핑시키는 공정(이하, N 프리도핑이라함)은 큰 문제점을 발생시킨다.As described above, the process of doping only the NMOS polygate region 17 in advance (hereinafter referred to as N predoping) causes a big problem.

여기서, 폴리게이트층(17) 식각시에 NMOS와 PMOS사이에 CD가 달라진다는 점이다. 이는 N 프리도핑에 의하여 NMOS와 PMOS의 폴리게이트부분사이에 식각되는 특성이 달라지기 때문이다. 즉, NMOS 폴리 게이트의 식각률이 높아짐에 따라 NMOS의 CD가 작아지고, 또한 프로파일도 달라진다.Here, the CD is changed between the NMOS and the PMOS when the polygate layer 17 is etched. This is because the etched property between the NMOS and the polygate portion of the PMOS is changed by N predoping. That is, as the etching rate of the NMOS poly gate increases, the CD of the NMOS becomes smaller and the profile also changes.

이렇게 CD 및 프로파일이 다른 것은 공정 및 소자 마진확보에 큰 영향을 실제적으로 주고 있다.This different CD and profile has a significant impact on process and device margins.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 폴리 다마신 공정을 이용한 폴리실리콘 배선 형성 및 패터닝후에 N 프리 도핑(predoping)을 진행하여 N 프리도핑에 따른 NMOS와 PMOS의 CD 바이어스 문제를 해결할 수 있는 반도체소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, N poly doping after the polysilicon wiring formation and patterning using the poly damascene process by the N pre-doping (pre-doping) by NMOS and PMOS CD according to N pre-doping It is an object of the present invention to provide a method for manufacturing a semiconductor device that can solve the bias problem.

도 1 및 도 2는 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정별 단면도.1 and 2 are cross-sectional views for each process for explaining a method of manufacturing a semiconductor device according to the present invention.

도 3 내지 도 10은 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정별 단면도.3 to 10 are cross-sectional views for each process for describing a method of manufacturing a semiconductor device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

21 : 반도체기판23 : 트렌치소자분리막21 semiconductor substrate 23 trench isolation film

25 : HLD산화막27 : 게이트산호막25: HLD oxide film 27: gate coral film

29 : 폴리실리콘층29a : 폴리실리콘층패턴29: polysilicon layer 29a: polysilicon layer pattern

31 : 감광막31: photosensitive film

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은, 반도체기판에 트렌치소자분리막을 형성하는 단계; 상기 반도체기판상에 HLD 산화막을 형성한후 NMOS지역과 PMOS지역의 게이트영역을 노출시키는 개구부를 형성하는 단계; 상기 개구부아래의 반도체기판표면에 게이트 산화막을 형성하는 단계; 상기 개구부내에 폴리실리콘층패턴을 형성한후 NMOS지역의 폴리실리콘층 패턴부분에 N프리도핑을 실시하는 단계; 및 상기 잔류하는 HLD 산화막을 제거한후 폴리실리콘층패턴양측아래의 반도체기판에 소오스/드레인영역을 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of: forming a trench device isolation film on a semiconductor substrate; Forming an opening for exposing a gate region of an NMOS region and a PMOS region after forming an HLD oxide film on the semiconductor substrate; Forming a gate oxide film on a surface of the semiconductor substrate under the opening; Forming a polysilicon layer pattern in the opening and performing N predoping on the polysilicon layer pattern portion of the NMOS region; And forming a source / drain region in the semiconductor substrate under both sides of the polysilicon layer pattern after removing the remaining HLD oxide layer.

(실시예)(Example)

이하, 본 발명에 따른 반도체소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 3 내지 도 10은 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.3 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

본 발명에 따른 반도체소자의 제조방법은, 도 3에 도시된 바와같이, 먼저 반도체기판(21)내에 트렌치소자분리막(23)을 형성한후 문턱전압 조절용 이온주입을포함한 웰 이온주입을 진행한다.In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 3, first, a trench device isolation film 23 is formed in a semiconductor substrate 21, and then well ion implantation including ion implantation for adjusting the threshold voltage is performed.

그다음, 도 4에 도시된 바와같이, 전체 구조의 상면에 HLD 산화막(25)을 약 2500 Å 두께로 증착한다.Then, as shown in Fig. 4, an HLD oxide film 25 is deposited to a thickness of about 2500 m 3 on the upper surface of the entire structure.

이어서, 도 5에 도시된 바와같이, 상기 HLD산화막(25)상에 폴리실리콘 배선이 형성될 지역을 노광마스크(미도시)를 이용한 포토공정 및 식각공정을 통하여 개구부(25a)를 형성한다. 이때, 개구부(25a)는 동일한 CD값을 갖는다.Subsequently, as shown in FIG. 5, an opening 25a is formed in the region where the polysilicon wiring is to be formed on the HLD oxide film 25 through a photo process and an etching process using an exposure mask (not shown). At this time, the opening portion 25a has the same CD value.

그다음, 도 6에 도시된 바와같이, 게이트산화공정을 진행하여 상기 개구부(25a)아래의 반도체기판(21)의 표면에 게이트산화막(27)을 성장시킨다.Next, as shown in FIG. 6, a gate oxidation process is performed to grow a gate oxide film 27 on the surface of the semiconductor substrate 21 under the opening 25a.

이어서, 도 7에 도시된 바와같이, 상기 개구부(25)를 포함한 전체 구조의 상면에 약 3500 내지 4500 Å 두께의 폴리실리콘층(29)을 증착한다.Subsequently, as shown in FIG. 7, a polysilicon layer 29 of about 3500 to 4500 mm thick is deposited on the upper surface of the entire structure including the opening 25.

그다음, 도 8에 도시된 바와같이, CMP 공정을 실시하여 상기 개구부(25a)내에 폴리실리콘층패턴(29a)을 형성한다. 이때, 상기 HLD산화막(25)상에 있는 폴리실리콘층은 모두 제거한다.Then, as shown in FIG. 8, a CMP process is performed to form the polysilicon layer pattern 29a in the opening 25a. At this time, all of the polysilicon layer on the HLD oxide layer 25 is removed.

이어서, 도 9에 도시된 바와같이, 상기 전체 구조의 상면에 감광물질을 도포한후 포토리소그라피공정기술에 의해 NMOS 지역에 위치하는 상기 감광물질을 노광 및 현상을 거쳐 식각하여 감광막패턴(31)을 형성한다.Subsequently, as shown in FIG. 9, after the photosensitive material is coated on the upper surface of the entire structure, the photosensitive material located in the NMOS region is exposed and etched through the photolithography process technology to expose the photosensitive film pattern 31. Form.

그다음, 상기 감광막패턴(31)을 마스크로 상기 노출된 NMOS지역에 N 프리도핑을 진행한다.Next, N predoping is performed on the exposed NMOS region using the photoresist pattern 31 as a mask.

이어서, 도 10에 도시된 바와같이, 남아 있는 감광막패턴(31)과 HLD 산화막(25)을 제거한다. 이때, 상기 HLD 산화막(25)은 BOE 용액을 이용하여 제거한다. 이렇게 되면, N 프리도핑을 맞은 지역과 맞지 않은 지역의 CD 차이가 전혀 없게 된다.Subsequently, as shown in FIG. 10, the remaining photoresist layer pattern 31 and the HLD oxide layer 25 are removed. At this time, the HLD oxide layer 25 is removed using a BOE solution. This ensures that there is no CD difference between the regions that are hit with N predoping and the regions that are not hit.

그다음, 이후 공정은 LDD 임플란트, LDD 스페이서 형성, 소오스/드레인 임플란트 공정 등을 거치는 기존 방법을 이용한다.Then, the subsequent process uses an existing method that goes through LDD implant, LDD spacer formation, source / drain implant process, and the like.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 제조방법에 의하면, NMOS 프리도핑 공정을 폴리게이트 식각전에 하는 것이 아니라 폴리실리콘 배선을 패터닝한후 실시하여 NMOS와 PMOS의 CD 바이어스를 없애 주므로써 현재 로직 디바이스 개발에 적용하고 있는 N 프리도핑에 따르는 심각한 문제를 제거할 수 있게 된다.As described above, according to the method of manufacturing a semiconductor device according to the present invention, the NMOS predoping process is performed after the polysilicon wiring is patterned instead of before the polygate etching, thereby eliminating the CD bias of the NMOS and PMOS. This can eliminate the serious problem of N predoping in logic device development.

따라서, 폴리게이트 식각공정의 안정화 및 마진 확대 그리고 소자의 특성 향상을 얻을 수 있게 된다.Accordingly, it is possible to obtain stabilization and margin expansion of the polygate etching process and improvement of device characteristics.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (5)

반도체기판에 트렌치소자분리막을 형성하는 단계;Forming a trench isolation layer on the semiconductor substrate; 상기 반도체기판상에 HLD산화막을 형성한후 NMOS지역과 PMOS지역의 게이트영역을 노출시키는 개구부를 형성하는 단계;Forming an opening for exposing a gate region of an NMOS region and a PMOS region after forming an HLD oxide film on the semiconductor substrate; 상기 개구부아래의 반도체기판표면에 게이트 산화막을 형성하는 단계;Forming a gate oxide film on a surface of the semiconductor substrate under the opening; 상기 개구부내에 폴리실리콘층패턴을 형성한후 NMOS지역의 폴리실리콘층패턴부분에 N프리도핑을 실시하는 단계; 및Forming a polysilicon layer pattern in the opening and then performing N predoping on the polysilicon layer pattern portion of the NMOS region; And 상기 잔류하는 HLD 산화막을 제거한후 폴리실리콘층패턴양측아래의 반도체기판에 소오스/드레인영역을 형성하는 단계를 포함하여 구성되는 것을 특징으로하는 반도체소자의 제조방법.And removing the remaining HLD oxide layer and forming a source / drain region on the semiconductor substrate under both sides of the polysilicon layer pattern. 제1항에 있어서, 상기 HLD 산화막은 2000 내지 3000 Å두께로 증착하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the HLD oxide film is deposited at a thickness of 2000 to 3000 microns. 제1항에 있어서, 상기 폴리실리콘층패턴을 형성하는 단계는, 먼저 상기 개구부를 포함한 HLD산화막상에 폴리실리콘층을 증착한후 CMP공정을 실시하여 상기 개구부내에만 남도록 하는 단계로 진행되는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the forming of the polysilicon layer pattern is performed by first depositing a polysilicon layer on the HLD oxide layer including the opening and then performing a CMP process so that the polysilicon layer pattern remains only in the opening. A method of manufacturing a semiconductor device. 제2항에 있어서, 상기 폴리실리콘층은 3500 내지 4000 Å 두께로 증착하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 2, wherein the polysilicon layer is deposited to a thickness of 3500 to 4000 microns. 제1항에 있어서, 상기 HLD산화막은 BOE 용액으로 제거하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the HLD oxide film is removed with a BOE solution.
KR1020020040783A 2002-07-12 2002-07-12 Method for fabricating semiconductor device KR20040006490A (en)

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