KR100303914B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, by forming a buffer dielectric layer having a different thickness of threshold voltages of transistors having different driving voltages on the same chip, and performing ion implantation for adjusting threshold voltages, respectively. The invention relates to a method for adjusting a threshold voltage of a semiconductor device to simplify a process by forming a channel region having a plurality of channel regions. In the method of controlling a threshold voltage of a semiconductor device according to the present invention, a first buffer dielectric film is formed on a surface of a first active region on a semiconductor substrate in which a first active region and a second active region are isolated, and a first buffer dielectric film is formed on a surface of a second active region. Forming a thicker second buffer dielectric film, performing ion implantation for adjusting the threshold voltage on the first buffer dielectric film and the second buffer dielectric film, and removing the first buffer dielectric film and the second buffer dielectric film. Is done.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, by forming a buffer dielectric layer having a different thickness of threshold voltages of transistors having different driving voltages on the same chip, and performing ion implantation for adjusting threshold voltages, respectively. The invention relates to a method for adjusting a threshold voltage of a semiconductor device to simplify a process by forming a channel region having a plurality of channel regions.

Recently, systems such as multimedia, which simultaneously display images, voices, and texts, are required to be miniaturized and lightweight while having various, complex, and improved functions. In order to meet the demand as described above, a technology of forming a single chip in which semiconductor circuits having different functions constituting a system are integrated and formed on the same chip has been developed.

Single-chip semiconductor circuits have different functions, and a plurality of circuits operating in different power sources must be formed such that the original functions and performances are maintained on the same semiconductor substrate. That is, a configuration of transistors having different driving voltages is required on the same semiconductor substrate, and in order to implement this, the threshold voltages of the devices must be adjusted to be different from each other.

The process of forming a dual gate oxide film for a product in which the operation voltage of the input / output terminal portion of the semiconductor device and the core portion where the logic is actually operated are differently required in the logic product. In this case, due to the LED region formed by the same design rule as the thickness of the different gate oxide film, a hot-carrier effect occurs in a transistor having a thin oxide film, thereby deteriorating device characteristics.

1A to 1D are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art, and illustrate a manufacturing process of a transistor having a gate insulating film having a different thickness from each other.

In FIG. 1A, a gate oxide film is grown by thermally oxidizing a surface of a silicon substrate 1 on which an element isolation field oxide film 2 is formed, and then a photoresist is formed to form a thick gate oxide film. A pattern (not shown) is formed.

Then, the gate oxide film of the portion not protected by the photoresist pattern is removed and then the photoresist pattern is removed. At this time, a thin gate oxide film is formed on the etched portion in a subsequent process.

Then, pre-cleaning is performed on the surface of the silicon substrate 1 to completely remove the remaining gate oxide film on the thin gate oxide film forming portion, thereby completely exposing the surface of the silicon substrate 1 at the portion except for the remaining gate oxide film.

Next, the surface of the silicon substrate 1 is thermally oxidized to grow an oxide film on the entire surface of the substrate 1 again. Therefore, the remaining gate oxide film portion becomes thicker to form a thick gate oxide film 3 and the remaining portion becomes a thin gate oxide film 4.

Referring to FIG. 1B, a polysilicon layer 5 doped with an impurity on the entire surface of the substrate 1 is formed to a predetermined thickness to form a gate, and then a photo using a mask for forming a gate pattern thereon. The resist pattern is formed by a photolithography process, and the polysilicon layer in a portion which is not protected by the photoresist pattern is dry-etched to remove the gate 5.

In addition, since the ion implantation for forming the low concentration impurity diffusion region on the entire surface of the substrate 1 is performed at low concentration using the gate 5 as an ion implantation mask, the LED region 6 is formed under the gate oxide films 3 and 4. On the substrate 1.

Referring to FIG. 1C, a high temperature low insulating film is formed on an entire surface of a substrate, that is, an upper surface of an exposed gate and an exposed surface of side gate oxide films 3 and 4 and an exposed field oxide film 2. and an oxide film 7 such as a pressure dielectric. At this time, the oxide film 7 is partially etched in a subsequent process to form a gate side wall.

Referring to FIG. 1D, anisotropic etching is performed on the oxide film 7 until the upper surface of the gate 5 is exposed to form the gate sidewall 8 made of the oxide film 7 remaining on the side surface of the gate 5. do.

In addition, an ion implantation using the gate side wall 8 and the gate 5 as an ion implantation mask is performed at a high concentration to form a high concentration impurity region 9 connected to the LED region to manufacture an LED transistor. At this time, impurities in the LED region 6 and the highly concentrated impurity region 9 are sufficiently diffused to form a source / drain.

2A to 2B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to another embodiment of the prior art, and illustrate a method of directly adjusting a threshold voltage by ion implantation into a substrate.

Referring to FIG. 2A, after the photoresist is applied to the semiconductor substrate 21, the first photoresist pattern 22 exposing the first device formation region having the first threshold voltage is formed by exposure and development.

The threshold voltage is adjusted on the entire surface of the substrate to adjust the threshold voltage of the first device formation region, which is a portion not protected by the first photoresist pattern 22.

Referring to FIG. 2B, after removing the first photoresist pattern, the second photoresist pattern 23 exposing the second device formation region having the second threshold voltage after applying photoresist to the surface of the substrate 21 again. ) Is formed by exposure and development.

In addition, the threshold voltage is adjusted on the entire surface of the substrate to adjust the threshold voltage of the second device formation region, which is not protected by the second photoresist pattern 23.

Subsequently, although not shown, a transistor having a different driving voltage is manufactured by forming a gate insulating film, a gate, an impurity ion diffusion region, and the like.

As described above, the method for adjusting the threshold voltage of a device formed by the prior arts has a problem in that the process is cumbersome and the manufacturing cost of the device increases because a complicated photo process and ion implantation have to be performed.

That is, in the first exemplary embodiment, a separate mask and a photographic process are generally required to reduce the threshold voltage for improving the performance of a transistor having a thick gate insulating film, and in the second embodiment, each has two kinds of threshold voltages. When manufacturing a PMOS device and an NMOS device, four types of masks and four steps of photo processing are required.

An object of the present invention is to form a buffer dielectric layer having different thicknesses of threshold voltages of transistors having different driving voltages on a substrate, and to form channel regions having different threshold voltages by performing ion implantation for adjusting threshold voltages. To provide a method for adjusting the threshold voltage of a semiconductor device to simplify the.

A method of manufacturing a semiconductor device according to the present invention for achieving the above object is to form a first buffer dielectric film on the surface of the first active region on a semiconductor substrate in which the first active region and the second active region are isolated, and to the surface of the second active region. Forming a second buffer dielectric film thicker than the first buffer dielectric film, performing ion implantation for adjusting the threshold voltage on the first buffer dielectric film and the second buffer dielectric film, and removing the first buffer dielectric film and the second buffer dielectric film A step is made.

1A to 1D are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

2A to 2B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to another embodiment of the prior art.

3A to 3B are cross-sectional views of a manufacturing process of a semiconductor device according to the present invention.

In general, logic products are designed with different operating voltages at the input / output part and the main core part, and in the case of the system, the demand tends to increase. This is due to the intention to operate the logic by accepting the external voltage as it is in the input / output of data and to operate the low voltage in the main core. Accordingly, problems of breakdown voltage and threshold voltage of the gate oxide film are raised. For this purpose, different threshold voltages are formed in each active region.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention, and illustrate a method of controlling a threshold voltage using a buffer film by ion implantation into a substrate.

Referring to FIG. 3A, photoresist patterns 300 are formed on the surface of the semiconductor substrate 31 to form buffer dielectric films 32 and 33, apply photoresist thereon, and then expose the first active region B1. Is formed on the buffer dielectric film 32. At this time, in the first active region B1 and the second active region B2 having different threshold voltages, the portion of the second active region B2 is covered with the photoresist pattern 300 and thus the first active region threshold voltage. The buffer dielectric film for the control ion implantation is left as it is to maintain the original dielectric film thickness.

Then, an etching process is performed on the entire surface of the substrate to remove the buffer dielectric film 33 in a portion not protected by the photoresist pattern 300 to a predetermined thickness, so that the first buffer dielectric film 33 and the second buffer dielectric film 32 are removed. Define. This is because the thickness of the buffer dielectric film is changed before the ion implantation for the threshold voltage control, so that a relatively small dose of ions are injected into the substrate at the bottom of the thick buffer dielectric film to obtain a low threshold voltage. This is to allow ions to be implanted to have a relatively high threshold voltage. That is, to adjust the threshold voltage of the device by controlling the ion implantation dose injected into the channel region of each transistor by controlling the thickness of the buffer dielectric film.

Referring to FIG. 3B, after removing the photoresist pattern, ion implantation for adjusting the threshold voltage is performed on the entire surface of the substrate including the exposed surface of the buffer dielectric film 32. Accordingly, the first buried layer 34 doped with a high concentration of ions for threshold voltage easily passing through the buffer dielectric layer 33 having a relatively thin thickness is formed on the substrate under the first buffer dielectric layer 33. The second buried layer 35 doped with a low concentration of the threshold voltage control ions that have passed through the second buffer dielectric film 32 having a relatively thick thickness relatively difficult is formed on the substrate under the second buffer dielectric film 32.

As a result, the first active region B1 is heavily doped and the second active region B2 is lightly doped to have different threshold voltages.

Subsequently, although not shown, the buffer dielectric films 33 and 32 are removed, and then a gate insulating film, a gate, an impurity ion diffusion region, and the like are formed to manufacture transistors having different driving voltages.

The present invention can be applied to the manufacture of CMOS devices and the like as well as the same conductive type devices.

Therefore, in the present invention, since the thickness of the buffer dielectric film is differently formed before the threshold voltage ion implantation, the ion implantation is performed, and only the mask element for controlling the thickness of the buffer dielectric film is added. Since it can be manufactured, there is an advantage of simplifying the process and reducing manufacturing cost.

Claims (4)

Forming a dielectric film on the semiconductor substrate, wherein the first active region and the second active region are separated from each other; Forming an etching mask on a portion of the dielectric layer corresponding to the second active region; By removing a portion of the dielectric layer that is not protected from the etch mask by a predetermined thickness, the first buffer dielectric layer of the first active region remaining by etching the dielectric layer and the second buffer of the second active region thicker than the first buffer dielectric layer. Dividing into dielectric layers, The first buffer dielectric film and the second buffer dielectric film having different thicknesses are implanted with ion implants for adjusting the threshold voltage, so that a smaller dose than the first active region is formed in the second active region under the second buffer dielectric film. Implanting ions of to have a low threshold voltage, And removing the first buffer dielectric film and the second buffer dielectric film. The method according to claim 1, After the step of removing the first to second buffer dielectric film, And manufacturing a plurality of transistors by forming a gate insulating film, a gate, a source / drain, and the like on the semiconductor substrate. The method of claim 2, wherein each of the plurality of transistors has a different threshold voltage. The method of claim 2, wherein the plurality of transistors are CMOS transistors.