KR20040002207A - Method for manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to reduce a short channel effect of a p-channel metal oxide semiconductor(PMOS) transistor by performing a channel control ion implantation process of an NMOS transistor before the first gate oxide layer is formed and by performing a channel control ion implantation process of the PMOS transistor after the first gate oxide layer is formed. CONSTITUTION: A portion of a dual gate oxide layer for a thin gate oxide layer is defined in a semiconductor substrate including a p-well and an n-well. A buffer layer is formed on the substrate. N channel control ions are implanted into the p-well to form an n channel region in the surface of the p-well. The buffer layer is removed. The first gate oxide layer is grown on the substrate. P channel control ions are implanted into the n-well to form a p channel region in the surface of the n-well. The first gate oxide layer in a portion for the thin gate oxide layer is etched to expose the substrate. The second gate oxide layer is grown on the exposed substrate and the first gate oxide layer to form the dual gate oxide layer.

Description

Method for manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, in a transistor forming process having a dual gate oxide film, a thermal oxidation process is performed after a channel control ion implantation process of a PMOS transistor. The present invention relates to a method for manufacturing a semiconductor device which improves the characteristics of the device.

The dual gate oxide film process is to form two kinds of gate oxide films having different thicknesses in the same wafer. The dual gate oxide film process is composed of a core chip portion requiring fast operation and an input / output block where reliability is important. It is a process generally used in circuit devices.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, in which “I” shows a first region where a NMOS transistor is to be formed, and “II” shows a portion where a PMOS transistor is to be formed. The second region is shown.

Referring to FIG. 1A, in a dual gate oxide film process, a semiconductor substrate 11 having a portion where a thin gate oxide film is to be formed is provided, and then a device isolation film forming process common to the semiconductor substrate 11 in the device isolation region. An element isolation film 13 is formed.

A first photosensitive film pattern (not shown) is formed on the semiconductor substrate 11 to expose only the first region I.

Subsequently, p-type impurities are ion-implanted on the entire surface with the first photoresist pattern as a mask to form a p well 15 in the surface of the semiconductor substrate 11 of the first region (I), and the first photoresist pattern is removed. do.

Then, the n well 17 is formed in the surface of the semiconductor substrate 11 of the second region (II) in the same process as that of forming the p-type well 15.

Thereafter, an oxide film 19, which is a buffer layer, is formed on the semiconductor substrate 11, and a second photosensitive film pattern 21 is formed on the oxide film 19 to expose only the first region I. do.

In addition, an n-channel controlled ion implantation process is performed on the entire surface of the second photoresist pattern 21 using a mask to form an n-channel region 23 in the surface of the p well 15.

Referring to FIG. 1B, the second photoresist layer pattern 21 is removed, and a third photoresist layer pattern 25 exposing only the second region II is formed on the oxide layer 19.

Then, a p-channel controlled ion implantation process is performed on the entire surface of the n-type photoresist layer 25 using a mask to form a p-channel region 27 in the n well 17 surface.

Referring to FIG. 1C, the third photoresist layer pattern 25 and the oxide layer 19 are removed, and the first gate oxide layer 29 is grown on the semiconductor substrate 11 by a thermal oxidation process.

A fourth photoresist pattern 31 is formed on the first gate oxide layer 29 to expose only a portion where the thin gate oxide layer is to be formed.

Referring to FIG. 1D, the first gate oxide layer 29 is etched using the fourth photoresist pattern 31 as a mask to expose the semiconductor substrate 11, and then the fourth photoresist pattern 31 is removed. .

The thermal oxidation process is performed to grow a second gate oxide layer 33 on the exposed semiconductor substrate 11 and the first gate oxide layer 29.

Here, a thin gate oxide film is formed of the second gate oxide film 33 formed on the exposed semiconductor substrate 11, and the second gate oxide film 33 formed on the first gate oxide film 29. ), A thick gate oxide film is formed, and a dual gate oxide film including the thin gate oxide film and the thick gate oxide film is formed.

However, the conventional method of manufacturing a semiconductor device has a short channel (Short) as the depth of the channel of the buried channel PMOS transistor is increased by two thermal processes for growing the gate oxide in the transistor forming process having the dual gate oxide film. There was a problem that the characteristics of the device is degraded due to an increase in the channel) effect.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the transistor formation process having a dual gate oxide film, the channel control ion implantation process of the NMOS transistor is performed before the first gate oxide film formation, and the channel control ion implantation of the PMOS transistor is performed. It is an object of the present invention to provide a method for manufacturing a semiconductor device which reduces the short channel effect of a PMOS transistor by performing the process after the first gate oxide film is formed.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

<Description of the symbols for the main parts of the drawings>

11,41 semiconductor substrate 13,43 device isolation film

15,45: p well 17,47: n well

19, 49: oxide film 21, 51: second photosensitive film pattern

23,53: n channel region 25,57: third photosensitive film pattern

27,59: p-channel region 29,55: first gate oxide film

31,61: fourth photosensitive film pattern 33,63: second gate oxide film

The present invention for achieving the above object,

Providing a semiconductor substrate having a p well and an n well, wherein a portion of the dual gate oxide film is to be formed;

Forming a buffer layer on the semiconductor substrate;

Implanting n channel regulatory ions into the p well to form an n channel region in the p well surface;

Removing the buffer layer and growing a first gate oxide film on the semiconductor substrate;

Implanting p channel control ions into the n well to form a p channel region in the n well surface;

Etching the first gate oxide layer of the portion where the thin gate oxide layer is to be formed to expose the semiconductor substrate;

Providing a method of manufacturing a semiconductor device, comprising: forming a dual gate oxide film by growing a second gate oxide film on the exposed semiconductor substrate and the first gate oxide film;

Forming the first gate oxide film at a thickness of 2.5 to 20 nm,

The second gate oxide film is formed to a thickness of 2.5 to 20nm.

The principle of the present invention is that in a transistor forming process having a dual gate oxide film, the channel control ion implantation process of the NMOS transistor is performed before the first gate oxide film formation, and the channel control ion implantation process of the PMOS transistor is performed after the first gate oxide film formation. By proceeding, one thermal oxidation process is performed after the channel control ion implantation process of the PMOS transistor is performed, thereby reducing the short channel effect of the PMOS transistor to increase the refresh characteristics and to enable the fabrication of low voltage devices. .

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, in which “I” shows a first region where a NMOS transistor is to be formed, and “II” shows a portion where a PMOS transistor is to be formed. The second region is shown.

Referring to FIG. 2A, in a dual gate oxide film process, a semiconductor substrate 41 having a portion where a thin gate oxide film is to be formed is provided, and then a device isolation film forming process common to the semiconductor substrate 41 in the device isolation region. The device isolation film 43 is formed.

A first photosensitive film pattern (not shown) is formed on the semiconductor substrate 41 to expose only the first region (I).

Subsequently, p-type impurities are ion-implanted on the entire surface using the first photoresist pattern as a mask to form a p well 45 in the surface of the semiconductor substrate 41 of the first region (I), and the first photoresist pattern is removed. do.

The n well 47 is formed in the surface of the semiconductor substrate 41 in the second region (II) in the same process as the p-type well 45 forming process.

Thereafter, an oxide film 49 serving as a buffer layer is formed on the semiconductor substrate 41, and a second photosensitive film pattern 51 exposing only the first region I is formed on the oxide film 49.

In addition, an n channel control ion implantation process is performed on the entire surface of the second photoresist layer pattern 51 using a mask to form an n channel region 53 in the surface of the p well 45.

Referring to FIG. 2B, the second photoresist layer pattern 51 and the oxide layer 49 are removed, and the first gate oxide layer 55 is grown to a thickness of 2.5 to 20 nm on the semiconductor substrate 41 by a thermal oxidation process. Let's do it.

A third photoresist layer pattern 57 may be formed on the first gate oxide layer 55 to expose only the second region II.

Subsequently, a p-channel control ion implantation process is performed on the entire surface of the n-photosensitive film pattern 57 using a mask to form a p-channel region 59 in the n well 47 surface.

Referring to FIG. 2C, the fourth photoresist pattern 61 may be removed and the fourth photoresist pattern 61 exposing only a portion where the thin gate oxide layer is to be formed on the first gate oxide layer 55. Form.

The first gate oxide layer 55 is etched using the fourth photoresist pattern 61 as a mask to expose the semiconductor substrate 41.

Referring to FIG. 2D, the fourth photoresist layer pattern 61 is removed and a thermal oxidation process is performed to form a second gate oxide layer 63 on the exposed semiconductor substrate 41 and the first gate oxide layer 55. It grows to thickness of 2.5-20 nm.

Here, a thin gate oxide film is formed from the second gate oxide film 63 formed on the exposed semiconductor substrate 41, and the second gate oxide film 63 is formed on the first gate oxide film 55. ), A thick gate oxide film is formed, and a dual gate oxide film including the thin gate oxide film and the thick gate oxide film is formed.

In the method of manufacturing a semiconductor device of the present invention, in the transistor forming step having a dual gate oxide film, the channel control ion implantation process of the NMOS transistor is performed before the first gate oxide film formation, and the channel control ion implantation process of the PMOS transistor is performed first. By proceeding after the gate oxide film formation, the thermal oxidation process is performed once after the channel control ion implantation process of the PMOS transistor is performed, thereby reducing the short channel effect of the PMOS transistor, thereby increasing the refresh characteristics and manufacturing a low voltage device. There is an effect of improving the characteristics of the device.

Claims (3)

Providing a semiconductor substrate having a p well and an n well, wherein a portion of the dual gate oxide film is to be formed; Forming a buffer layer on the semiconductor substrate; Implanting n channel regulatory ions into the p well to form an n channel region in the p well surface; Removing the buffer layer and growing a first gate oxide film on the semiconductor substrate; Implanting p channel control ions into the n well to form a p channel region in the n well surface; Etching the first gate oxide layer of the portion where the thin gate oxide layer is to be formed to expose the semiconductor substrate; And growing a second gate oxide film on the exposed semiconductor substrate and the first gate oxide film to form a dual gate oxide film. The method of claim 1, The first gate oxide film is formed to a thickness of 2.5 to 20nm, the manufacturing method of a semiconductor device. The method of claim 1, The second gate oxide film is formed to a thickness of 2.5 to 20nm, the manufacturing method of a semiconductor device.