KR20030001788A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20030001788A KR20030001788A KR1020010037475A KR20010037475A KR20030001788A KR 20030001788 A KR20030001788 A KR 20030001788A KR 1020010037475 A KR1020010037475 A KR 1020010037475A KR 20010037475 A KR20010037475 A KR 20010037475A KR 20030001788 A KR20030001788 A KR 20030001788A
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title abstract description 32
- 238000004519 manufacturing process Methods 0.000 title abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 230000002093 peripheral effect Effects 0.000 claims description 16
- 238000002955 isolation Methods 0.000 claims description 8
- 230000001105 regulatory effect Effects 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 28
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract 3
- 238000009792 diffusion process Methods 0.000 abstract 1
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- 229920002120 photoresistant polymer Polymers 0.000 description 20
- 230000009977 dual effect Effects 0.000 description 16
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 듀얼(Dual) 게이트 산화막 공정에 있어서, 주변 영역의 PMOS의 카운터 도핑(Counter doping) 이온 주입 공정을 제 1 게이트 산화막 형성 공정과 제 2 게이트 산화막 형성 공정 사이에 진행하여 소자의 수율 및 신뢰성을 향상시키고 공정을 단순화시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in a dual gate oxide film process, a counter doping ion implantation process of a PMOS in a peripheral region may be performed by forming a first gate oxide film and a second gate oxide film. The present invention relates to a method for manufacturing a semiconductor device that progresses between processes to improve the yield and reliability of the device and simplify the process.
일반적인 디램(Dynamic Random Access Memory : DRAM) 공정에서는 안정성을 위하여 단일 게이트 산화막만을 사용하여 왔으나, 고속 동작을 요구하는 DRAM의 필요성이 점차 커지기 때문에 얇은 게이트 산화막을 요구하게 된다.In general DRAM (Dynamic Random Access Memory (DRAM)) process has used only a single gate oxide film for stability, but the demand for a DRAM that requires high-speed operation is increasingly required, a thin gate oxide film is required.
상기 얇은 게이트 산화막은 게이트 누설 전류의 증가를 가져오기 때문에 리프레쉬(Refresh) 특성이 중요한 DRAM 셀(Cell) 트랜지스터에는 사용상의 제약을 받게 된다.Since the thin gate oxide film increases the gate leakage current, the DRAM cell transistors in which the refresh characteristics are important are restricted in use.
상술한 두 가지 요구를 만족하기 위해서 주변 영역의 트랜지스터에 사용할 얇은 게이트 산화막과 셀 영역의 트랜지스터에 사용할 두꺼운 게이트 산화막을 동일 칩(chip)내에서 동시에 구현할 수 있는 듀얼 게이트 산화막 공정의 도입이 요구되었다.In order to satisfy the above two requirements, the introduction of a dual gate oxide film process capable of simultaneously implementing a thin gate oxide film for a transistor in a peripheral region and a thick gate oxide film for a transistor in a cell region in the same chip is required.
상기 듀얼 게이트 산화막 공정은 동일 웨이퍼 내에서 두께가 서로 다른 두 가지 종류의 게이트 산화막을 형성하는 공정으로서, 빠른 동작을 요구하는 코아(Core) 칩 부분과 신뢰성이 중요시되는 입/출력 블록(Block)으로 구성되는 회로 소자에서 일반적으로 사용하는 공정이다.The dual gate oxide film process is a process of forming two kinds of gate oxide films having different thicknesses in the same wafer. The dual gate oxide film process includes a core chip portion requiring fast operation and an input / output block where reliability is important. It is the process generally used by the circuit element comprised.
도 1a 내지 도 1f는 종래 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
그리고, 도 2는 듀얼, 싱글(Single) NMOS와 듀얼, 싱글 PMOS 각각의 문턱 전압을 나타낸 도면이고, 도 3은 듀얼, 싱글 PMOS의 채널 도핑 프로파일(Profile)을 나타낸 도면이다.FIG. 2 is a diagram illustrating threshold voltages of dual, single NMOS, and dual and single PMOS, and FIG. 3 is a diagram illustrating channel doping profiles of dual and single PMOS.
도 1a 내지 도 1g는 종래 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
종래 기술에 따른 반도체 소자의 제조 방법은 도 1a에서와 같이, 듀얼 게이트 산화막 공정에 있어서, DRAM 셀 트랜지스터가 형성될 부위인 제 1 영역(Ⅰ), 주변 영역의 NMOS가 형성될 부위인 제 2 영역(Ⅱ) 및 주변 영역의 PMOS가 형성될 부위인 제 3 영역(Ⅲ)이 각각 정의된 반도체 기판(11)을 준비한다.In the method of manufacturing a semiconductor device according to the related art, as shown in FIG. 1A, in a dual gate oxide film process, a first region (I) where a DRAM cell transistor is to be formed and a second region where a NMOS of a peripheral region are to be formed. The semiconductor substrate 11 in which (II) and the third region (III), which is the portion where the PMOS is formed, in the peripheral region is defined, is prepared, respectively.
그리고, 상기 소자분리 영역의 반도체 기판(11)에 일반적인 소자분리막 형성 공정으로 소자분리막(13)을 형성한 후, 전면에 제 1 감광막(15)을 도포한다.After the device isolation film 13 is formed on the semiconductor substrate 11 in the device isolation region by a general device isolation film forming process, the first photosensitive film 15 is coated on the entire surface.
이어, 상기 제 1 감광막(15)을 상기 제 1 영역(Ⅰ)에만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 1 감광막(15)을 마스크로 상기 제 1 영역(Ⅰ)의 반도체 기판(11)에 제 1 웰(Well) 형성 이온 및 문턱전압(Vth)조절이온(17)을 주입한다.Subsequently, after selectively exposing and developing the first photosensitive film 15 to be removed only in the first region I, the selectively exposed and developed first photosensitive film 15 is masked in the first region I. FIG. The first well forming ions and the threshold voltage (Vth) adjusting ions 17 are implanted into the semiconductor substrate 11.
도 1b에서와 같이, 상기 제 1 감광막(15)을 제거하고, 전면에 제 2 감광막(19)을 도포한다.As shown in FIG. 1B, the first photosensitive film 15 is removed and a second photosensitive film 19 is coated on the entire surface.
이어, 상기 제 2 감광막(19)을 상기 제 2 영역(Ⅱ)에만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 2 감광막(19)을 마스크로 상기 제 2 영역(Ⅱ)의 반도체 기판(11)에 제 2 웰 형성 이온 및 문턱전압 조절이온(21)을 주입한다.Subsequently, the second photoresist film 19 is selectively exposed and developed to be removed only in the second region II, and then the second exposed photoresist 19 is selectively exposed and developed using the second photoresist film 19 as a mask. Second well forming ions and threshold voltage adjusting ions 21 are implanted into the semiconductor substrate 11.
도 1c에서와 같이, 상기 제 2 감광막(19)을 제거하고, 전면의 열산화 공정으로 상기 반도체 기판(11)상에 패드(Pad) 산화막(23)을 성장시킨다.As shown in FIG. 1C, the second photosensitive layer 19 is removed, and a pad oxide layer 23 is grown on the semiconductor substrate 11 by a thermal oxidation process on the entire surface.
그리고, 상기 패드 산화막(23)을 포함한 전면에 제 3 감광막(25)을 도포한 후, 상기 제 3 감광막(25)을 상기 제 3 영역(Ⅲ)에만 제거되도록 선택적으로 노광 및 현상한다.After the third photosensitive film 25 is applied to the entire surface including the pad oxide film 23, the third photosensitive film 25 is selectively exposed and developed to be removed only in the third region III.
그 후, 상기 선택적으로 노광 및 현상된 제 3 감광막(25)을 마스크로 상기 제 3 영역(Ⅲ)의 반도체 기판(11)에 제 3 웰 형성 이온 및 문턱전압 조절이온(27)을 주입한다.Thereafter, the third well-forming ions and the threshold voltage adjusting ions 27 are implanted into the semiconductor substrate 11 of the third region III using the selectively exposed and developed third photosensitive film 25.
여기서, DRAM 셀 트랜지스터는 일반적으로 n+다결정 실리콘의 싱글 게이트 전극을 형성하기 때문에 주변 영역의 PMOS는 문턱전압 조절을 위하여 카운터 도핑을 실시하게 되어 버리드 채널(Buried channel)을 갖아 도 2에서와 같이, 표면 채널을 갖는 NMOS는 듀얼 게이트 산화막 공정과 싱글 게이트 산화막 공정에 대한 문턱전압 차이가 없지만 버리드 채널을 갖는 PMOS는 열 산화 공정에 대한 문턱전압의 변화가 크다.Here, since the DRAM cell transistor generally forms a single gate electrode of n + polycrystalline silicon, the PMOS in the peripheral region is counter-doped to adjust the threshold voltage, and has a buried channel as shown in FIG. 2. However, the NMOS having the surface channel has no difference in threshold voltage between the dual gate oxide process and the single gate oxide process, but the PMOS having the buried channel has a large change in the threshold voltage for the thermal oxidation process.
그리고 도 3에서와 같이, 상기 주변 영역의 PMOS는 오이디(Oxidation Enhanced Diffusion : OED)로 인하여 보론 로스(Boron loss)가 싱글 게이트 산화막공정보다 듀얼 게이트 산화막 공정에서 심하게 나타난다.As shown in FIG. 3, the PMOS of the peripheral region is more severe in boron loss than in a single gate oxide process due to OID.
도 1d에서와 같이, 상기 제 3 감광막(25)과 패드 산화막(23)을 제거하고, 전면의 열산화 공정으로 상기 반도체 기판(11)상에 제 1 게이트 산화막(29)을 성장시킨다.As shown in FIG. 1D, the third photosensitive film 25 and the pad oxide film 23 are removed, and the first gate oxide film 29 is grown on the semiconductor substrate 11 by a thermal oxidation process on the entire surface.
도 1e에서와 같이, 상기 제 1 게이트 산화막(29)을 포함한 전면에 제 4 감광막(31)을 도포하고, 상기 제 4 감광막(31)을 상기 제 1 영역(Ⅰ)에만 남도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 4 감광막(31)을 마스크로 상기 제 2 영역(Ⅱ)과 제 3 영역(Ⅲ)의 제 1 게이트 산화막(29)을 제거한다.As shown in FIG. 1E, a fourth photosensitive layer 31 is coated on the entire surface including the first gate oxide layer 29, and the exposure and development are selectively performed such that the fourth photosensitive layer 31 remains only in the first region I. After that, the first gate oxide layer 29 of the second region II and the third region III is removed using the selectively exposed and developed fourth photoresist layer 31 as a mask.
도 1f에서와 같이, 상기 제 4 감광막(31)을 제거하고, 전면의 열산화 공정으로 상기 반도체 기판(11)과 제 1 게이트 산화막(29)상에 제 2 게이트 산화막(33)을 성장시킨다.As shown in FIG. 1F, the fourth photoresist layer 31 is removed and a second gate oxide layer 33 is grown on the semiconductor substrate 11 and the first gate oxide layer 29 by a thermal oxidation process on the entire surface.
그리고, 상기 제 2 게이트 산화막(33)을 포함한 전면에 게이트 전극용 다결정 실리콘층(35)을 형성한다.A gate electrode polycrystalline silicon layer 35 is formed on the entire surface including the second gate oxide layer 33.
그러나 종래의 반도체 소자의 제조 방법은 듀얼 게이트 산화막 공정에 있어서, DRAM 셀 트랜지스터는 n+다결정 실리콘의 싱글 게이트 전극을 형성하기 때문에 주변 영역의 PMOS의 경우 문턱전압 조절을 위하여 카운터 도핑을 실시하게 되어 버리드 채널을 가지므로 열 산화 공정에 대한 문턱전압의 변화가 크고 보론 로스가 커 소자의 수율 및 신뢰성이 저하되는 문제점이 있었다.However, in the conventional semiconductor device manufacturing method, in the dual gate oxide film process, since the DRAM cell transistor forms a single gate electrode of n + polycrystalline silicon, in the case of PMOS in the peripheral region, counter doping is performed to adjust the threshold voltage. Since it has a hard channel, a large change in the threshold voltage for the thermal oxidation process and a large boron loss have a problem in that the yield and reliability of the device are deteriorated.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 듀얼 게이트 산화막 공정에 있어서, 주변 영역의 PMOS의 카운터 도핑 이온 주입 공정을 제 1 게이트 산화막 형성 공정과 제 2 게이트 산화막 형성 공정 사이에 진행하므로, 상기 주변 영역의 PMOS는 DRAM 셀 트랜지스터와 동일한 열 산화 공정이 진행되어 열 산화 공정에 대한 PMOS의 문턱전압 변화를 방지하고 OED로 인한 보론 로스를 억제하는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and in the dual gate oxide film process, the counter-doped ion implantation process of the PMOS in the peripheral region is performed between the first gate oxide film forming process and the second gate oxide film forming process. The PMOS in the peripheral area is subjected to the same thermal oxidation process as the DRAM cell transistor to prevent a change in the threshold voltage of the PMOS for the thermal oxidation process, and to provide a method for manufacturing a semiconductor device that suppresses boron loss due to OED.
도 1a 내지 도 1f는 종래 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2는 듀얼, 싱글 NMOS와 듀얼, 싱글 PMOS 각각의 문턱 전압을 나타낸 도면.2 is a diagram illustrating threshold voltages of dual, single NMOS, and dual and single PMOS, respectively.
도 3은 듀얼, 싱글 PMOS의 채널 도핑 프로파일을 나타낸 도면.3 shows channel doping profiles of dual, single PMOS.
도 4a 내지 도 4e는 본 발명의 실시 예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
41 : 반도체 기판 43 : 소자분리막41 semiconductor substrate 43 device isolation film
45 : 제 1 감광막 47 : 제 1 웰 형성 이온 및 문턱전압 조절이온45: first photosensitive film 47: first well-forming ion and threshold voltage control ion
49 : 제 2 감광막 51 : 제 2 웰 형성 이온 및 문턱전압 조절이온49: second photosensitive film 51: second well forming ion and threshold voltage control ion
53 : 제 1 게이트 산화막 55 : 제 3 감광막53: first gate oxide film 55: third photosensitive film
59 : 제 4 감광막 57 : 제 3 웰 형성 이온 및 문턱전압 조절이온59: fourth photosensitive film 57: third well forming ion and threshold voltage adjusting ion
61 : 제 2 게이트 산화막 63 : 다결정 실리콘층61 second gate oxide film 63 polycrystalline silicon layer
본 발명의 반도체 소자의 제조 방법은 DRAM 셀 트랜지스터가 형성되는 제 1 영역, 주변 영역의 NMOS가 형성되는 제 2 영역 및 주변 영역의 PMOS가 형성되는 제 3 영역이 각각 정의되며 소자분리막이 형성된 기판을 마련하는 단계, 상기 제 1 영역의 기판에 제 1 웰 형성 이온 및 문턱전압 조절이온을 주입하는 단계, 상기 제 2 영역의 기판에 제 2 웰 형성 이온 및 문턱전압 조절이온을 주입하는 단계, 상기 기판 상에 열산화 공정으로 제 1 게이트 산화막을 성장시키는 단계, 상기 제 3 영역의 기판에 제 3 웰 형성 이온 및 문턱전압 조절이온을 주입하는 단계, 상기 제 2 영역과 제 3 영역의 제 1 게이트 산화막을 제거하는 단계, 상기 기판과 제 1 게이트 산화막 상에 열산화 공정으로 제 2 게이트 산화막을 성장시키는 단계 및 상기 제 2 게이트 산화막을 포함한 전면에 게이트 전극용 다결정 실리콘층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of manufacturing a semiconductor device of the present invention, a first region in which a DRAM cell transistor is formed, a second region in which an NMOS is formed in a peripheral region, and a third region in which a PMOS is formed in a peripheral region are defined, respectively. Preparing, implanting first well forming ions and threshold voltage adjusting ions into a substrate of the first region, implanting second well forming ions and threshold voltage adjusting ions into the substrate of the second region, and Growing a first gate oxide film on the substrate in a thermal oxidation process, implanting a third well forming ion and a threshold voltage adjusting ion into a substrate of the third region, and first gate oxide films of the second region and the third region Removing a second layer; growing a second gate oxide layer on the substrate and the first gate oxide layer by a thermal oxidation process; and on the entire surface including the second gate oxide layer Including the step of forming a polycrystalline silicon layer for the electrode sites characterized by true.
상기와 같은 본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시 예를첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.
도 4a 내지 도 4e는 본 발명의 실시 예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
본 발명의 실시예에 따른 반도체 소자의 제조 방법은 도 4a에서와 같이, 듀얼 게이트 산화막 공정에 있어서, DRAM 셀 트랜지스터가 형성될 부위인 제 1 영역(Ⅰ), 주변 영역의 NMOS가 형성될 부위인 제 2 영역(Ⅱ) 및 주변 영역의 PMOS가 형성될 부위인 제 3 영역(Ⅲ)이 각각 정의된 반도체 기판(41)을 준비한다.In the method of manufacturing a semiconductor device according to the embodiment of the present invention, as shown in FIG. 4A, in the dual gate oxide film process, a region where the NMOS of the first region (I), which is the region where the DRAM cell transistor is to be formed, and the peripheral region, is to be formed The semiconductor substrate 41 in which the second region II and the third region III, which is a portion where the PMOS is to be formed, is defined.
그리고, 상기 소자분리 영역의 반도체 기판(41)에 일반적인 소자분리막 형성 공정으로 소자분리막(43)을 형성한 후, 전면에 제 1 감광막(45)을 도포한다.After the device isolation film 43 is formed on the semiconductor substrate 41 in the device isolation region by a general device isolation film forming process, the first photosensitive film 45 is coated on the entire surface.
이어, 상기 제 1 감광막(45)을 상기 제 1 영역(Ⅰ)에만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 1 감광막(45)을 마스크로 상기 제 1 영역(Ⅰ)의 반도체 기판(41)에 제 1 웰 형성 이온 및 문턱전압 조절이온(47)을 주입한다.Subsequently, after selectively exposing and developing the first photoresist film 45 to be removed only in the first region I, the selectively exposed and developed first photoresist film 45 is masked with the first region (I). First well forming ions and threshold voltage adjusting ions 47 are implanted into the semiconductor substrate 41.
도 4b에서와 같이, 상기 제 1 감광막(45)을 제거하고, 전면에 제 2 감광막(49)을 도포한다.As shown in FIG. 4B, the first photosensitive film 45 is removed and the second photosensitive film 49 is coated on the entire surface.
이어, 상기 제 2 감광막(49)을 상기 제 2 영역(Ⅱ)에만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 2 감광막(49)을 마스크로 상기 제 2 영역(Ⅱ)의 반도체 기판(41)에 제 2 웰 형성 이온 및 문턱전압 조절이온(51)을 주입한다.Subsequently, after selectively exposing and developing the second photoresist film 49 to be removed only in the second region II, the second photoresist film 49 is selectively exposed and developed using the second photoresist film 49 as a mask. The second well forming ions and the threshold voltage adjusting ions 51 are implanted into the semiconductor substrate 41.
도 4c에서와 같이, 상기 제 2 감광막(49)을 제거하고, 전면의 열산화 공정으로 상기 반도체 기판(41)상에 제 1 게이트 산화막(53)을 성장시킨다.As shown in FIG. 4C, the second photoresist film 49 is removed, and the first gate oxide film 53 is grown on the semiconductor substrate 41 by a thermal oxidation process of the entire surface.
그리고, 상기 제 1 게이트 산화막(53)을 포함한 전면에 제 3 감광막(55)을 도포한 후, 상기 제 3 감광막(55)을 상기 제 3 영역(Ⅲ)에만 제거되도록 선택적으로 노광 및 현상한다.After the third photoresist film 55 is coated on the entire surface including the first gate oxide film 53, the third photoresist film 55 is selectively exposed and developed to be removed only in the third region III.
그 후, 상기 선택적으로 노광 및 현상된 제 3 감광막(55)을 마스크로 상기 제 3 영역(Ⅲ)의 반도체 기판(41)에 제 3 웰 형성 이온 및 문턱전압 조절이온(57)을 주입한다.Thereafter, a third well-forming ion and a threshold voltage adjusting ion 57 are implanted into the semiconductor substrate 41 of the third region III using the selectively exposed and developed third photoresist film 55.
도 4d에서와 같이, 상기 제 3 감광막(55)을 제거하고, 상기 제 1 게이트 산화막(53)을 포함한 전면에 제 4 감광막(59)을 도포하고, 상기 제 4 감광막(59)을 상기 제 1 영역(Ⅰ)에만 남도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 4 감광막(59)을 마스크로 상기 제 2 영역(Ⅱ)과 제 3 영역(Ⅲ)의 제 1 게이트 산화막(53)을 제거한다.As shown in FIG. 4D, the third photoresist film 55 is removed, a fourth photoresist film 59 is applied to the entire surface including the first gate oxide film 53, and the fourth photoresist film 59 is applied to the first photoresist film 59. After selectively exposing and developing so as to remain only in the region (I), the first gate oxide film of the second region (II) and the third region (III) using the selectively exposed and developed fourth photoresist film 59 as a mask ( 53) Remove.
도 4e에서와 같이, 상기 제 4 감광막(59)을 제거하고, 전면의 열산화 공정으로 상기 반도체 기판(41)과 제 1 게이트 산화막(53)상에 제 2 게이트 산화막(61)을 성장시킨다.As shown in FIG. 4E, the fourth photoresist layer 59 is removed, and a second gate oxide layer 61 is grown on the semiconductor substrate 41 and the first gate oxide layer 53 by a thermal oxidation process on the entire surface.
그리고, 상기 제 2 게이트 산화막(61)을 포함한 전면에 게이트 전극용 다결정 실리콘층(63)을 형성한다.A gate electrode polycrystalline silicon layer 63 is formed on the entire surface including the second gate oxide layer 61.
본 발명의 반도체 소자의 제조 방법은 듀얼 게이트 산화막 공정에 있어서, 주변 영역의 PMOS의 카운터 도핑 이온 주입 공정을 제 1 게이트 산화막 형성 공정과 제 2 게이트 산화막 형성 공정 사이에 진행하므로, 상기 주변 영역의 PMOS는 DRAM 셀 트랜지스터와 동일한 열 산화 공정이 진행되어 열 산화 공정에 대한 PMOS의 문턱전압 변화를 방지하고 OED로 인한 보론 로스를 억제하여 소자의 수율 및 신뢰성을 향상시키고 또한 종래의 패드 산화막의 열 산화 공정을 생략하여 공정을 단순화시키는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention, in the dual gate oxide film process, the counter-doped ion implantation process of the PMOS in the peripheral region is performed between the first gate oxide film forming process and the second gate oxide film forming process, so that the PMOS of the peripheral region is The same thermal oxidation process as the DRAM cell transistor is performed to prevent the change of the threshold voltage of the PMOS for the thermal oxidation process, and to suppress boron loss due to the OED, thereby improving the yield and reliability of the device and the thermal oxidation process of the conventional pad oxide film. By omitting, there is an effect of simplifying the process.
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