CN112382562B - Method for improving photoresist morphology of ion implantation photoetching layer - Google Patents
Method for improving photoresist morphology of ion implantation photoetching layer Download PDFInfo
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- CN112382562B CN112382562B CN202011201722.5A CN202011201722A CN112382562B CN 112382562 B CN112382562 B CN 112382562B CN 202011201722 A CN202011201722 A CN 202011201722A CN 112382562 B CN112382562 B CN 112382562B
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- 238000000034 method Methods 0.000 title claims abstract description 161
- 238000005468 ion implantation Methods 0.000 title claims abstract description 158
- 229920002120 photoresistant polymer Polymers 0.000 title claims abstract description 103
- 238000001259 photo etching Methods 0.000 title claims abstract description 14
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000007789 gas Substances 0.000 claims abstract description 38
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 21
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000001301 oxygen Substances 0.000 claims abstract description 18
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 18
- 238000004026 adhesive bonding Methods 0.000 claims abstract description 10
- 231100000572 poisoning Toxicity 0.000 claims abstract description 10
- 230000000607 poisoning effect Effects 0.000 claims abstract description 10
- 238000002513 implantation Methods 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000004381 surface treatment Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 125000001475 halogen functional group Chemical group 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000007781 pre-processing Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 4
- 238000002203 pretreatment Methods 0.000 abstract 2
- 239000003292 glue Substances 0.000 description 6
- 230000008094 contradictory effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000004925 denaturation Methods 0.000 description 1
- 230000036425 denaturation Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
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Abstract
The invention discloses a method for improving the photoresist morphology of an ion implantation photoetching layer, which comprises the following steps: providing a semiconductor substrate needing ion implantation, wherein field oxygen is formed in the semiconductor substrate, a gate structure is formed on an active region, and a silicon nitride side wall is formed on the side surface of the gate structure; step two, pre-treatment before gluing is carried out, wherein the pre-treatment before gluing adopts synthesis gas or adopts mixed gas of synthesis gas and nitrogen to treat the surface of the semiconductor substrate; step three, performing a photoetching process, including photoresist gluing, exposure and development processes, and forming a photoresist pattern after development; step four, carrying out the ion implantation; and fifthly, removing the photoresist pattern. The invention can simultaneously eliminate the nitrogen poisoning influence of the silicon nitride side wall of the grid structure on the photoresist and the defect of bottom unfilled corner of the photoresist caused by different light emittance of the active region and the field oxygen, ensures the performance of the device, and has simple process and low cost.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for improving the photoresist morphology of an ion implantation lithography layer.
Background
In the mainstream process of integrated circuit manufacture, the grid side wall is usually made of silicon nitride material, while Photoresist (PR) is sensitive to nitrogen-containing material, PR denaturation is easy to cause chamfering (photoresist), and the purpose of solving the photoresist is usually achieved by O2 treatment before photoetching. However, the problem of bottom corner defect (unrercut) of PR due to poor flatness of SRAM region, which is caused by the difference of the reflectivity of Active Area (AA) and Shallow Trench Isolation (STI), becomes non-negligible at the technical node below 28nm, because it directly affects the region defined by Halo ion implantation, and thus device performance. While the use of an added anti-reflective coating (BARC) in the more advanced 14 nm FinFET technology may solve the PR topography problem, it also increases the process cost and complexity. Therefore, the PR unrercut problem is of great significance on the premise of not increasing the cost and the process complexity.
The prior art will now be described with reference to the accompanying drawings:
as shown in fig. 1A to 1C, the schematic views of the device structure in each step of the conventional process for forming an ion implantation process layer are shown; FIG. 2 is a photograph corresponding to FIG. 1C; the prior ion implantation process layer forming process method comprises the following steps:
step one, as shown in fig. 1A, a semiconductor substrate 101 requiring ion implantation is provided, field oxide 103 is formed in the semiconductor substrate 101, an active region is isolated in the semiconductor substrate 101 by the field oxide 103, a gate structure is formed on the active region, and a silicon nitride sidewall 107 is formed on a side surface of the gate structure.
Typically, the semiconductor substrate 101 comprises a silicon substrate.
A well region 102 is formed in the semiconductor substrate 101, and the active region is located in the corresponding well region 102. For PMOS, the well region 102 is an N-type well; for NMOS, the well region 102 is a P-type well.
The field oxide 103 is formed using a shallow trench isolation process.
The gate structure is formed by overlapping a gate dielectric layer 104 and a gate conductive material layer 105.
The gate dielectric layer 104 is a silicon dioxide layer. The gate dielectric layer 104 may be a high-k layer.
The gate conductive material layer 105 comprises a polysilicon gate. Typically, a top mask layer 106 is also formed on top of the gate conductive material layer 105.
The ion implantation is one of a lightly doped drain implantation, a halo implantation and a source drain implantation, and the ion implantation is self-aligned with the side surface of the silicon nitride sidewall 107.
Step two, as shown in fig. 1B, pre-glue pretreatment is performed, wherein the pre-glue pretreatment is shown by arrow lines corresponding to the marks 108, and oxygen is used for treating the surface of the semiconductor substrate 101; the pretreatment before the photoresist coating performs a surface treatment on the silicon nitride side wall 107 to prevent the silicon nitride material of the silicon nitride side wall 107 from causing nitrogen poisoning to the subsequent photoresist.
Step three, as shown in fig. 1C, a photolithography process is performed, including photoresist gumming, exposure and developing processes, and a photoresist pattern 109 is formed after developing, where the photoresist pattern 109 opens the ion implantation area.
It can be seen that the photoresist pattern 109 is prone to corner chipping, i.e., bottom corner chipping, in the bottom region as indicated by circle 110. As shown in fig. 2, which is a photograph corresponding to fig. 1C, it can be seen that the photoresist pattern 109 has unfilled corners in the bottom region shown by circle 110.
And fourthly, carrying out ion implantation, wherein in the ion implantation region, the ion implantation takes the side wall as a self-aligned boundary. Since the photoresist pattern 109 has a bottom unfilled corner, the ion implanted ions easily affect the bottom unfilled corner region, which may affect device performance.
And fifthly, removing the photoresist pattern 109.
Disclosure of Invention
The invention aims to provide a method for improving the appearance of photoresist of an ion implantation photoetching layer, which can simultaneously eliminate the nitrogen poisoning influence of a silicon nitride side wall of a grid structure on the photoresist and the defect that the photoresist generates a bottom unfilled corner due to different light emittance of an active region and field oxygen, can ensure the performance of a device, and has simple process and low cost.
In order to solve the above technical problems, the forming process of the first ion implantation process layer of the method for improving the photoresist morphology of the ion implantation photoetching layer provided by the invention comprises the following steps:
step one, providing a semiconductor substrate which needs to be subjected to ion implantation, wherein field oxygen is formed in the semiconductor substrate, an active region is isolated from the semiconductor substrate by the field oxygen, a grid structure is formed on the active region, and a silicon nitride side wall is formed on the side surface of the grid structure.
Step two, preprocessing before gluing, wherein the preprocessing before gluing adopts synthesis gas or mixed gas of synthesis gas and nitrogen to process the surface of the semiconductor substrate; the pretreatment before the photoresist coating is used for carrying out surface treatment on the silicon nitride side wall so as to prevent the silicon nitride material of the silicon nitride side wall from causing nitrogen poisoning to the subsequent photoresist, and simultaneously, the pretreatment before the photoresist coating is used for carrying out surface treatment on the active region and the field oxygen so as to prevent bottom unfilled corners of the photoresist caused by different light emittance of the active region and the field oxygen in photoetching.
And thirdly, performing a photoetching process, including photoresist gluing, exposure and development processes, and developing to form a photoresist pattern, wherein the photoresist pattern opens the ion implantation area.
And fourthly, carrying out ion implantation, wherein in the ion implantation region, the ion implantation takes the side wall as a self-aligned boundary.
And fifthly, removing the photoresist pattern.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
The field oxide is formed by adopting a shallow trench isolation process.
The grid structure is further improved by laminating a grid dielectric layer and a grid conductive material layer.
The further improvement is that the gate dielectric layer adopts a silicon dioxide layer or the gate dielectric layer adopts a high dielectric constant layer.
A further improvement is that the layer of gate conductive material comprises a polysilicon gate.
A further improvement is that the ion implantation is one of a lightly doped drain implantation, a halo implantation and a source drain implantation.
The semiconductor substrate is further improved in that the semiconductor substrate comprises a forming area of SRAM, and ion implantation of the forming area of the SRAM is achieved through the forming process of the first ion implantation process layer.
A further improvement is that the semiconductor substrate further comprises a logic device forming region; the surface flatness of the active region and the field oxide of the formation region of the logic device is better than the surface flatness of the active region and the field oxide of the formation region of the SRAM.
A further improvement is that the ion implantation of the forming region of the logic device is implemented by using the forming process of the first ion implantation process layer.
A further improvement is that the ion implantation of the formation region of the logic device is completed before the ion implantation of the formation region of the SRAM;
the ion implantation of the forming area of the logic device is realized by adopting a forming process of a second ion implantation process layer, and the process steps of the second ion implantation process layer and the first ion implantation process layer are different in that:
the first to fourth steps of the second ion implantation process layer forming process are the same as the first to fourth steps of the first ion implantation process layer forming process;
the fifth step of the second ion implantation process layer forming process is that: removing the photoresist pattern by using the synthesis gas or a mixed gas of the synthesis gas and nitrogen;
meanwhile, after the ion implantation of the forming area of the logic device is completed, omitting a second step when the ion implantation of the forming area of the SRAM is performed;
a further improvement is that the ion implantation of the formation region of the logic device is completed before the ion implantation of the formation region of the SRAM;
the ion implantation of the forming area of the logic device is realized by adopting a forming process of a second ion implantation process layer, the first, third and fourth steps of the forming process of the second ion implantation process layer are the same as the first, third and fourth steps of the forming process of the first ion implantation process layer, and the process steps of the second ion implantation process layer and the first ion implantation process layer are different from each other in that:
the second step of the forming process of the second ion implantation process layer is set as follows: treating the surface of the semiconductor substrate with oxygen;
the fifth step of the second ion implantation process layer forming process is that: removing the photoresist pattern by using the synthesis gas or a mixed gas of the synthesis gas and nitrogen;
meanwhile, after the ion implantation of the forming area of the logic device is completed, the second step is omitted when the ion implantation of the forming area of the SRAM is performed.
A further improvement is that the first ion implantation process layer forming process is applied to a technology node below 28 nm.
A further improvement is that the synthesis gas is a mixture of 96% N2 and 4% H2.
A further improvement is that well regions are formed in the semiconductor substrate, and the active regions are located in the corresponding well regions.
In the prior art, in order to eliminate the influence of nitrogen poisoning of the silicon nitride side wall, when oxygen pretreatment before gluing is introduced, the difference of the light emissivity of an active area and field oxygen is caused, and thus, the bottom unfilled corner of the photoresist is formed, so that the contradictory influence exists between the chamfer (corner) generated by eliminating nitrogen poisoning and the bottom unfilled corner of the photoresist.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIGS. 1A-1C are schematic views of a device structure at various steps in a conventional ion implantation process for forming an ion implantation process layer;
FIG. 2 is a photograph corresponding to FIG. 1C;
FIG. 3 is a flow chart of a method for improving photoresist profile of an ion implantation photoresist layer according to an embodiment of the invention;
FIGS. 4A-4C are schematic views of a device structure at various steps in a method for improving the photoresist profile of an ion implantation photoresist layer according to an embodiment of the present invention;
fig. 5 is a photograph corresponding to fig. 4C.
Detailed Description
FIG. 3 is a flow chart of a method for improving photoresist morphology in an ion implantation lithography layer according to an embodiment of the present invention; fig. 4A to 4C are schematic views of device structures in each step of a method for improving the photoresist morphology of an ion implantation photoresist layer according to an embodiment of the present invention; the first ion implantation process layer forming process of the method for improving the photoresist morphology of the ion implantation photoetching layer comprises the following steps:
step one, as shown in fig. 4A, a semiconductor substrate 1 requiring ion implantation is provided, field oxide 3 is formed in the semiconductor substrate 1, an active region is isolated from the field oxide 3 in the semiconductor substrate 1, a gate structure is formed on the active region, and a silicon nitride sidewall 7 is formed on a side surface of the gate structure.
In the embodiment of the present invention, the semiconductor substrate 1 includes a silicon substrate.
A well region 2 is formed in the semiconductor substrate 1, and the active region is located in the corresponding well region 2. For PMOS, the well region 2 is an N-type well; for NMOS, the well region 2 is a P-type well.
The field oxide 3 is formed by a shallow trench isolation process.
The gate structure is formed by superposing a gate dielectric layer 4 and a gate conductive material layer 5.
The gate dielectric layer 4 is a silicon dioxide layer. In other embodiments, the gate dielectric layer 4 is a high dielectric constant layer.
The gate conductive material layer 5 comprises a polysilicon gate. Typically, a top mask layer 6 is also formed on top of the gate conductive material layer 5.
The ion implantation is one of lightly doped drain implantation, halo implantation and source drain implantation, and the ion implantation is self-aligned with the side surface of the silicon nitride side wall 7.
Step two, as shown in fig. 4B, pre-glue pretreatment is performed, wherein the pre-glue pretreatment is shown by an arrow line corresponding to a mark 8, and the pre-glue pretreatment adopts synthesis gas or adopts mixed gas of synthesis gas and nitrogen to treat the surface of the semiconductor substrate 1; the pretreatment before the photoresist coating is used for carrying out surface treatment on the silicon nitride side wall 7 so as to prevent the nitrogen poisoning of the silicon nitride material of the silicon nitride side wall 7 on the subsequent photoresist, and simultaneously, the pretreatment before the photoresist coating is used for carrying out surface treatment on the active region and the field oxide 3 so as to prevent bottom unfilled corners of the photoresist caused by different light emittance of the active region and the field oxide 3 in the photoetching.
In the embodiment of the invention, the synthesis gas is a mixed gas of 96% of N2 and 4% of H2.
And step three, as shown in fig. 4C, performing a photolithography process including photoresist gumming, exposure and development processes, and forming a photoresist pattern 9 after development, wherein the photoresist pattern 9 opens the ion implantation region. It can be seen that the photoresist pattern 9 has good morphology and eliminates bottom unfilled corners. As shown in fig. 5, which is a photograph corresponding to fig. 4C, it can be seen that the photoresist pattern 9 has a good morphology.
And fourthly, carrying out ion implantation, wherein in the ion implantation region, the ion implantation takes the side wall as a self-aligned boundary.
And fifthly, removing the photoresist pattern 9.
In the embodiment of the invention, the forming process of the first ion implantation process layer is applied to the technical node below 28nm, for example, the embodiment of the invention can be applied to the ion implantation of the forming area of the SRAM of the technical node below 28nm, and can also be applied to the ion implantation of the SRAM and the logic device integrated simultaneously. The following will now be described respectively:
the first application is: the semiconductor substrate 1 includes a formation region of an SRAM, and ion implantation of the formation region of the SRAM is performed by using a formation process of the first ion implantation process layer. That is, the method of the embodiment of the invention is particularly suitable for ion implantation of the forming region of the SRAM.
The second application is: the semiconductor substrate 1 includes a formation region of an SRAM, and ion implantation of the formation region of the SRAM is performed by using a formation process of the first ion implantation process layer.
A formation region of a logic device is further included on the semiconductor substrate 1; the surface flatness of the active region of the formation region of the logic device and the field oxide 3 is better than the surface flatness of the active region of the formation region of the SRAM and the field oxide 3. Ion implantation of the forming region of the logic device is achieved by adopting the forming process of the first ion implantation process layer.
The third application is: the semiconductor substrate 1 includes a formation region of an SRAM, and ion implantation of the formation region of the SRAM is performed by using a formation process of the first ion implantation process layer.
A formation region of a logic device is further included on the semiconductor substrate 1; the surface flatness of the active region of the formation region of the logic device and the field oxide 3 is better than the surface flatness of the active region of the formation region of the SRAM and the field oxide 3.
Ion implantation of the formation region of the logic device is completed before ion implantation of the formation region of the SRAM; the ion implantation of the forming area of the logic device is realized by adopting a forming process of a second ion implantation process layer, and the process steps of the second ion implantation process layer and the first ion implantation process layer are different in that:
the first to fourth steps of the second ion implantation process layer forming process are the same as the first to fourth steps of the first ion implantation process layer forming process;
the fifth step of the second ion implantation process layer forming process is that: removing the photoresist pattern 9 by using the synthesis gas or a mixed gas of synthesis gas and nitrogen;
meanwhile, after the ion implantation of the forming region of the logic device is completed, the second step is omitted when the ion implantation of the forming region of the SRAM is performed, that is, the fifth step of the corresponding second ion implantation process layer of the forming region of the logic device is simultaneously used as the second step when the ion implantation of the forming region of the SRAM is performed.
The fourth application is: the semiconductor substrate 1 includes a formation region of an SRAM, and ion implantation of the formation region of the SRAM is performed by using a formation process of the first ion implantation process layer.
A formation region of a logic device is further included on the semiconductor substrate 1; the surface flatness of the active region of the formation region of the logic device and the field oxide 3 is better than the surface flatness of the active region of the formation region of the SRAM and the field oxide 3.
Ion implantation of the formation region of the logic device is completed before ion implantation of the formation region of the SRAM;
the ion implantation of the forming area of the logic device is realized by adopting a forming process of a second ion implantation process layer, the first, third and fourth steps of the forming process of the second ion implantation process layer are the same as the first, third and fourth steps of the forming process of the first ion implantation process layer, and the process steps of the second ion implantation process layer and the first ion implantation process layer are different from each other in that:
the second step of the forming process of the second ion implantation process layer is set as follows: treating the surface of the semiconductor substrate 1 by oxygen; that is, the same as the prior art method, but since the surfaces of the active region of the formation region of the logic device and the field oxide 3 are relatively flat, the bottom corner defect of the photoresist is not easily generated even with the prior art method.
The fifth step of the second ion implantation process layer forming process is that: removing the photoresist pattern 9 by using the synthesis gas or a mixed gas of synthesis gas and nitrogen;
meanwhile, after the ion implantation of the forming region of the logic device is completed, the second step is omitted when the ion implantation of the forming region of the SRAM is performed, that is, the fifth step of the corresponding second ion implantation process layer of the forming region of the logic device is simultaneously used as the second step when the ion implantation of the forming region of the SRAM is performed.
In the prior art, in order to eliminate the influence of nitrogen poisoning of the silicon nitride side wall 7, when oxygen pretreatment before glue coating is introduced, the light emissivity of the active area and the light emissivity of the field oxide 3 are different, and thus, the bottom unfilled corner of the photoresist is formed, so that the contradictory influence exists between the chamfer generated by eliminating nitrogen poisoning and the bottom unfilled corner of the photoresist.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (14)
1. The method for improving the photoresist morphology of the ion implantation photoetching layer is characterized in that the forming process of the first ion implantation process layer comprises the following steps:
providing a semiconductor substrate needing ion implantation, forming field oxygen in the semiconductor substrate, isolating an active region in the semiconductor substrate by the field oxygen, forming a gate structure on the active region, and forming a silicon nitride side wall on the side surface of the gate structure;
step two, preprocessing before gluing, wherein the preprocessing before gluing adopts synthesis gas or mixed gas of synthesis gas and nitrogen to process the surface of the semiconductor substrate; the pretreatment before the photoresist coating is used for carrying out surface treatment on the silicon nitride side wall so as to prevent nitrogen poisoning of a silicon nitride material of the silicon nitride side wall on subsequent photoresist, and simultaneously, the pretreatment before the photoresist coating is used for carrying out surface treatment on the active region and the field oxygen so as to prevent bottom unfilled corners of the photoresist caused by different light emittance of the active region and the field oxygen in photoetching;
the synthesis gas is a mixed gas of 96% of N2 and 4% of H2;
step three, performing a photoetching process, which comprises photoresist gluing, exposure and development processes, and forming a photoresist pattern after development, wherein the photoresist pattern opens an ion implantation area;
step four, carrying out ion implantation, wherein in the ion implantation region, the ion implantation takes the side wall as a self-aligned boundary;
and fifthly, removing the photoresist pattern, and removing the photoresist pattern by adopting the synthesis gas or adopting the mixed gas of the synthesis gas and the nitrogen.
2. The method of improving the photoresist morphology of an ion implantation photoresist layer of claim 1, wherein: the semiconductor substrate includes a silicon substrate.
3. The method of improving the photoresist morphology of an ion implantation photoresist layer of claim 2, wherein: the field oxide is formed by adopting a shallow trench isolation process.
4. The method of improving the photoresist morphology of an ion implantation photoresist layer of claim 1, wherein: the grid structure is formed by laminating a grid dielectric layer and a grid conductive material layer.
5. The method for improving the photoresist morphology of an ion implantation photoresist layer as defined in claim 4, wherein: the gate dielectric layer adopts a silicon dioxide layer or the gate dielectric layer adopts a high dielectric constant layer.
6. The method for improving the photoresist morphology of an ion implantation photoresist layer according to claim 4 or 5, wherein: the gate conductive material layer includes a polysilicon gate.
7. The method for improving the photoresist morphology of an ion implantation photoresist layer according to claim 1 or 2, wherein: the ion implantation is one of lightly doped drain implantation, halo implantation and source drain implantation.
8. The method for improving the photoresist morphology of an ion implantation photoresist layer according to claim 1 or 2, wherein: and forming an SRAM forming area on the semiconductor substrate, wherein the ion implantation of the SRAM forming area is realized by adopting the forming process of the first ion implantation process layer.
9. The method of improving the photoresist morphology of an ion implantation photoresist layer of claim 8, wherein: a forming region of a logic device is further included on the semiconductor substrate; the surface flatness of the active region and the field oxide of the formation region of the logic device is better than the surface flatness of the active region and the field oxide of the formation region of the SRAM.
10. The method of improving the photoresist morphology of an ion implantation photoresist layer of claim 9, wherein: ion implantation of the forming region of the logic device is achieved by adopting the forming process of the first ion implantation process layer.
11. The method of improving the photoresist morphology of an ion implantation photoresist layer of claim 9, wherein: ion implantation of the formation region of the logic device is completed before ion implantation of the formation region of the SRAM;
the ion implantation of the forming area of the logic device is realized by adopting a forming process of a second ion implantation process layer, and the process steps of the second ion implantation process layer and the first ion implantation process layer are different in that:
the first to fourth steps of the second ion implantation process layer forming process are the same as the first to fourth steps of the first ion implantation process layer forming process;
the fifth step of the second ion implantation process layer forming process is that: removing the photoresist pattern by using the synthesis gas or a mixed gas of the synthesis gas and nitrogen;
meanwhile, after the ion implantation of the forming area of the logic device is completed, the second step is omitted when the ion implantation of the forming area of the SRAM is performed.
12. The method of improving the photoresist morphology of an ion implantation photoresist layer of claim 9, wherein: ion implantation of the formation region of the logic device is completed before ion implantation of the formation region of the SRAM;
the ion implantation of the forming area of the logic device is realized by adopting a forming process of a second ion implantation process layer, the first, third and fourth steps of the forming process of the second ion implantation process layer are the same as the first, third and fourth steps of the forming process of the first ion implantation process layer, and the process steps of the second ion implantation process layer and the first ion implantation process layer are different from each other in that:
the second step of the forming process of the second ion implantation process layer is set as follows: treating the surface of the semiconductor substrate with oxygen;
the fifth step of the second ion implantation process layer forming process is that: removing the photoresist pattern by using the synthesis gas or a mixed gas of the synthesis gas and nitrogen;
meanwhile, after the ion implantation of the forming area of the logic device is completed, the second step is omitted when the ion implantation of the forming area of the SRAM is performed.
13. The method of improving the photoresist morphology of an ion implantation photoresist layer of claim 1, wherein: the formation process of the first ion implantation process layer is applied to a technology node below 28 nm.
14. The method of improving the photoresist morphology of an ion implantation photoresist layer of claim 1, wherein: a well region is formed in the semiconductor substrate, and the active region is located in the corresponding well region.
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| JP2000208638A (en) * | 1999-01-12 | 2000-07-28 | Hyundai Electronics Ind Co Ltd | Double gate forming method for semiconductor element |
| CN109712872A (en) * | 2018-12-29 | 2019-05-03 | 上海华力集成电路制造有限公司 | Enhance the method for semiconductor devices ion implanting lithographic process window |
| CN110854075A (en) * | 2019-11-13 | 2020-02-28 | 上海华力集成电路制造有限公司 | CMOS device manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000208638A (en) * | 1999-01-12 | 2000-07-28 | Hyundai Electronics Ind Co Ltd | Double gate forming method for semiconductor element |
| CN109712872A (en) * | 2018-12-29 | 2019-05-03 | 上海华力集成电路制造有限公司 | Enhance the method for semiconductor devices ion implanting lithographic process window |
| CN110854075A (en) * | 2019-11-13 | 2020-02-28 | 上海华力集成电路制造有限公司 | CMOS device manufacturing method |
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