KR100554201B1 - Manufacturing method of CDMOS - Google Patents

Manufacturing method of CDMOS Download PDF

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KR100554201B1
KR100554201B1 KR1019990010793A KR19990010793A KR100554201B1 KR 100554201 B1 KR100554201 B1 KR 100554201B1 KR 1019990010793 A KR1019990010793 A KR 1019990010793A KR 19990010793 A KR19990010793 A KR 19990010793A KR 100554201 B1 KR100554201 B1 KR 100554201B1
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high voltage
region
photoresist pattern
drain
nmos
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KR20000061623A (en
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이순학
김용돈
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페어차일드코리아반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region

Abstract

본 발명은 반도체 소자에 관한 것으로, 특히 디모스(DMOS) 소자와 씨모스(CMOS) 소자를 결합시킨 씨디모스 제조 방법에 관한 것이다. 본 발명의 일 실시예에 의한 씨디모스 제조방법은, 실리콘 기판의 엘디모스와, 고전압 피모스 및 엔모스, 저전압 피모스 및 엔모스 영역에 N웰과 P웰을 형성하는 단계와, 상기 실리콘 기판 상에 질화막을 형성한 후 제1 포토레지스트 패턴을 이용하여 이를 식각하고, 계속해서 N형의 불순물을 이온주입하여 엘디모스의 드리프트와, 고농도 엔모스의 저농도 소오스/ 드레인과, 고전압 피모스와 저전압 피모스의 필드 디플리션 P-채널 영역을 동시에 형성하는 단계와, 상기 제1 포토레지스트 패턴을 제거한 후 제2 포토레지스트 패턴을 형성하고, 계속해서 P형의 불순물을 이온주입을 행하여 고전압 피모스의 저농도 소오스/ 드레인과, 고전압 엔모스와 저전압 엔모스의 필드 디플리션 N-채널 영역을 형성하는 단계를 구비하는 것을 특징으로 한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a CDMOS in which a DMOS device and a CMOS device are combined. According to an embodiment of the present disclosure, a method for manufacturing a CDMOS includes forming N wells and P wells in an ELDIMOS, high voltage PMOS and NMOS, low voltage PMOS, and NMOS regions of a silicon substrate, and the silicon substrate. After the nitride film is formed on the substrate, it is etched using a first photoresist pattern, followed by ion implantation of an N-type impurity to drift the ELDIMOS, the low concentration source / drain of the high concentration NMOS, the high voltage PMOS and the low voltage P Simultaneously forming the field depletion P-channel region of Morse, removing the first photoresist pattern, and forming a second photoresist pattern, followed by ion implantation of P-type impurities And forming a field depletion N-channel region of low concentration source / drain and high voltage and low voltage enmos.

Description

씨디모스 제조방법{Manufacturing method of CDMOS}Manufacturing method of CDMOS

도 1 내지 도 11은 본 발명의 일 실시예에 의한 씨디모스(CDMOS) 제조 방법을 공정순서별로 설명하기 위해 도시한 단면도들이다.1 to 11 are cross-sectional views illustrating a CDMOS manufacturing method according to an embodiment of the present invention by process order.

본 발명은 반도체 소자에 관한 것으로, 특히 디모스(DMOS) 소자와 씨모스(CMOS) 소자를 결합시킨 씨디모스 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a CDMOS in which a DMOS device and a CMOS device are combined.

디모스(Double diffused MOS)와 고전압 및 저전압의 씨모스(Complementary MOS)를 결합시킨 씨디모스를 제조하는 과정에 있어서, 기존에는 여러 가지 공정적인 어려움과 특성적인 문제로 인해 사용되는 사진 공정 수가 많고 기타공정이 복잡해짐으로써 제조원가가 증가되었다.In the process of manufacturing CDMOS combining double diffused MOS and high voltage and low voltage CMOS, the number of photographic processes used in the past is high due to various process difficulties and characteristic problems. The complexity of the process has increased manufacturing costs.

본 발명의 목적은 공정을 단순화하면서도 전기적 특성은 기존의 수준을 유지할 수 있는 씨디모스 제조 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a CDMOS manufacturing method which can simplify the process while maintaining the existing level of electrical characteristics.

상기 목적을 달성하기 위한, 본 발명의 일 실시예에 의한 씨디모스 제조방법 은, 실리콘 기판의 엘디모스와, 고전압 피모스 및 엔모스, 저전압 피모스 및 엔모스 영역에 N웰과 P웰을 형성하는 단계와, 상기 실리콘 기판 상에 질화막을 형성한 후 제1 포토레지스트 패턴을 이용하여 이를 식각하고, 계속해서 N형의 불순물을 이온주입하여 엘디모스의 드리프트와, 고농도 엔모스의 저농도 소오스/ 드레인과, 고전압 피모스와 저전압 피모스의 필드 디플리션 P-채널 영역을 동시에 형성하는 단계와, 상기 제1 포토레지스트 패턴을 제거한 후 제2 포토레지스트 패턴을 형성하고, 계속해서 P형의 불순물을 이온주입을 행하여 고전압 피모스의 저농도 소오스/ 드레인과, 고전압 엔모스와 저전압 엔모스의 필드 디플리션 N-채널 영역을 형성하는 단계를 구비하는 것을 특징으로 한다. In order to achieve the above object, a CDMOS manufacturing method according to an embodiment of the present invention includes forming N wells and P wells in an ELDMOS, high voltage PMOS and NMOS, low voltage PMOS and NMOS regions of a silicon substrate. And forming a nitride film on the silicon substrate, and then etching the same using a first photoresist pattern, followed by ion implantation of N-type impurities to drift the ELDMOS and the low concentration source / drain of the high concentration NMOS. And simultaneously forming a field depletion P-channel region of a high voltage PMOS and a low voltage PMOS, removing the first photoresist pattern, and then forming a second photoresist pattern, and subsequently ionizing P-type impurities. Performing implantation to form a low concentration source / drain of the high voltage PMOS, and a field depletion N-channel region of the high voltage NMOS and low voltage EnMOS; It features.

이때, 상기 제1 포토레지스트 패턴은 엘디모스의 드리프트 영역, 고전압 피모스의 저농도 소오스/ 드레인과 에프디피 영역, 고전압 엔모스의 저농도 소오스/ 드레인과, 에프디엔 영역, 저전압 피모스의 에프디피 영역 및 저전압 엔모스의 에프디엔 영역을 노출시키는 모양이고, 상기 제2 포토레지스트 패턴은 고전압 피모스의 저농도 소오스/ 드레인과, 고전압 엔모스의 에프디엔 영역과, 저전압 엔모스의 에프디엔 영역을 노출시키는 모양이다.In this case, the first photoresist pattern may include a drift region of an ELDIMOS, a low concentration source / drain and an FDPI region of a high voltage PMOS, a low concentration source / drain of a high voltage NMOS, an FDI region, an FDPI region of a low voltage PMOS, The second photoresist pattern is configured to expose a low voltage source / drain of a high voltage PMOS, an Fdiene region of a high voltage NMOS, and an Fdiene region of a low voltage NMOS. to be.

또한, 상기 필드 디플리션 N-채널 영역을 형성하는 단계 후, 기판 전면에 게이트 산화막과 다결정실리콘막을 형성한 후 제3 포토레지스트 패턴을 이용하여 상기 다결정실리콘막을 사진/ 식각한 후 이온주입하여 엘디모스의 P 바디와 고전압 피모스의 소오스/ 드레인을 형성하는 단계와, 상기 제3 포토레지스트 패턴을 제거한 후 기판 전면에 문턱전압 조절용 불순물을 주입하는 단계를 더 구비한다.In addition, after the forming of the field depletion N-channel region, a gate oxide film and a polysilicon film are formed on the entire surface of the substrate, and the photonic crystal is photographed / etched using a third photoresist pattern, followed by ion implantation. And forming a source / drain of the P body of the MOS and the source / drain of the high voltage PMOS, and injecting impurities for adjusting the threshold voltage on the entire surface of the substrate after removing the third photoresist pattern.

따라서, 본 발명에 의하면, 하나의 마스크를 이용하여 필드 디플리션 N- 채널 영역과 필드 디플리션 P- 채널 영역을 형성할 수 있으므로 공정을 단순화할 수 있다.Therefore, according to the present invention, since the field depletion N-channel region and the field depletion P-channel region can be formed using one mask, the process can be simplified.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되어지는 것이다. 따라서, 도면에서의 요소의 형상 등은 보다 명확한 설명을 강조하기 위해서 과장되어진 것이며, 도면 상에서 동일한 부호로 표시된 요소는 동일한 요소를 의미한다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.

도 1 내지 도 11은 본 발명의 일 실시예에 의하 씨디모스 제조 방법을 공정순서별로 설명하기 위해 도시한 단면도들이다.1 to 11 are cross-sectional views illustrating a method for manufacturing CDMOS according to an embodiment of the present invention for each process sequence.

먼저, 도 1을 참조하면, 농고가 낮은 P형 실리콘 기판(10) 표면에 얇은 산화막(12)을 생성하고 이 전면 상에 제1 질화막(14)을 증착한 후, 상기 제1 질화막(14) 전면 상에 제1 포토레지스트막을 도포한다. 이후, 상기 제1 포토레지스트막을 사진 현상하여 엘디엔모스 영역("LDNMOS"로 표시), 고전압 피모스(High Voltage PMOS; "HVPMOS"로 표시) 영역, 저전압 피모스 (low voltage PMOS; "PMOS"로 표시) 영역의 질화막을 노출시키는 제1 포토레지스트 패턴(16)을 형성한 후, 이를 식각마스크로 하여 노출되어 있는 제1 질화막을 패터닝함으로써 제1 질화막 패턴(14)을 형성한다. 이어서, N형의 불순물(18)을 저농도로, 예컨대 1∼20E12 이온/ ㎠의 도우즈로 주입하여 상기 엘디모스 영역과 고전압 피모스 영역과, 저전압 피모스 영역에 각각 N웰 주입층(20a)을 형성한다.First, referring to FIG. 1, a thin oxide film 12 is formed on a surface of a low-pitched P-type silicon substrate 10, and a first nitride film 14 is deposited on the entire surface thereof, followed by the first nitride film 14. The first photoresist film is coated on the entire surface. Thereafter, the first photoresist film is photo-developed to display an ElDienmos region (denoted as "LDNMOS"), a High Voltage PMOS (denoted as "HVPMOS") region, and a low voltage PMOS ("PMOS"). After forming the first photoresist pattern 16 exposing the nitride film in the region, the first nitride film pattern 14 is formed by patterning the exposed first nitride film as an etching mask. Subsequently, the N type impurity 18 is implanted at a low concentration, for example, in a dose of 1 to 20E12 ions / cm 2, and the N well implanted layer 20a is respectively applied to the Eldimos region, the high voltage PMOS region, and the low voltage PMOS region. To form.

도 2를 참조하면, 상기 제1 포토레지스트 패턴을 제거하고, 부분적인 산화공정(LOCOS)을 진행하여 상기 엘디엔모스 영역과, 고전압 피모스 영역과, 저전압 피모스 영역 각각에 필드 산화막(22)을 형성한 후, 상기 제1 질화막 패턴(도 1의 14)을 제거한다. 이어서, 결과물 기판 전면에 P형 불순물(24)을, 예컨대 1∼20E12 이온/㎠의 도우즈로 주입하여 분리영역 ("ISO"로 표시), 고전압 엔모스 (High Voltage NMOS; "HVNMOS"라 표시) 영역 및 저전압 엔모스 (low voltage NMOS; "NMOS"로 표시) 영역에 P웰 주입층(26a)을 형성한다. 이때, 상기 필드 산화막(22)은, 예컨대 1,000Å ∼ 10,000Å의 두께로 형성하며, 상기 P웰 주입층(26a)은 상기 필드 산화막(22)에 자기정합되게 형성된다.Referring to FIG. 2, the first photoresist pattern is removed and a partial oxidation process (LOCOS) is performed to fill the field oxide layer 22 in each of the ELDMOS region, the high voltage PMOS region, and the low voltage PMOS region. After the formation, the first nitride film pattern 14 of FIG. 1 is removed. Subsequently, a P-type impurity 24 is implanted into the entire surface of the resultant substrate, for example, with a dose of 1 to 20E12 ions / cm 2 to indicate a separation region (denoted by "ISO") and a high voltage NMOS ("HVNMOS"). P-well injection layer 26a is formed in the < RTI ID = 0.0 >) region and low voltage NMOS (" NMOS ") region. At this time, the field oxide film 22 is formed to have a thickness of, for example, 1,000 kPa to 10,000 kPa, and the P well injection layer 26a is formed to be self-aligned to the field oxide film 22.

도 3을 참조하면, 상기 N웰 주입층(도 2의 20a) 및 P웰 주입층(도 2의 26a) 내의 불순물을 확산시켜 N웰(20) 및 P웰(26)을 형성하고, 결과물 기판 전면에 제2 질화막과 제2 포토레지스트막을 차례대로 증착한다. 이후, 상기 제2 포토레지스트막을 사진 현상하여 제2 포토레지스트 패턴(32)을 형성하고, 이 제2 포토레지스트 패턴(32)을 마스크로한 식각공정으로 상기 제2 질화막을 패터닝함으로써 제2 질화막 패턴(30)을 형성한다. 이때, 상기 제2 질화막 패턴(30)은 각 고전압 피모스와 저전압 피모스의 N웰(20)의 가장자리부분과, 고전압 엔모스와 저전압 엔모스의 P웰(26)의 가장자리부분과, 분리영역의 P웰(26) 전체와, 엘디엔모스의 드리프트 영역이 형성될 부분을 노출시키는 창을 갖는 모양으로 형성된다. 계속해서, 상기 제2 질화막 패턴(30)이 형성되어 있는 결과물 기판 전면에 N형의 불순물(34)을, 예컨대 1∼20E13 이온/㎠의 도우즈로 주입함으로써 N형 주입층(36)을 형성한다. Referring to FIG. 3, impurities in the N well injection layer (20a of FIG. 2) and the P well injection layer (26a of FIG. 2) are diffused to form an N well 20 and a P well 26, and a resultant substrate. A second nitride film and a second photoresist film are sequentially deposited on the entire surface. Thereafter, the second photoresist film is photographed to form a second photoresist pattern 32, and the second nitride film pattern is patterned by an etching process using the second photoresist pattern 32 as a mask. 30 is formed. In this case, the second nitride film pattern 30 may include an edge portion of the N well 20 of each of the high voltage PMOS and the low voltage PMOS, an edge portion of the P well 26 of the high voltage NMOS and the low voltage NMOS, and an isolation region. It is formed in a shape having a window that exposes the entire P well 26 and the portion where the drift region of the ELD is to be formed. Subsequently, an N-type implantation layer 36 is formed by injecting an N-type impurity 34 into a dose of 1 to 20E13 ions / cm 2, for example, on the entire surface of the resultant substrate on which the second nitride film pattern 30 is formed. do.

도 4를 참조하면, 상기 제2 포토레지스트 패턴(도 3의 32)을 제거한 후, 제3 포토레지스트막을 도포하고 이를 사진 현상함으로써 분리영역(ISO)의 P웰(26), 고전압 피모스의 저농도 소오스/ 드레인 영역, 고전압 엔모스의 P웰(26)의 가장자리부분 및 저전압 엔모스의 P웰(26)의 가장자리부분을 노출시키는 창을 갖는 제3 포토레지스트 패턴(38)을 형성한다. 이후, 상기 제3 포토레지스트 패턴(38)을 마스크로 하여 P형의 불순물(40)을, 예컨대 1∼20E13 이온/㎠의 도우즈로 주입함으로써 P형 주입층(42)을 형성한다.Referring to FIG. 4, after removing the second photoresist pattern (32 in FIG. 3), a third photoresist film is coated and photographed to develop a low concentration of the P well 26 and the high voltage PMOS of the isolation region ISO. A third photoresist pattern 38 having a source / drain region, an edge portion of the P well 26 of the high voltage NMOS and an edge portion of the P well 26 of the low voltage NMOS is formed. Thereafter, the P-type implantation layer 42 is formed by injecting a P-type impurity 40 into a dose of, for example, 1 to 20E13 ions / cm 2 using the third photoresist pattern 38 as a mask.

도 5를 참조하면, 상기 제3 포토레지스트 패턴(도 4의 38)을 제거하고, 상기 제2 질화막 패턴(도 4의 30)을 마스크로한 산화공정을 실시함으로써 상기 제2 질화막 패턴에 의해 노출된 영역에 필드 산화막(44)을 형성한 후, 상기 제2 질화막 패턴을 제거한다. 상기 산화 공정 시 제공되는 열에너지에 의해, 상기 N형 주입층(도 3의 36)과 P형 주입층(도 4의 42) 내의 불순물이 확산하여 엘디엔모스 영역에는 드리프트 영역(36a 및 36b)을, 분리영역(ISO)엔 저농도 P웰(42)을, 고전압 피모스 영역에는 저농도 P- 소오스/ 드레인(42b)과 N웰(20)의 가장자리에 형성되는 레프디피(Field Depletion P-channel; FDP) (36c)를, 고전압 엔모스 영역에는 저농도 N- 소오스/ 드레인(36d)과 P웰(26)의 가장자리에 형성되는 에프디엔(Field Depletion N-channel) (42c)을, 저전압 피모스 영역에는 N웰(20)의 가장자리에 형성되는 에프디피(36c)을, 저전압 엔모스 영역에는 P웰(26)의 가장자리에 형성되는 에프디엔(42d)을 형성한다.Referring to FIG. 5, the third photoresist pattern (38 in FIG. 4) is removed and the second nitride film pattern (30 in FIG. 4) is subjected to an oxidation process using a mask to expose the second nitride film pattern. After the field oxide film 44 is formed in the region, the second nitride film pattern is removed. Due to the thermal energy provided during the oxidation process, impurities in the N-type injection layer (36 in FIG. 3) and the P-type injection layer (42 in FIG. 4) diffuse to form drift regions 36a and 36b in the ELDIMOS region. In the isolation region ISO, a low concentration P well 42 is formed, and in the high voltage PMOS region, a low concentration P- source / drain 42b and a field depletion P-channel (FDP) formed at the edge of the N well 20 are formed. (36c), a low concentration N- source / drain (36d) and a field depletion N-channel (42c) formed at the edge of the P well 26 in the high voltage NMOS region, the low voltage PMOS region The FD36c formed at the edge of the N well 20 is formed, and the FDN42d formed at the edge of the P well 26 is formed in the low voltage NMOS region.

이후, 제2 질화막 패턴(도 4의 30)을 제거하고, 게이트 산화막(46)을 100Å ∼ 1,000Å 정도의 두께로 형성한 후, 다결정실리콘을 1,000Å ∼ 10,000Å 정도의 두께로 증착하여 다결정실리콘막(48)을 형성한다.Thereafter, the second nitride film pattern (30 in FIG. 4) is removed, and the gate oxide film 46 is formed to a thickness of about 100 kPa to about 1,000 kPa, and then polycrystalline silicon is deposited to a thickness of about 1,000 kPa to about 10,000 kPa. A film 48 is formed.

도 6을 참조하면, 상기 다결정실리콘막(48) 상에 제4 포토레지스트막을 도포한 후 이를 사진 현상하여 제4 포토레지스트 패턴(66)을 형성한 후, 상기 제4 포토레지스트 패턴(66)을 마스크로 한 사진/식각 공정을 통해서 상기 다결정실리콘막을 패터닝함으로써 엔디엔모스의 P 바디가 형성될 부분과 고전압 피모스의 소오스/ 드레인이 형성될 부분을 노출시키는 다결정실리콘 패턴(48)을 형성한다. 이후, 상기 제4 포토레지스트 패턴(66)과 다결정실리콘 패턴(48)을 마스크로하여 P형의 불순물(68)을 주입함으로써 상기 엔디엔모스의 P 바디가 형성될 부분과 고전압 엔모스의 소오스/ 드레인이 형성된 부분에 P형 주입층(70)을 각각 형성한다.Referring to FIG. 6, after the fourth photoresist film is coated on the polysilicon film 48, photodevelopment is performed to form the fourth photoresist pattern 66, and then the fourth photoresist pattern 66 is formed. The polysilicon film is patterned through a photolithography process using a mask to form a polysilicon pattern 48 that exposes a portion where the P body of the endian MOS is to be formed and a portion where the source / drain of the high voltage PMOS is to be formed. Subsequently, a P-type impurity 68 is implanted using the fourth photoresist pattern 66 and the polysilicon pattern 48 as a mask to form a portion of the P body of the N & DMOS and a source / high voltage source of the NMOS. P-type injection layers 70 are formed in portions where the drains are formed.

도 7을 참조하면, 상기 제4 포토레지스트 패턴(도 6의 66)을 제거한 후, 결과물 전면에 문턱전압 조절용 불순물(72)을 이온주입함으로써 각 소자 영역에 문턱전압 조절용 불순물층(74)을 형성한다. 이때, 상기 문턱전압 조절용 불순물(72)은 다결정실리콘 패턴(48)과 게이트 산화막(46)을 통과하여 주입되며, 필드 산호막(44)이 형성되어 있는 부분에는 주입되지 않는다.Referring to FIG. 7, after removing the fourth photoresist pattern (66 of FIG. 6), the impurity layer 74 for threshold voltage adjustment is formed in each device region by ion implanting the impurity voltage for controlling the threshold voltage 72 on the entire surface of the resultant. do. At this time, the threshold voltage adjusting impurity 72 is injected through the polysilicon pattern 48 and the gate oxide film 46, and is not injected into the portion where the field coral film 44 is formed.

도 6 및 도 7에서 설명한 방법으로 엔디엔모스의 P 바디 및 고전압 피모스의 소오스/ 드레인 형성을 위한 이온주입과 문턱전압 조절을 위한 이온주입을 행하면 한번의 사진공정을 생략할 수 있으며, 가장 문제가 되는 엔디엔모스 소자의 드리프 트 영역은 에피디피에 의해 열화를 방지할 수 있다.6 and 7 can be omitted by performing ion implantation for forming the source / drain of the P body and the high voltage PMOS of the endian MOS and ion implantation for adjusting the threshold voltage. The drift region of the endian < RTI ID = 0.0 > enMOS element < / RTI >

도 8을 참조하면, 상기 다결정실리콘 패턴(도 7의 48)을 게이트 전극 형성용 제5 포토레지스트 패턴(76)을 마스크로 이용한 사진 식각공정을 통해 패터닝함으로써 엔디엔모스의 게이트 전극(48a)과, 고전압 피모스의 게이트 전극(48b)과, 고전압 엔모스의 게이트 전극(48c)과, 저전압 피모스의 게이트 전극(48d)과, 저전압 엔모스의 게이트 전극(48e)을 형성한다.Referring to FIG. 8, the polysilicon pattern 48 of FIG. 7 is patterned by a photolithography process using a fifth photoresist pattern 76 for forming a gate electrode as a mask to form a gate electrode 48a of the endenmos. The gate electrode 48b of the high voltage PMOS, the gate electrode 48c of the high voltage NMOS, the gate electrode 48d of the low voltage PMOS, and the gate electrode 48e of the low voltage PMOS are formed.

도 9를 참조하면, 상기 제5 포토레지스트 패턴(도 8의 76)을 제거한 후, 불순물이 도우프되지 않은 산화막(undoped oxide)을 도포한 후 이를 이방성식각하여 각 게이트 전극들(48a,b,c,d 및 e)의 측벽에 산화막 스페이서(50)을 형성한다.Referring to FIG. 9, after removing the fifth photoresist pattern 76 (in FIG. 8), an undoped oxide layer is coated with an impurity, and then anisotropically etched to form the gate electrodes 48a, b, Oxide film spacers 50 are formed on the sidewalls of c, d, and e).

도 10을 참조하면, N형 불순물을 고농도로 선택적으로 주입하여 엘디엔모스의 소오스/ 드레인(80)과, 고전압 엔모스의 소오스/ 드레인(84)과, 저전압 엔모스의 소오스/ 드레인(88)을 형성하고, P형 불순물을 고농도로 선택적으로 주입하여 엘디엔모스의 P+ 영역(78)과, 고전압 피모스의 소오스/ 드레인(82)과, 저전압 피모스의 소오스/ 드레인(86)을 형성한다.Referring to FIG. 10, an N-type impurity is selectively implanted at a high concentration, so that the source / drain 80 of the Eldiene MOS source, the source / drain 84 of the high voltage NMOS, and the source / drain 88 of the low voltage NMOS are provided. P-type impurities are selectively implanted at a high concentration to form the P + region 78 of the Eldiene MOS, the source / drain 82 of the high voltage PMOS, and the source / drain 86 of the low voltage PMOS. .

도 11을 참조하면, 결과물 전면 상에 층간절연층(90)을 형성한 후 이를 패터닝하여 각 소자의 소오스/ 드레인을 부분적으로 노출시킨다. 이후, 금속층을 ??여성한 후 이를 패터닝함으로써 상기 엘디엔모스의 소오스/ 드레인 전극(S,D)과, 상기 고전압 피모스의 소오스/ 드레인 전극(S,D)과, 상기 고전압 엔모스의 소오스/ 드레인 전극(S,D)과, 상기 저전압 피모스의 소오스/ 드레인 전극(S,D)과, 상기 저전압 엔모스의 소오스/ 드레인 전극(S,D)을 형성한다.Referring to FIG. 11, an interlayer insulating layer 90 is formed on the entire surface of the resultant and then patterned to partially expose the source / drain of each device. The source / drain electrodes (S, D) of the ELD, the source / drain electrodes (S, D) of the high voltage PMOS, and the source of the high voltage NMOS are formed by patterning the metal layer. / Drain electrodes (S, D), the source / drain electrodes (S, D) of the low voltage PMOS, and the source / drain electrodes (S, D) of the low voltage NMOS.

본 발명에 의한 씨디모스 제조방법에 의하면, 하나의 마스크를 이용하여 필드 디플리션 N-채널 영역과 필드 디플리션 P-채널 영역을 형성할 수 있으므로 공정을 단순화할 수 있다.According to the CDMOS manufacturing method according to the present invention, since the field depletion N-channel region and the field depletion P-channel region can be formed using one mask, the process can be simplified.

Claims (3)

실리콘 기판의 엘디모스와, 고전압 피모스 및 엔모스, 저전압 피모스 및 엔모스 영역에 N웰과 P웰을 형성하는 단계;Forming N wells and P wells in the Eldimos, high voltage PMOS and NMOS, low voltage PMOS and NMOS regions of the silicon substrate; 상기 실리콘 기판 상에 질화막을 형성한 후 제1 포토레지스트 패턴을 이용하여 이를 식각하고, 계속해서 N형의 불순물을 이온주입하여 엘디모스의 드리프트와, 고농도 엔모스의 저농도 소오스/ 드레인과, 고전압 피모스와 저전압 피모스의 필드 디플리션 P-채널 영역을 동시에 형성하는 단계; 및After the nitride film is formed on the silicon substrate, it is etched by using a first photoresist pattern, followed by ion implantation of N-type impurities to drift of eldimose, low concentration source / drain of high concentration NMOS, and high voltage coating. Simultaneously forming field depletion P-channel regions of a low voltage PMOS; And 상기 제1 포토레지스트 패턴을 제거한 후 제2 포토레지스트 패턴을 형성하고, 계속해서 P형의 불순물을 이온주입을 행하여 고전압 피모스의 저농도 소오스/ 드레인과, 고전압 엔모스와 저전압 엔모스의 필드 디플리션 N-채널 영역을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 소자의 씨디모스 제조방법.After removing the first photoresist pattern, a second photoresist pattern is formed, followed by ion implantation of a P-type impurity, and a low concentration source / drain of a high voltage PMOS, a field dimple of a high voltage NMOS and a low voltage NMOS. Forming a portion N-channel region; 제1항에 있어서,The method of claim 1, 상기 제1 포토레지스트 패턴은 엘디모스의 드리프트 영역, 고전압 피모스의 저농도 소오스/ 드레인과 에프디피 영역, 고전압 엔모스의 저농도 소오스/ 드레인 과, 에프디엔 영역, 저전압 피모스의 에프디피 영역 및 저전압 엔모스의 에프디엔 영역을 노출시키는 모양이고, 상기 제2 포토레지스트 패턴은 고전압 피모스의 저농도 소오스/ 드레인과, 고전압 엔모스의 에프디엔 영역과, 저전압 엔모스의 에프디엔 영역을 노출시키는 모양인 것을 특징으로 하는 반도체 소자의 씨디모스 제조방법.The first photoresist pattern includes a drift region of an ELDMOS, a low concentration source / drain and an FDPI region of a high voltage PMOS, a low concentration source / drain of a high voltage NMOS, an FDN region, an FDMP region of a low voltage PMOS, and a low voltage EN The second die photoresist pattern is a shape that exposes a low-density source / drain of a high voltage PMOS, a high-energy F-die region, and a low-voltage N-MOS region. A CD device manufacturing method for a semiconductor device characterized by the above-mentioned. 제1항에 있어서,The method of claim 1, 상기 필드 디플리션 N-채널 영역을 형성하는 단계 후, 기판 전면에 게이트 산화막과 다결정실리콘막을 형성한 후 제3 포토레지스트 패턴을 이용하여 상기 다결정실리콘막을 사진/ 식각한 후 이온주입하여 엘디모스의 P 바디와 고전압 피모스의 소오스/ 드레인을 형성하는 단계와, 상기 제3 포토레지스트 패턴을 제거한 후 기판 전면에 문턱전압 조절용 불순물을 주입하는 단계를 더 구비하는 것을 특징으로 하는 반도체 소자의 씨디모스 제조방법.After forming the field depletion N-channel region, a gate oxide film and a polysilicon film are formed on the entire surface of the substrate, and then photo / etched the polycrystalline silicon film using a third photoresist pattern, followed by ion implantation. Forming a source / drain of the P body and the high voltage PMOS, and implanting impurities for adjusting the threshold voltage on the entire surface of the substrate after removing the third photoresist pattern; Way.
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JPH0629477A (en) * 1992-06-03 1994-02-04 Fuji Electric Co Ltd Manufacture of semiconductor device
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JPH05160355A (en) * 1991-05-03 1993-06-25 Hyundai Electron Ind Co Ltd Manufacture of cmos with twin well
JPH0629477A (en) * 1992-06-03 1994-02-04 Fuji Electric Co Ltd Manufacture of semiconductor device
KR950024357A (en) * 1994-01-21 1995-08-21 문정환 LDD MOSFET manufacturing method of semiconductor device
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