KR100215697B1 - Isolation method in semiconductor device - Google Patents
Isolation method in semiconductor device Download PDFInfo
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- KR100215697B1 KR100215697B1 KR1019960051693A KR19960051693A KR100215697B1 KR 100215697 B1 KR100215697 B1 KR 100215697B1 KR 1019960051693 A KR1019960051693 A KR 1019960051693A KR 19960051693 A KR19960051693 A KR 19960051693A KR 100215697 B1 KR100215697 B1 KR 100215697B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
- H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
Abstract
본 발명은 반도체 소자의 아이솔레이션 방법에 관한 것으로, 소정 두께의 패드 산화막 및 질화막이 적층된 실리콘 기판을 제공하는 단계, 여기서 실리콘 기판은 P웰 및 N웰이 형성된 구조이다; 질화막 상에 제 1 포토마스크 패턴을 형성하는 단계; 노출된 질화막이 제거되도록 제 1 포토마스크 패턴의 형태로 상기 질화막을 식각하는 단계; 질화막이 제거된 부분에 불순물을 이온 주입하는 단계; 제 1 포토마스크 패턴을 제거하는 단계; 상기 적층막 및 패드 산화막의 상부에 제 2 포토마스크 패턴을 형성하는 단계; 제 2 포토마스크 패턴의 형태로 그 하부의 질화막을 식각하는 단계; 상기 질화막이 제거된 부분에 불순물을 이온 주입하는 단계; 제 2 포토마스크 패턴을 제거하는 단계; 열산화 공정으로 상기 질화막이 제거된 부분에 필드 산화막을 성장시키는 단계; 및 잔여 질화막을 제거하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method for isolating a semiconductor device, the method comprising: providing a silicon substrate on which a pad oxide film and a nitride film of a predetermined thickness are stacked, wherein the silicon substrate has a structure in which P wells and N wells are formed; Forming a first photomask pattern on the nitride film; Etching the nitride film in the form of a first photomask pattern to remove the exposed nitride film; Implanting impurities into a portion where the nitride film is removed; Removing the first photomask pattern; Forming a second photomask pattern on the laminated film and the pad oxide film; Etching the nitride film thereunder in the form of a second photomask pattern; Ion implanting impurities into the portion where the nitride film is removed; Removing the second photomask pattern; Growing a field oxide film on a portion where the nitride film is removed by a thermal oxidation process; And removing the residual nitride film.
Description
본 발명은 반도체 소자의 아이솔레이션 방법에 관한 것으로, 보다 상세하게는, CMOS 소자의 아이솔레이션 공정시, 최소한의 포토마스크 공정으로 생산성을 향상시킬 수 있는 반도체 소자의 아이솔레이션 방법에 관한 것이다.The present invention relates to a method for isolating a semiconductor device, and more particularly, to a method for isolating a semiconductor device capable of improving productivity with a minimum photomask process during an isolation process of a CMOS device.
일반적으로 CMOS 기술은, PMOS 또는 NMOS 기술에 비하여 낮은 전력-지연시간의 곱(power delay product)을 얻을 수 있으며, 소자의 신뢰도가 우수하기 때문에 현재의 고집적 시스템에 적합한 기술로 인식되어 있다. 이러한, 저전력 정적회로를 제조할 수 있는 CMOS 소자는 반대극성인 PMOS와 NMOS를 함께 제작해야 하므로 실리콘 기판내에 트윈 웰(twin well)의 형성이 필수적으로 요구된다.In general, CMOS technology has a low power-delay product compared to PMOS or NMOS technology, and because of the reliability of the device is recognized as a suitable technology for the current high-density system. Since CMOS devices capable of manufacturing low-power static circuits must be fabricated with opposite polarity PMOS and NMOS, formation of twin wells in a silicon substrate is essential.
상기와 같이, 트윈 웰을 갖는 반도체 소자를 제조함에 있어서는 소자와 소자사이에 불필요한 기생소자들이 발생되는 것을 방지하고, 전기적 특성을 향상시키기 위하여 이웃하는 소자들 사이를 통상, 산화막을 형성하여 분리하는 공정이 수행되며, 이러한, 공정을 소자분리(Isolation)라 한다.As described above, in manufacturing a semiconductor device having a twin well, a process of forming an oxide film and separating the neighboring devices to prevent unnecessary parasitic elements from occurring between the devices and the devices, and to improve electrical characteristics. Is carried out, and this process is called isolation.
통상적인 소자분리 공정으로는 로코스(LOCOS : local oxidation of silicon) 방식이 주종을 이루고 있으며, 이러한, 로코스 방식을 개략적으로 설명하면, 패드 산화막과 실리콘 질화막 및 기타 막을 마스크로 사용하여 실리콘 기판을 선택적으로 산화시켜 소자들 사이를 분리하도록 비활성 영역인 필드 산화막을 형성시키는 기술이다.A typical LOCOS (local oxidation of silicon) method is mainly used as a device isolation process. To illustrate the LOCOS method, a silicon substrate is used by using a pad oxide film, a silicon nitride film, and other films as masks. It is a technique of forming a field oxide film which is an inactive region so as to selectively oxidize to separate between devices.
상기의 아이솔레이션 공정에 있어서는 필드 산화막을 형성하기 전에 그 하부에서 발생될 수 있는 기생 트랜지스터로 인한 소자의 결함을 방지하도록 필드 산화막이 형성될 부분에 불순물을 주입하는 채널 스탑 이온 주입 공정이 반드시 실시되어야 한다.In the above isolation process, a channel stop ion implantation process must be performed to inject impurities into a portion where the field oxide film is to be formed so as to prevent device defects due to parasitic transistors that may be generated below the field oxide film. .
종래 기술에 따른 반도체 소자의 아이솔레이션 공정을 도 1A 내지 도 1E 를 참조하여 설명하면 다음과 같다.The isolation process of the semiconductor device according to the prior art will be described with reference to FIGS. 1A to 1E.
도 1A 를 참조하면, P웰(1a) 및 N웰(1b)이 형성된 실리콘 기판상에 패드 산화막(2)을 성장시키고, 그 상부에 후속 공정에서 필드 산화막이 성장되는 것을 억제시키기 위하여 질화막(3)을 증착한다. 그런 다음, 질화막(3) 상에 필드 산화막 예정 영역에 적층되어 있는 성장저지층인 질화막(3) 및 패드 산화막(2)을 제거하기 위하여 제 1 포토마스크 패턴(4)을 형성한다.Referring to FIG. 1A, the nitride film 3 is grown in order to grow the pad oxide film 2 on the silicon substrate on which the P well 1a and the N well 1b are formed, and to suppress the growth of the field oxide film in a subsequent process thereon. E). Then, the first photomask pattern 4 is formed on the nitride film 3 to remove the nitride film 3 and the pad oxide film 2, which are the growth inhibiting layers stacked on the field oxide film predetermined regions.
도 1B 를 참조하면, 식각 공정을 실시하여 실리콘 기판이 노출되도록 제 1 포토마스크 패턴(4)이 형성되지 않은 부분의 질화막(3) 및 패드 산화막(2)을 제거한다.Referring to FIG. 1B, an etch process is performed to remove the nitride film 3 and the pad oxide film 2 in a portion where the first photomask pattern 4 is not formed to expose the silicon substrate.
도 1C 를 참조하면, 이후에 형성되어질 필드 산화막의 하부에 기생 트랜지스터가 발생되는 것을 방지하기 위하여 N웰(1b) 및 그 상부의 적층막 상에 제 2 포토마스크 패턴(5)을 형성한 후, 노출된 P웰(1a), 즉, 필드 산화막이 형성될 부분에만 n-채널 필드 스탑 이온 주입 공정을 실시한다.Referring to FIG. 1C, after forming the second photomask pattern 5 on the N well 1b and the stacked layer thereon, in order to prevent parasitic transistors from occurring below the field oxide film to be formed later, Only the exposed P well 1a, i.e., the portion where the field oxide film is to be formed, is subjected to the n-channel field stop ion implantation process.
도 1D 를 참조하면, 제 2 포토마스크 패턴(5)을 제거한 후, 도 1C 에 도시된 공정과는 반대로, P웰 및 그 상부의 적층막 상에 제 3 포토마스크 패턴(6)을 형성하고, 노출된 N웰(1b)에만 p-채널 필드 스탑 이온 주입 공정을 실시한다.Referring to FIG. 1D, after removing the second photomask pattern 5, a third photomask pattern 6 is formed on the P well and the stacked layer thereon, in contrast to the process shown in FIG. 1C. Only the exposed N well 1b is subjected to a p-channel field stop ion implantation process.
도 1E 를 참조하면, 제 3 포토마스크 패턴(6)을 제거한 후, 통상적인 열산화 공정을 실시하여 질화막이 형성되지 않은 실리콘 기판에 소자와 소자를 분리시키기 위한 필드 산화막(6)을 형성한다. 그리고 나서, 성장저지층으로 사용된 질화막(3)을 제거한다.Referring to FIG. 1E, after removing the third photomask pattern 6, a conventional thermal oxidation process is performed to form a field oxide film 6 for separating the device from the device on the silicon substrate on which the nitride film is not formed. Then, the nitride film 3 used as the growth inhibiting layer is removed.
그러나, 상기와 같은 종래 기술은, 아이솔레이션 공정시 3단계의 포토마스크 공정이 실시되기 때문에 이에 따라, 포토마스크 공정에 기인된 결함의 발생확률이 높고, 또한, 공정이 복잡하여 생산성이 떨어지는 문제점이 있었다.However, in the conventional technology as described above, since the three-step photomask process is performed during the isolation process, there is a problem that the probability of occurrence of defects due to the photomask process is high, and the process is complicated and the productivity is low. .
따라서, 본 발명은 3단계의 포토마스크 공정을 2단계의 포토마스크 공정으로 줄임으로써, 포토마스크 공정에서 발생될 수 있는 결함의 발생확률을 줄이고, 공정 수를 감소시켜 생산성을 향상시킬 수 있는 반도체 소자의 아이솔레이션 방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention reduces the probability of defects that may occur in the photomask process and reduces the number of processes, thereby improving productivity by reducing the three-step photomask process to two-step photomask processes. The purpose is to provide an isolation method.
도 1A 내지 도 1E 는 종래 기술에 따른 반도체 소자의 아이솔레이션 공정을 설명하기 위한 도면.1A to 1E are views for explaining an isolation process of a semiconductor device according to the prior art.
도 2A 내지 도 2E 는 본 발명에 따른 반도체 소자의 아이솔레이션 공정을 설명하기 위한 도면.2A to 2E are views for explaining an isolation process of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11a : P웰11b : N웰11a: P well 11b: N well
12 : 패트 산화막13 : 질화막12 Pat oxide film 13: Nitride film
14 : 제 1 포토마스크 패턴15 : 제 2 포토마스크 패턴14: first photomask pattern 15: second photomask pattern
16 : 필드 산화막16: field oxide film
상기와 같은 목적은, 제 1 형의 웰과 제 2 형의 웰이 표면으로부터 소정깊이까지 형성되고, 소정 두께의 패드 산화막 및 질화막이 순차적으로 적층된 실리콘 기판을 제공하는 단계; 제 1 포토마스크 패턴을 이용하여 제 1 형의 웰의 소자분리영역으로 예정된 부분들 사이의 질화막을 제거하는 단계; 질화막이 제거된 부분에 제 1 형의 불순물을 이온 주입하는 단계; 제 1 포토마스크 패턴을 제거하는 단계; 제 2 포토마스크 패턴을 이용하여 제 2 형의 웰의 소자 분리영역으로 예정된 부분들 사이의 질화막을 제거하는 단계; 질화막이 제거된 부분에 제 2 형의 불순물을 이온주입하는 단계; 제 2 포토마스크 패턴을 제거하는 단계; 열산화 공정으로 상기 질화막이 제거된 부분에 소자분리용 필드 산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 아이솔레이션 방법에 의하여 달성된다.The above object is to provide a silicon substrate in which the wells of the first type and the wells of the second type are formed to a predetermined depth from the surface, and the pad oxide film and the nitride film of the predetermined thickness are sequentially stacked; Removing the nitride film between the portions destined for the device isolation region of the well of the first type using the first photomask pattern; Ion implanting impurities of a first type into a portion where the nitride film is removed; Removing the first photomask pattern; Removing the nitride film between the portions destined for the device isolation region of the well of the second type using the second photomask pattern; Ion implanting impurities of the second type into the portion where the nitride film is removed; Removing the second photomask pattern; It is achieved by the isolation method of the semiconductor device comprising the step of forming a field oxide film for device isolation in the portion where the nitride film is removed by a thermal oxidation process.
본 발명에 따르면, 포토마스크 공정을 2단계로 줄임으로써 포토마스크 공정에서 결함이 발생될 수 있는 확률을 감소시킬 수 있으며, 또한, 공정 수를 감소시킴으로써 생산성을 향상시킬 수 있다.According to the present invention, by reducing the photomask process in two steps, it is possible to reduce the probability that defects may occur in the photomask process, and also increase productivity by reducing the number of processes.
[실시예]EXAMPLE
이하, 명세서에 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2A 를 참조하면, P웰(11a) 및 N웰(11b)이 형성된 실리콘 기판상에 패드 산화막(12) 및 성장저지층인 질화막(13)을 적층한 후, 질화막(13)의 상부에 제 1 포토마스크 패턴(14)을 형성한다. 이 때, P웰(11a) 상부는 필드 산화막 예정 영역을 제외한 나머지 영역에만 제 1 포토마스크 패턴(14)이 형성되고, N웰(11b) 상부는 제 1 포토마스크 패턴(14)으로 완전히 덮힌다.Referring to FIG. 2A, a pad oxide film 12 and a nitride film 13, which is a growth inhibiting layer, are stacked on a silicon substrate on which P wells 11a and N wells 11b are formed, and then a top of the nitride film 13 is formed. 1 Photomask pattern 14 is formed. At this time, the first photomask pattern 14 is formed only on the remaining portions of the P well 11a except for the field oxide film predetermined region, and the upper part of the N well 11b is completely covered by the first photomask pattern 14. .
도 2B 를 참조하면, 식각 공정으로 노출된 P웰(11a) 상부의 질화막(13)을 제거한 후, 필드 산화막의 하부에 기생 트랜지스터가 발생되는 것을 방지하도록 P웰(11a) 영역에만 p+채널 필드 스탑 이온 주입 공정을 실시한다. 여기서, p+채널 필드 스탑 이온은 붕소(Boron)이다.Referring to FIG. 2B, after removing the nitride film 13 on the upper portion of the P well 11a exposed by the etching process, the p + channel field is formed only in the P well 11a region to prevent parasitic transistors from occurring below the field oxide layer. A stop ion implantation process is performed. Here, the p + channel field stop ions are boron.
도 2C 를 참조하면, 제 1 포토마스크 패턴(14)을 제거하고, 전체 상부에 제 2 포토마스크 패턴(15)을 형성한다. 이 때, 도 2A 에 도시된 공정과는 반대로 N웰(11a) 상부는 필드 산화막 예정 영역을 제외한 나머지 영역에만 제 2 포토마스크 패턴(15)이 형성되고, P웰(11b) 상부는 제 2 포토마스크 패턴(15)으로 완전히 덮힌다.Referring to FIG. 2C, the first photomask pattern 14 is removed, and the second photomask pattern 15 is formed on the entire upper portion. At this time, in contrast to the process illustrated in FIG. 2A, the second photomask pattern 15 is formed only on the remaining portions of the N well 11a except for the field oxide film predetermined region, and on the upper portion of the P well 11b. It is completely covered with a mask pattern 15.
도 2D 를 참조하면, 식각 공정으로 N웰(11b) 상부의 노출된 질화막(13)을 제거하고, N웰(11b) 영역에만 n+채널 필드 스탑 이온 주입 공정이 실시된다. 여기서, n+채널 필드 스탑 이온은 비소(Asenic)이다.Referring to FIG. 2D, the exposed nitride layer 13 on the N well 11b is removed by an etching process, and an n + channel field stop ion implantation process is performed only on the N well 11b region. Here, the n + channel field stop ions are arsenic.
도 2E 를 참조하면, 제 2 포토마스크 패턴(15)을 제거한 상태에서, 열산화 공정을 실시하여 질화막(13)이 제거된 영역에 필드 산화막(16)을 형성한 후, 성장저지층으로 사용된 잔여 질화막(13)을 제거한다.Referring to FIG. 2E, in a state where the second photomask pattern 15 is removed, a thermal oxidation process is performed to form the field oxide film 16 in the region where the nitride film 13 is removed, and then used as a growth inhibiting layer. The remaining nitride film 13 is removed.
이상에서와 같이, 본 발명의 반도체 소자의 아이솔레이션 방법은 포토마스크 공정을 줄임으로써, 포토마스크 공정에서 야기되는 결함의 발생확률을 줄일 수 있고, 이에 따라, 반도체 소자의 생산성을 향상시킬 수 있다.As described above, the isolation method of the semiconductor device of the present invention can reduce the probability of occurrence of defects caused in the photomask process by reducing the photomask process, thereby improving the productivity of the semiconductor device.
Claims (6)
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