KR100371144B1 - Method For Forming The Source And Drain Of MOS - Transistor - Google Patents
Method For Forming The Source And Drain Of MOS - Transistor Download PDFInfo
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- KR100371144B1 KR100371144B1 KR10-1999-0065210A KR19990065210A KR100371144B1 KR 100371144 B1 KR100371144 B1 KR 100371144B1 KR 19990065210 A KR19990065210 A KR 19990065210A KR 100371144 B1 KR100371144 B1 KR 100371144B1
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- ions
- dose
- implanted
- ion implantation
- forming
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- 238000000034 method Methods 0.000 title claims description 15
- 229910052796 boron Inorganic materials 0.000 claims abstract description 27
- 150000002500 ions Chemical class 0.000 claims abstract description 25
- -1 boron ions Chemical class 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- 230000007547 defect Effects 0.000 claims description 6
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000010884 ion-beam technique Methods 0.000 abstract description 6
- 230000005465 channeling Effects 0.000 abstract description 5
- 238000002513 implantation Methods 0.000 abstract description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
Abstract
본 발명은, 모스형 트랜지스터 제조방법에 관한 것으로서, 모스형 트랜지스터의 PMOS소오스/드레인영역을 형성할 때, BF2이온을 주입하는 대신에 보론(Boron)이온을 저 에너지로 고농도의 도오즈량으로 주입하므로 이온빔 밀도를 극대화하여 기판의 표면 근처를 비정질화시키므로 채널링 효과와 누설전류 특성을 획기적으로 개선하여 소자의 전기적인 특성을 향상하도록 하는 매우 유용하고 효과적인 발명에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS transistor, wherein when forming a PMOS source / drain region of a MOS transistor, instead of implanting BF 2 ions, boron ions are used at a low energy and a high concentration of dose. Since the implantation maximizes the ion beam density to amorphize near the surface of the substrate, the present invention relates to a very useful and effective invention for improving the electrical characteristics of the device by dramatically improving the channeling effect and the leakage current characteristics.
Description
본 발명은 모스형트랜지스터를 제조할 때, 누설전류를 개선하는 방법에 관한 것으로서, 특히, 모스형 트랜지스터의 PMOS소오스/드레인영역을 형성할 때, BF2이온을 주입하는 대신에 보론(Boron)이온을 저 에너지로 고농도의 도오즈량으로 주입하므로 이온빔 밀도를 극대화하여 기판의 표면 근처를 비정질화시키므로 채널링 효과와 누설전류 특성을 완화하여 소자의 전기적인 특성을 증대하도록 하는 모스형 트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for improving leakage current when manufacturing a MOS transistor, and in particular, when forming a PMOS source / drain region of a MOS transistor, a boron ion instead of implanting BF 2 ions. Is injected in a high concentration of dose with low energy to maximize the ion beam density and to amorphize near the surface of the substrate, thereby reducing the channeling effect and leakage current characteristics and increasing the electrical characteristics of the device. It is about.
일반적으로, 상기한 모스형 전계효과트랜지스터는 반도체 기판상에 형성된 게이트가 반도체층에서 얇은 산화 실리콘막에 위해 격리되어 있는 전계효과 트랜지스터로 접합형과 같이 임피던스가 저하되는 일이 없으며, 확산 공정이 1회로 간단하고, 소자간의 분리가 필요 없는 장점을 지니고 있어서, 고밀도 집적화에 적합한 특성을 지니고 있는 반도체 장치이다.In general, the MOS type field effect transistor is a field effect transistor in which the gate formed on the semiconductor substrate is isolated from the semiconductor layer for the thin silicon oxide film, and the impedance is not lowered like the junction type. It is a semiconductor device that has the advantages of a simple circuit and no separation between elements, and is suitable for high density integration.
도 1(a) 및 도 1(b)는 종래의 모스형 트랜지스터의 제조방법을 보인 도면으로서, 도 1(a)에 도시된 바와 같이, 반도체기판(1)에 고 에너지 상태의 이온을 주입하여 n-웰을 형성한 후, 소자분리공정을 이용하여 소자분리막(3)을 반도체기판(1)상에 형성하도록 한다.1 (a) and 1 (b) show a conventional method of manufacturing a MOS transistor, as shown in FIG. 1 (a), by implanting ions in a high energy state into the semiconductor substrate 1 After the n-well is formed, the device isolation film 3 is formed on the semiconductor substrate 1 by using a device isolation process.
그리고, 상기 소자구조가 형성된 반도체기판(1) 상에 게이트산화막(5), 게이트전극층(6) 및 마스산화막(7)을 적층한 후, 마스킹식각공정으로 게이트를 형성하도록 한다.After the gate oxide film 5, the gate electrode layer 6, and the mask oxide film 7 are stacked on the semiconductor substrate 1 on which the device structure is formed, a gate is formed by a masking etching process.
그리고, 상기 게이트에 산화막을 적층한 후 블랭킷식각으로 게이트 양측면에 스페이서막(8)을 형성하도록 한다.After the oxide film is deposited on the gate, spacer layers 8 are formed on both sides of the gate by blanket etching.
그런 후에, 도 1(b)에 도시된 바와 같이, 게이트의 마스크산화막(7) 상에 감광막(9)을 적층한 후, BF2이온을 주입하여 소오스/드레인영역(10)을 형성하도록 한다.Thereafter, as shown in FIG. 1B, after the photoresist layer 9 is laminated on the mask oxide layer 7 of the gate, BF 2 ions are implanted to form the source / drain regions 10.
그런데, 상기한 바와 같이, 상기 BF2이온을 주입하여 P+ 소오스/드레인영역 (10)을 형성하는 경우는, 얕은 졍션 깊이(Shallow Junction Depth)를 얻기에는 유리하지만 도 2에 도시된 바와 같이, 소오스/드레인영역에 과도한 결함을 유발하기 때문에 누설전류 열화의 가능성이 항상 존재하는 실정이다.However, as described above, in the case of forming the P + source / drain region 10 by implanting the BF 2 ions, it is advantageous to obtain a shallow junction depth, but as shown in FIG. The possibility of leakage current deterioration is always present because it causes excessive defects in the / drain region.
특히, 반도체장치가 고집적화 될수록 소오스/드레인영역의 졍션의 깊이(a)를 줄여야만 쇼트채널 이펙트(Short Channel Effect)에 의한 소자의 특성 저하를 방지함에도 불구하고, 졍션깊이가 줄수록 이온주입후의 EOR(End Of Range) 결함영역 (b)과 트랜지스터 동작시의 디플리션 영역과의 간격과 서로 접촉되어져서 결국에는 누설전류를 증가시키므로 소자의 전기적인 특성을 저하시키는 문제점을 지닌다.In particular, as semiconductor devices become more integrated, the depth (a) of the section of the source / drain regions must be reduced to prevent deterioration of device characteristics due to the short channel effect, but as the depth of the section decreases, the EOR after ion implantation decreases. (End Of Range) Since the gap between the defect area (b) and the depletion area during the transistor operation is in contact with each other, the leakage current is increased eventually, thereby deteriorating the electrical characteristics of the device.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 모스형 트랜지스터의 PMOS소오스/드레인영역을 형성할 때, BF2이온을 주입하는 대신에 보론이온을 저 에너지로 고농도의 도오즈량으로 주입하므로 이온빔 밀도를 극대화하여 기판의 표면 근처를 비정질화시키므로 채널링 효과와 누설전류 특성을 완화하여 소자의 전기적인 특성을 증대하는 것이 목적이다.The present invention has been made in view of this point, and when forming a PMOS source / drain region of a MOS transistor, instead of implanting BF 2 ions, boron ions are implanted at a high concentration with low energy and thus ion beam density. The purpose is to increase the electrical characteristics of the device by reducing the channeling effect and leakage current characteristics by maximizing the amorphous state near the surface of the substrate.
도 1(a) 및 도 1(b)는 종래의 모스형 트랜지스터의 제조방법을 보인 도면이고,1 (a) and 1 (b) are views showing a conventional method for manufacturing a MOS transistor.
도 2는 종래의 모스형 트랜지스터의 소오스/드레인영역에 메탈콘택영역을 형성할 때, BF2이온주입불량에 의한 결함을 보인 도면이고,2 is a view showing a defect caused by BF 2 ion implantation failure when forming a metal contact region in a source / drain region of a conventional MOS transistor.
도 3(a) 및 도 3(b)는 본 발명에 따른 모스형 트랜지스터의 제조방법을 보인 도면이며,3 (a) and 3 (b) show a method of manufacturing a MOS transistor according to the present invention.
도 4는 본 발명에 따른 소오스/드레인영역에 보론이온을 주입할 때, 이온주입농도와 주입깊이를 보인 그래프이고,4 is a graph showing ion implantation concentration and implantation depth when boron ions are implanted into a source / drain region according to the present invention;
도 5는 본 발명에 따른 소오스/드레인영역에 보론이온을 주입할 때, 보론이온의 도오즈량을 보인 도면이다.5 is a view showing the dose of boron ions when the boron ions are injected into the source / drain region according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
20 : 반도체기판 25 : n-웰20: semiconductor substrate 25: n-well
30 : 소자분리막 35 : 게이트산화막30 device isolation layer 35 gate oxide film
40 : 게이트전극층 45 : 마스크산화막40: gate electrode layer 45: mask oxide film
50 : 감광막50: photosensitive film
이러한 목적은 반도체기판 상에 소자분리막을 형성한 후, 고농도의 이온을 주입하여 N-웰을 형성하는 단계와; 상기 결과물 상에 게이트산화막, 게이트전극층 및 마스크산화막을 적층한 후, 식각으로 게이트를 형성하고 측면부에 스페이서막을 형성하는 단계와; 상기 게이트 상에 감광막을 적층한 후 소오스/드레인영역이 형성될 부위에 저에너지, 고농도의 보론 이온을 주입하여 기판의 표면에 선 비정질화층을 형성하는 단계를 포함하여 이루어진 모스형 트랜지스터 제조방법을 제공함으로써 달성된다.The object is to form an N-well by forming a device isolation film on the semiconductor substrate, and then implanting a high concentration of ions; Stacking a gate oxide film, a gate electrode layer and a mask oxide film on the resultant, forming a gate by etching and forming a spacer film on a side surface thereof; By depositing a low-energy, high concentration of boron ions in the source / drain region to form a photoresist layer on the gate to form a line amorphous layer on the surface of the substrate by providing a method for manufacturing a MOS transistor Is achieved.
그리고, 상기 보론이온주입은, 0 ∼ 5Kev의 에너지와, 5.0 mA/㎠ 이상의 주입 도오즈 비율로 주입하는 것이 바람직 하다.The boron ion injection is preferably injected at an energy of 0 to 5 Kev and an injection dose ratio of 5.0 mA / cm 2 or more.
상기 보론이온을 주입할 때, 주입 영역의 데미지를 최소화하기 위하여 제1단계 및 제2단계로 이온을 주입하는 것이 바람직하다.When implanting the boron ions, it is preferable to implant ions in the first and second stages in order to minimize the damage of the implanted region.
이 때, 상기 제1단계 이온주입은, 0 ∼ 5Kev의 에너지와, 5.0 mA/㎠ 이상의도오즈 비율로 주입하고, 이온의 도오즈량은 1E15 ions/㎠ 이상으로 주입하도록 한다.At this time, the first stage ion implantation is implanted at an energy of 0-5 Kev and a dose ratio of 5.0 mA / cm 2 or more, and the dose of ions is implanted at 1E15 ions / cm 2 or more.
그리고, 상기 제2단계 이온주입은, 0 ∼ 5Kev의 에너지와, 0.1 ∼ 5.0 mA/㎠ 이상의 도오즈 비율로 주입하고, 이온의 도오즈량은 (T-A)ions/㎠ 이상(T는 전체이온주입 도오즈량이고, A는 소오스/드레인영역 보론이온주입 도오즈량임)으로 주입하도록 한다.The second stage ion implantation is implanted at an energy of 0 to 5 Kev and a dose ratio of 0.1 to 5.0 mA / cm 2 or more, and the dose of ions is (TA) ions / cm 2 or more (T is total ion implantation). Dose is the dose, and A is the source / drain region boron ion implantation dose).
상기 보론이온 주입 후에 결함제거를 위한 어닐링공정을 더 추가 하도록 하고, 상기 어닐링공정은, 질소가스 분위기에서, 900 ∼ 1100℃의 온도범위에서, 5 ∼ 90 초 동안 진행하고, 승온비는 30 ∼ 250℃/초 인 것이 바람직 하다.After the boron ion injection, an annealing process for removing defects is further added. The annealing process is performed in a nitrogen gas atmosphere for 5 to 90 seconds in a temperature range of 900 to 1100 ° C., and the temperature increase ratio is 30 to 250. Preference is given to ° C / sec.
상기 질소가스는 1 ∼ 20slpm의 유량으로 공급되고, 20 ∼ 100℃/초의 냉각속도로 진행하는 것이 바람직하다.The nitrogen gas is supplied at a flow rate of 1 to 20 slm and preferably proceeds at a cooling rate of 20 to 100 ° C / sec.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 3(a)에 도시된 바와 같이, 반도체기판(10) 상에 소자분리막(30)을 형성한 후, 고농도의 이온을 주입하여 N-웰(25)을 형성한다. 그리고, 상기 결과물 상에 게이트산화막(35), 게이트전극층(40) 및 마스크산화막(45)을 적층한 후, 식각으로 게이트를 형성하고 측면부에 스페이서막(47)을 형성하도록 한다.As shown in FIG. 3A, after the device isolation layer 30 is formed on the semiconductor substrate 10, a high concentration of ions is implanted to form an N-well 25. After the gate oxide layer 35, the gate electrode layer 40, and the mask oxide layer 45 are stacked on the resultant product, the gate is formed by etching and the spacer layer 47 is formed on the side surface.
도 3(b)에 도시된 바와 같이, 상기 게이트 상에 감광막(50)을 적층한 후, 소오스/드레인영역(55)이 형성될 부위에 저에너지, 고농도의 보론 이온을 주입하여 기판의 표면에 선비정질화층(Continuous Pre-amorphization Layer)(c)을 형성하도록 한다.As shown in FIG. 3B, after the photoresist layer 50 is stacked on the gate, low energy and high concentrations of boron ions are implanted in a portion where the source / drain regions 55 are to be formed to form a line on the surface of the substrate. A continuous pre-amorphization layer (c) is formed.
상기 보론이온주입은, 0 ∼ 5Kev의 에너지와, 5.0 mA/㎠ 이상의 주입 도오즈 비율로 주입하는 것이 바람직 하다.It is preferable to inject | pour the said boron ion implantation with the energy of 0-5Kev, and the injection dose ratio of 5.0 mA / cm <2> or more.
상기 보론이온을 주입할 때, 주입 영역의 데미지를 최소화하기 위하여 제1단계 및 제2단계로 보론이온을 주입하도록 한다.When injecting the boron ions, the boron ions are implanted in the first and second steps in order to minimize the damage of the injection region.
상기 제1단계 이온주입은, 0 ∼ 5Kev의 에너지와, 5.0 mA/㎠ 이상의 도오즈 비율로 주입하고, 이온의 도오즈량은 1E15 ions/㎠ 이상으로 주입하도록 하고, 상기 제2단계 이온주입은, 0 ∼ 5Kev의 에너지와, 0.1 ∼ 5.0 mA/㎠ 이상의 도오즈 비율로 주입하고, 이온의 도오즈량은 (T-A)ions/㎠ 이상(T는 전체이온주입 도오즈량이고, A는 소오스/드레인영역 보론이온주입 도오즈량임)으로 주입하도록 한다.The first stage ion implantation is implanted at an energy ratio of 0 to 5 Kev and a dose ratio of 5.0 mA / cm 2 or more, and the dose of ions is implanted at 1E15 ions / cm 2 or more, and the second stage ion implantation is performed. , Energy of 0 to 5 Kev and a dose ratio of 0.1 to 5.0 mA / cm 2 or more, and the dose of ions is (TA) ions / cm 2 or more (T is the total ion implantation dose, and A is the source / Drain region boron ion implantation dose).
상기 보론이온 주입 후에 결함제거를 위한 어닐링공정을 더 추가 하도록 한다.After the boron ion implantation, an annealing process for removing defects may be further added.
상기 어닐링공정은, 질소가스 분위기에서, 900 ∼ 1100℃의 온도범위에서, 5 ∼ 90 초 동안 진행하고, 승온속도는 30 ∼ 250℃/초 인 것이 바람직 하다.The annealing step is carried out for 5 to 90 seconds in a nitrogen gas atmosphere at a temperature range of 900 to 1100 ℃, the temperature increase rate is preferably 30 to 250 ℃ / second.
상기 질소가스는 1 ∼ 20slpm 의 유량으로 공급되고, 20 ∼ 100℃/초의 냉각속도로 진행하도록 한다.The nitrogen gas is supplied at a flow rate of 1 to 20 slm and proceeds at a cooling rate of 20 to 100 ° C./sec.
도 4는 본 발명에 따른 소오스/드레인영역에 보론이온을 주입할 때, 이온주입농도와 주입깊이를 보인 그래프로서, 상기한 공정을 통하여 반도체기판(20)의 소오스/드레인영역(55)이 표면에 선비정질화층(c)이 형성되는 상태를 보이고 있다.4 is a graph showing ion implantation concentration and implantation depth when boron ions are implanted into a source / drain region according to the present invention. The source / drain region 55 of the semiconductor substrate 20 is formed by the above-described process. The sun amorphous layer (c) is formed.
한편, 하기에 표시된 표1은, 2KeV에너지로 보론이온을 주입할 때, 빔커런트(Beam Current)에 따른 단위 면적당 도오즈 비(Dose Rate)를 나타낸다.On the other hand, Table 1 shown below shows the dose rate per unit area according to the beam current (Beam Current) when injecting the boron ion with 2 KeV energy.
[표1]Table 1
도 5는 본 발명에 따른 소오스/드레인영역에(55) 보론이온을 주입할 때, 보론이온의 도오즈량을 보인 도면으로서, 그래프에서, "A"로 표시된 바와 같이, 주입되는 보론이온은, 25℃에서 0.26mA/㎠의 도오즈 비(Dose Rate)로 이온주입시 비정질층 형성을 위한 임계 도오즈는, 대략적으로 1E17KeV임을 알 수 있다. 이것은 PMOS 트랜지스터를 형성하기 위한 도오즈가 1E15KeV임을 감안하면 매우 고농도의 이온이 주입된 다는 것을 알 수 있습니다.5 is a view showing the dose of boron ions when the 55 boron ions are implanted into the source / drain region according to the present invention. It can be seen that the critical dose for forming an amorphous layer upon ion implantation at a dose rate of 0.26 mA / cm 2 at 25 ° C. is approximately 1E17KV. This shows that a very high concentration of ions are implanted, considering that the dose to form a PMOS transistor is 1E15KeV.
표 1에서 표시된 바와 같이, 12mA 빔 커런트의 경우에 6.79mA/㎠ 정도로 이온 빔 밀도를 극대화시킴으로써 표면근처를 비정질화시키기에 충분한 이온 빔 에너지를 확보함으로써 보론이온 주입시에 나타나는 채널링(Channeling)을 억제함과 동시에 이온주입시 필연적으로 나타나는 데미지를 감소시키므로 P+ 울트라 쉘로우 졍션(Ultra Shallow Junction)을 형성하여 쇼오트 채널 이펙트(Short Channel Effect) 특성과 같은 PMOS특성을 개선하므로 신뢰성 높은 고품질의 소자 특성을 확보하도록 한다.As shown in Table 1, in the case of the 12 mA beam current, the ion beam density is maximized at about 6.79 mA / cm 2 to ensure sufficient ion beam energy to amorphous the surface, thereby suppressing channeling during boron ion implantation. At the same time, it reduces damage inevitably during ion implantation, forming P + Ultra Shallow Junction to improve PMOS characteristics such as short channel effect characteristics, thereby ensuring high quality device characteristics. Do it.
상기한 바와 같이, 본 발명에 따른 모스형 트랜지스터 제조방법을 이용하게 되면, 모스형 트랜지스터의 PMOS소오스/드레인영역을 형성할 때, BF2이온을 주입하는 대신에 보론이온을 저 에너지로 고농도의 도오즈량으로 주입하므로 이온빔 밀도를 극대화하여 기판의 표면 근처를 비정질화시키므로 채널링 효과(Channeling Effect)와 누설전류(Leakage Current) 특성을 획기적으로 개선하여 소자의 전기적인 특성을 향상하도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the MOS transistor manufacturing method according to the present invention is used, when the PMOS source / drain regions of the MOS transistor are formed, instead of implanting BF 2 ions, the boron ions are injected at high concentration with low energy. It is very useful and effective to improve the electrical characteristics of the device by drastically improving the channeling effect and leakage current characteristics by maximizing ion beam density by injecting in the amount of ozone, thereby making the amorphous surface near the surface of the substrate. Invention.
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