KR100913056B1 - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device Download PDF

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KR100913056B1
KR100913056B1 KR1020020084277A KR20020084277A KR100913056B1 KR 100913056 B1 KR100913056 B1 KR 100913056B1 KR 1020020084277 A KR1020020084277 A KR 1020020084277A KR 20020084277 A KR20020084277 A KR 20020084277A KR 100913056 B1 KR100913056 B1 KR 100913056B1
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region
ion implantation
semiconductor substrate
gate electrode
implantation process
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KR20040057519A (en
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차한섭
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, 반도체 소자의 제조공정에 있어서, 'n+' 이온 주입 공정 후 'p+' 이온 주입 공정 전에 퍼니스 어닐링 방식으로 열처리공정을 실시함으로써 상기 'n+' 이온 주입 공정시 반도체 기판 내에서 발생하는 결함을 제거할 수 있으며, 따라서, 궁극적으로 반도체 제품의 수율을 향상시킬 수 있는 반도체 소자의 제조방법을 개시한다.
The present invention relates to a method for manufacturing a semiconductor device, wherein in the manufacturing process of a semiconductor device, the 'n +' ion implantation process is performed by a furnace annealing method after the 'n +' ion implantation process and before the 'p + ' ion implantation process. Disclosed is a method of manufacturing a semiconductor device capable of eliminating defects occurring in a semiconductor substrate during a process and ultimately improving a yield of a semiconductor product.

반도체 소자, CMOS, 퍼니스 어닐링, 전이 에치 핏 Semiconductor Devices, CMOS, Furnace Annealing, Transition Etch Fit

Description

반도체 소자의 제조방법{Method for manufacturing a semiconductor device} Method for manufacturing a semiconductor device             

도 1 내지 도 5는 종래기술의 반도체 소자의 제조방법에 따라 야기되는 문제점을 설명하기 위한 도면들이다. 1 to 5 are diagrams for explaining a problem caused by the method of manufacturing a semiconductor device of the prior art.

도 6 내지 도 14는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위하여 도시한 단면도들이다.
6 to 14 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명>        <Explanation of symbols for the main parts of the drawings>

10, 100 : 반도체 기판 12, 102 : 소자 분리막10, 100: semiconductor substrate 12, 102: device isolation film

104 : 게이트 산화막 106 : 폴리실리콘막 104: gate oxide film 106: polysilicon film

110 : NMOS 게이트 전극 112 : PMOS 게이트 전극110: NMOS gate electrode 112: PMOS gate electrode

116, 120 : 저농도 접합영역 122 : LDD 스페이서116, 120 low concentration junction region 122 LDD spacer

126, 130 : 고농도 접합영역 126, 130: high concentration junction region

18, 114, 118, 124, 128 : 포토레지스트 패턴
18, 114, 118, 124, 128: photoresist pattern

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 고집적 반도체 소자의 제조공정시 반도체 기판에 발생하는 결함을 제거하여 궁극적으로 제품의 수율을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of removing defects occurring in a semiconductor substrate during a manufacturing process of a highly integrated semiconductor device and ultimately improving product yield.

최근 로직 소자(logic device)의 제조에서는 소자 분리를 위해 통상적으로 STI(Shallow Trench Isolation) 스킴(scheme)이 이용된다. 이러한 STI 스킴은 안정적인 활성영역의 확보에는 많은 기여를 하고 있으나, 도 1에 도시된 'A'에서와 같이 트렌치 모서리(trench corner) 부위에 집중되는 고응력에 의해 다양한 문제가 발생하고 있는 실정이다. 그 중 제품의 불량률에 가장 큰 영향을 주는 것이 고응력 집중 부위에 발생하는 전위(dislocation), 즉 격자결함에 의한 누설전류의 증가다. 트렌치 하부(trench bottom)를 통한 누설전류의 증가는 제품의 수율에 직접적인 영향을 준다. In the manufacture of logic devices, a shallow trench isolation (STI) scheme is commonly used for device isolation. Although the STI scheme contributes to securing a stable active region, various problems are caused by high stress concentrated in trench corners as shown in 'A' of FIG. 1. Among them, the greatest influence on the defective rate of the product is the dislocation occurring at the high stress concentration site, that is, the increase of leakage current due to lattice defects. The increase in leakage current through the trench bottom directly affects product yield.

도 1에 도시된 바와 같이 고응력 부위가 형성된 후 소오스/드레인 이온주입공정을 통해 NMOS 영역(즉, n+ 영역)은 통상적으로 'As'로 이온주입되게 된다. 이때, 도 2에 도시된 바와 같이 'As'의 원자 충돌에 의해 도시된 'B' 부위에 많은 결함들이 발생하게 된다. 그리고, 상기 결함들은 후속의 열공정에 의해 트렌치의 고응력 부위로 이동하게 되며, 이에 따라, 도 3에 도시된 'C'와 같이 트렌치 근처에 전이가 형성된다. 이러한 전이를 분석하는 방법은 반도체 소자의 제조 공정후 디캡(decap) 과정을 통해 기판 상의 모든 구조물층을 제거한 후 'Wright Etch'를 실시하여 전이가 형성되는 부위에 발생한 에치 핏(etch pit)을 관찰함으로써 가능 하다. As shown in FIG. 1, the NMOS region (ie, the n + region) is usually implanted into 'As' through the source / drain ion implantation process after the high stress region is formed. In this case, as shown in FIG. 2, many defects are generated at the 'B' portion shown by the atomic collision of 'As'. The defects are then moved to the high stress site of the trench by a subsequent thermal process, whereby a transition is formed near the trench as shown in FIG. 3. The method for analyzing such transitions is to remove all the structure layers on the substrate through a decap process after the semiconductor device manufacturing process, and then perform a 'right etch' to observe the etch pit generated at the site where the transition is formed. It is possible by doing

도 3에 도시된 바와 같이, 전이가 형성되면 'Wright Etch'시 도 4와 같이 식각방향에 따른 식각속도 차에 의해 전이를 따라 에치 핏이 발생하게 된다. 실제로 도 5에 도시된 'D'와 같이 NMOS 활성영역과 트렌치 경계부위에서 에치 핏이 발생한다. 이와 같이 NMOS 영역에는 에피 칫이 발생하는 반면, 일반적으로 'B' 또는 'BF2'는 'As'처럼 과도한 결함을 유발하지 않기 때문에 PMOS 영역(즉, p+ 영역)에서는 에치 핏이 발생하지 않는다. 여기서, 미설명된 '10'은 반도체 기판이고, '12'는 소자 분리막이며, '20'은 전이 시드(dislocation seed)를 가리키며, '30'는 식각방향을 가리킨다.
As shown in FIG. 3, when the transition is formed, an etch fit is generated along the transition by the difference in etching speed in the etching direction as shown in FIG. 4 during 'Wright Etch'. In fact, an etch fit occurs in the NMOS active region and the trench boundary, as shown by 'D' shown in FIG. As such, the epitaxial is generated in the NMOS region, whereas in general, 'B' or 'BF 2 ' does not cause excessive defects such as 'As', so no etch fit occurs in the PMOS region (ie, the p + region). Herein, '10', which is not described, is a semiconductor substrate, '12' is a device isolation layer, '20' is a transition seed, and '30' is an etching direction.

따라서, 본 발명은 상기에서 설명한 종래 기술의 문제점을 해결하기 위해 안출된 것으로, 고집적 반도체 소자의 제조공정시 반도체 기판에 발생하는 결함을 제거하여 궁극적으로 제품의 수율을 향상시킬 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.
Accordingly, the present invention has been made to solve the problems of the prior art described above, the manufacturing of a semiconductor device that can improve the yield of the product by eliminating defects occurring in the semiconductor substrate during the manufacturing process of the highly integrated semiconductor device The purpose is to provide a method.

본 발명의 일측면에 따르면, NMOS 영역과 PMOS 영역으로 정의되는 반도체 기판에 소자 분리막을 형성하는 단계와, 상기 반도체 기판 상에 NMOS 게이트 전극과 PMOS 게이트 전극을 형성하는 단계와, LDD 이온 주입 공정을 실시하여 상기 NMOS 게이트 전극 및 상기 PMOS 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 저농도 접합영역을 형성하는 단계와, 'n+' 이온 주입 공정을 실시하여 상기 NMOS 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 상기 저농도 접합영역보다 깊은 제1 고농도 접합영역을 형성하는 단계와, 퍼니스 어닐링 방식을 이용한 열처리공정을 실시하여 상기 단계에서 실시되는 상기 'n+' 이온 주입 공정에 의해 상기 반도체 기판 내에서 발생하는 격자결합을 제거하는 단계와, 'p+' 이온 주입 공정을 실시하여 상기 PMOS 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 상기 저농도 접합영역보다 깊은 제2 고농도 접합영역을 형성하는 단계를 포함하는 반도체 소자의 제조방법을 제공한다. According to an aspect of the present invention, forming an isolation layer on a semiconductor substrate defined as an NMOS region and a PMOS region, forming an NMOS gate electrode and a PMOS gate electrode on the semiconductor substrate, and an LDD ion implantation process And forming a low concentration junction region in the semiconductor substrate exposed to both sides of the NMOS gate electrode and the PMOS gate electrode, and performing an 'n + ' ion implantation process to expose the semiconductor to both sides of the NMOS gate electrode. Forming a first high concentration junction region deeper than the low concentration junction region on the substrate, and performing a heat treatment process using a furnace annealing method to generate the inside of the semiconductor substrate by the 'n + ' ion implantation process performed in the step. the PMOS gate electrode by carrying out the step of removing the grid coupling, '+ p' ion implantation step of In the semiconductor substrate which is exposed on both sides to provide a method of manufacturing a semiconductor device including forming a deep second heavily doped junction area than that of the lightly doped junction regions.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

도 6 내지 도 14는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면들이다. 그 일례로 CMOS(Complementary Metal-Oxide-Semiconductor) 소자를 도시한 단면도들이다. 도 6 내지 도 14에 도시된 참조부호들 중 동일한 참조부호는 서로 동일한 기능을 하는 동일한 구성요소를 가리 킨다. 6 to 14 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. As an example, cross-sectional views of a complementary metal-oxide-semiconductor (CMOS) device are shown. The same reference numerals among the reference numerals shown in FIGS. 6 to 14 indicate the same components having the same function.

도 6을 참조하면, P형 반도체 기판(100)을 NMOS 영역과 PMOS 영역으로 정의하기 위해 STI(Shallow Trench Isolation) 공정을 실시하여 소자 분리막(102)을 형성한다. 그런 다음, NMOS 영역에는 'p-' 불순물인 'B'을 주입하여 P-웰(P-Well)을 형성하고, PMOS 영역에는 'n-' 불순물인 'P' 또는 'As'을 주입하여 N-웰(N-Well)을 형성한다. Referring to FIG. 6, a device isolation layer 102 is formed by performing a shallow trench isolation (STI) process to define the P-type semiconductor substrate 100 as an NMOS region and a PMOS region. Then, NMOS region 'p -' - by implanting impurities of 'P' or 'As' N impurity of 'B' by injection P- well (P-Well) and a, PMOS region has 'n' -Form a well (N-Well).

도 7을 참조하면, 전체 구조 상부에 게이트 산화막(104)을 형성한 후 그 상부에 게이트 전극용 폴리실리콘막(106)을 형성한다. 그런 다음, 일례로, NMOS 영역이 오픈(open)되도록 PMOS 영역에 미도시된 포토레지스트 패턴을 형성한 후 상기 포토레지스트 패턴을 이용한 전처리 이온주입공정을 실시한다. 이로써, NMOS 영역의 폴리실리콘막(106) 내에는 인 또는 비소가 주입된다. Referring to FIG. 7, a gate oxide film 104 is formed on the entire structure, and a polysilicon film 106 for the gate electrode is formed thereon. Then, as an example, a photoresist pattern (not shown) is formed in the PMOS region so that the NMOS region is opened, and then a pretreatment ion implantation process using the photoresist pattern is performed. As a result, phosphorus or arsenic is implanted into the polysilicon film 106 in the NMOS region.

도 8을 참조하면, 전체 구조 상부에 게이트 전극 패턴용 포토레지스트 패턴(108)을 형성한 후 상기 포토레지스트 패턴(108)을 이용한 식각공정을 실시하여 NMOS 영역에는 NMOS 게이트 전극(110)을 형성하고, PMOS 영역에는 PMOS 게이트 전극(112)을 형성한다. Referring to FIG. 8, after forming the photoresist pattern 108 for the gate electrode pattern on the entire structure, an etching process using the photoresist pattern 108 is performed to form the NMOS gate electrode 110 in the NMOS region. In the PMOS region, the PMOS gate electrode 112 is formed.

도 9를 참조하면, NMOS 영역이 오픈되도록 포토레지스트 패턴(114)을 PMOS 영역에만 형성한 후 상기 포토레지트 패턴(114)을 이용한 LDD(Lightly Drain Doped) 이온 주입 공정, 즉 'n-' 이온 주입 공정을 실시하여 NMOS 영역의 P-웰에 얕은 접합영역(Shallow junction)인 저농도 접합영역(116)을 형성한다. 이후, 스트립 공정을 실시하여 상기 포토레지스트 패턴(114)을 제거한다. Referring to Figure 9, after the photoresist pattern is NMOS region are open 114 formed only in PMOS region of the photoresist bit pattern 114, LDD (Lightly Drain Doped) ion implantation process using, that is, 'n -' ion The implantation process is performed to form a low concentration junction region 116, which is a shallow junction, in the P-well of the NMOS region. Thereafter, the photoresist pattern 114 is removed by performing a strip process.

도 10을 참조하면, PMOS 영역이 오픈되도록 포토레지스트 패턴(118)을 NMOS 영역에만 형성한 후 상기 포토레지트 패턴(118)을 이용한 LDD 이온 주입 공정, 즉 'p-' 이온 주입 공정을 실시하여 PMOS 영역의 N-웰에 얕은 접합영역인 저농도 접합영역(120)을 형성한다. 그런 다음, 스트립 공정을 실시하여 상기 포토레지스트 패턴(118)을 제거한다. 10, after the photoresist pattern has PMOS region are open 118 formed only in the NMOS region LDD ion implantation process, that is, using the above photoresist bit pattern (118) by performing an ion implantation process 'p' A low concentration junction region 120, which is a shallow junction region, is formed in the N-well of the PMOS region. Thereafter, a strip process is performed to remove the photoresist pattern 118.

도 11을 참조하면, 증착공정 및 식각공정을 순차적으로 실시하여 NMOS 게이트 전극(110) 및 PMOS 게이트 전극(112)의 양측벽에 고농도 이온 주입 공정시 이온주입마스크로 기능하기 위하여 LDD 스페이서(122)를 형성한다. 이때, LDD 스페이서(122)는 HLD(High temperature Low pressure Dielectric)막을 이용하여 형성한다. Referring to FIG. 11, the LDD spacer 122 may function as an ion implantation mask in a high concentration ion implantation process on both sidewalls of the NMOS gate electrode 110 and the PMOS gate electrode 112 by sequentially performing a deposition process and an etching process. To form. In this case, the LDD spacer 122 is formed using a high temperature low pressure dielectric (HLD) film.

도 12를 참조하면, NMOS 영역이 오픈되도록 포토레지스트 패턴(124)을 PMOS 영역에만 형성한 후 상기 포토레지트 패턴(124)을 마스크로 이용한 'n+' 이온 주입 공정을 실시하여 NMOS 영역의 P-웰에 깊은 접합영역(Depth junction)인 고농도 접합영역(126)을 형성한다. 이때, 'n+' 이온 주입 공정은 'As' 및 'P'를 이용하여 실시한다. Referring to FIG. 12, the photoresist pattern 124 is formed only in the PMOS region to open the NMOS region, and then a 'n + ' ion implantation process using the photoresist pattern 124 as a mask is performed to form the P in the NMOS region. A high concentration junction region 126, which is a depth junction, is formed in the well. At this time, the 'n + ' ion implantation process is carried out using 'As' and 'P'.

도 13을 참조하면, 전체 구조 상부에 대하여 상기 포토레지스트 패턴(124)을 제거하고 열처리공정을 실시한다. 이때, 열처리공정은 'n+' 이온 주입 공정후 발생 하는 결함을 제거하기 위하여 퍼니스 어닐링(furnace annealing) 방식으로 실시한다. 여기서, 퍼니스 어닐링 방식은 650 내지 850℃ 온도에서 10 내지 20분 동안 실시하되, 바람직하게는 적어도 700℃ 온도에서 적어도 10분 동안 실시한다. 또한, 퍼니스 어닐링 방식은 100% O2 분위기에서 실시하여 소정 영역에 미도시된 산화막을 20 내지 150Å의 두께로 형성하는 것이 바람직하다. Referring to FIG. 13, the photoresist pattern 124 is removed and heat treatment is performed on the entire structure. At this time, the heat treatment process is carried out by the furnace annealing (furnace annealing) method to remove the defects generated after the 'n + ' ion implantation process. Here, the furnace annealing method is carried out for 10 to 20 minutes at a temperature of 650 to 850 ℃, preferably at least 10 minutes at a temperature of at least 700 ℃. In addition, the furnace annealing method is preferably carried out in a 100% O 2 atmosphere to form an oxide film not shown in a predetermined region to a thickness of 20 to 150 kPa.

이와 같이, 퍼니스 어닐링 방식으로 열처리공정을 실시함으로써 종래기술에서 'n+' 이온 주입 공정후 발생하는 결함을 제거할 수 있다. 즉, 상기 열처리공정을 적어도 700℃에서 적어도 10분 동안 실시하게 되면, NMOS 영역에서 발생하는 격자결함이 제거된다. 이로써, NMOS 영역에서는 종래기술에서 발생하는 에치 핏이 발생되지 않는다. 또한, 열처리공정을 100% O2 분위기에서 실시함으로써 공정진행시 표면의 산화시 발생하는 스태킹 폴트(stacking fault)에 의해 실리콘 원자(silicon intersitial)를 주입할 수 있도록 하여 이온 주입시 발생한 결함을 더욱 빨리 제거할 수 있도록 한다. 한편, 상기 열처리 공정을 실시함으로써 도 14에서 실시되는 'p+' 이온 주입 공정시 발생할 수 있는 'B' 침투(penetration) 문제를 방지할 수 있다. As such, by performing the heat treatment process by the furnace annealing method, defects occurring after the 'n + ' ion implantation process in the related art can be removed. That is, when the heat treatment process is performed at least 700 ° C. for at least 10 minutes, lattice defects occurring in the NMOS region are removed. As a result, the etch fit generated in the prior art is not generated in the NMOS region. In addition, the heat treatment process is performed in a 100% O 2 atmosphere so that silicon intersitial can be injected by the stacking fault generated during the oxidation of the surface during the process, and thus the defects generated during ion implantation can be removed more quickly. To be removed. On the other hand, by performing the heat treatment process it is possible to prevent the 'B' penetration (penetration) problem that may occur during the 'p + ' ion implantation process performed in FIG.

도 14를 참조하면, PMOS 영역이 오픈되도록 포토레지스트 패턴(128)을 NMOS 영역에만 형성한 후 상기 포토레지트 패턴(128)을 이용한 'p+' 이온 주입 공정을 실시하여 PMOS 영역의 N-웰에 깊은 접합영역인 고농도 접합영역(130)을 형성한다. 이 후, 스트립 공정을 실시하여 상기 포토레지스트 패턴(128)을 제거한다. 이로써, NMOS 영역의 P-웰에는 저농도 접합영역(116) 및 고농도 접합영역(126)으로 이루어진 NMOS 소오스/드레인 영역이 형성되고, PMOS 영역의 N-웰에는 저농도 접합영역(120) 및 고농도 접합영역(130)으로 이루어진 PMOS 소오스/드레인 영역이 형성된다.Referring to FIG. 14, the photoresist pattern 128 is formed only in the NMOS region to open the PMOS region, and then a 'p + ' ion implantation process using the photoresist pattern 128 is performed to form an N-well in the PMOS region. A high concentration junction region 130 is formed in the deep junction region. Thereafter, a strip process is performed to remove the photoresist pattern 128. As a result, an NMOS source / drain region including a low concentration junction region 116 and a high concentration junction region 126 is formed in the P-well of the NMOS region, and a low concentration junction region 120 and a high concentration junction region are formed in the N-well of the PMOS region. A PMOS source / drain region consisting of 130 is formed.

상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예은 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

이상 설명한 바와 같이, 본 발명에서는 반도체 소자의 제조공정에 있어서, 'n+' 이온 주입 공정 후 'p+' 이온 주입 공정 전에 퍼니스 어닐링 방식으로 열처리공정을 실시함으로써 상기 'n+' 이온 주입 공정시 반도체 기판 내에서 발생하는 결함을 제거할 수 있다. 따라서, 궁극적으로 반도체 제품의 수율을 향상시킬 수 있다.
As described above, in the present invention, the semiconductor substrate during the 'n +' ion implantation process is performed by a furnace annealing process in the manufacturing process of the semiconductor device after the 'n + ' ion implantation process and before the 'p +' ion implantation process. The defect which arises in the inside can be eliminated. Therefore, ultimately, the yield of a semiconductor product can be improved.

Claims (5)

(a) NMOS 영역과 PMOS 영역으로 정의되는 반도체 기판에 소자 분리막을 형성하는 단계;(a) forming an isolation layer on a semiconductor substrate defined by an NMOS region and a PMOS region; (b) 상기 반도체 기판 상에 NMOS 게이트 전극과 PMOS 게이트 전극을 형성하는 단계; (b) forming an NMOS gate electrode and a PMOS gate electrode on the semiconductor substrate; (c) LDD 이온 주입 공정을 실시하여 상기 NMOS 게이트 전극 및 상기 PMOS 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 저농도 접합영역을 형성하는 단계; (c) performing a LDD ion implantation process to form a low concentration junction region in the semiconductor substrate exposed to both sides of the NMOS gate electrode and the PMOS gate electrode; (d) 'n+' 이온 주입 공정을 실시하여 상기 NMOS 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 상기 저농도 접합영역보다 깊은 제1 고농도 접합영역을 형성하는 단계;performing a 'n + ' ion implantation process to form a first high concentration junction region deeper than the low concentration junction region in the semiconductor substrate exposed to both sides of the NMOS gate electrode; (e) 퍼니스 어닐링 방식을 이용한 열처리공정을 실시하여 상기 (d) 단계에서 실시되는 상기 'n+' 이온 주입 공정에 의해 상기 반도체 기판 내에서 발생하는 격자결함을 제거하는 단계; 및(e) performing a heat treatment process using a furnace annealing method to remove the lattice defects generated in the semiconductor substrate by the 'n + ' ion implantation process performed in step (d); And (f) 'p+' 이온 주입 공정을 실시하여 상기 PMOS 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 상기 저농도 접합영역보다 깊은 제2 고농도 접합영역을 형성하는 단계를 포함하고,(f) performing a 'p + ' ion implantation process to form a second high concentration junction region deeper than the low concentration junction region on the semiconductor substrate exposed to both sides of the PMOS gate electrode; 상기 (e) 단계에서 실시되는 상기 퍼니스 어닐링 방식의 열처리공정에 의해 상기 반도체 기판 상에 20 내지 150Å의 두께로 산화막이 형성되는 것을 특징으로 하는 반도체 소자의 제조방법. A method of manufacturing a semiconductor device, characterized in that an oxide film is formed on the semiconductor substrate with a thickness of 20 to 150 GPa by the heat treatment process of the furnace annealing method performed in the step (e). 제 1 항에 있어서, The method of claim 1, 상기 (e) 단계에서 실시되는 상기 퍼니스 어닐링 방식의 열처리공정은 700℃에서 10분 동안 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The furnace annealing heat treatment process performed in the step (e) is performed for 10 minutes at 700 ℃. 제 1 항에 있어서, The method of claim 1, 상기 (e) 단계에서 실시되는 상기 퍼니스 어닐링 방식의 열처리공정은 650 내지 850℃에서 10 내지 20분 동안 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The furnace annealing heat treatment process performed in the step (e) is carried out for 10 to 20 minutes at 650 to 850 ℃. 제 2 항 또는 제 3 항에 있어서, The method of claim 2 or 3, 상기 열처리공정은 100% O2 분위기에 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The heat treatment step is a manufacturing method of a semiconductor device, characterized in that carried out in 100% O 2 atmosphere. 삭제delete
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JPH09252055A (en) * 1996-03-18 1997-09-22 Oki Electric Ind Co Ltd Manufacture of cmosfet
KR19980084534A (en) * 1997-05-23 1998-12-05 문정환 Manufacturing method of semiconductor device
KR100334965B1 (en) * 1999-08-12 2002-05-04 박종섭 Formation method of device of mos field effect transistor

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Publication number Priority date Publication date Assignee Title
JPH09252055A (en) * 1996-03-18 1997-09-22 Oki Electric Ind Co Ltd Manufacture of cmosfet
KR19980084534A (en) * 1997-05-23 1998-12-05 문정환 Manufacturing method of semiconductor device
KR100334965B1 (en) * 1999-08-12 2002-05-04 박종섭 Formation method of device of mos field effect transistor

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