KR100235619B1 - Method for fabricating semiconductor device - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof for preventing a latch-up phenomenon of a CMOS transistor are disclosed. A method of manufacturing a semiconductor device having a BILLI structure for preventing a latch-up phenomenon of a CMOS transistor, the method comprising the steps of: forming a P-type buried layer surrounding an N-well and serving as a P- The p-type buried layer is formed by tilting and implanting the p-type impurity.

Description

A method of manufacturing a semiconductor device.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a buried implanted layer for lateral isolation (BILLI) structure capable of preventing a latch up phenomenon of a CMOS transistor .

In general, the Cmos has the advantage of lower power consumption, larger process margin, and lower soft error than a single element of N-MOS or P-MOS.

The C MOS having such an advantage has a problem that a parasitic circuit called "latch-up" occurs and, in severe cases, the chip is destroyed.

To be more specific, the C-MOSs are formed in different wells, that is, N-wells and P-wells are formed in a common semiconductor substrate, P-MOSs are formed in the N-wells and N-MOSs are formed in the P- . However, in this C-MOS, a parasitic bipolar transistor is formed between the portion where the N-well and the P-well are in contact with each other and the junction region of the MOS transistor in the well, and an unwanted bipolar transistor is operated when the MOS transistor is driven, , Causing a problem that the system is broken.

Conventionally, a BILLI structure has been proposed in which an N well is surrounded by a P-type buried layer and a P-type buried layer serves as a P-well to prevent the latch-up phenomenon.

In the conventional BILLI structure, as shown in FIG. 1A, a first mask pattern 2 is formed on a P-type semiconductor substrate 1 provided with a field oxide film 10 so that a predetermined N well region is exposed, Impurities 3 for forming N wells are implanted into the exposed semiconductor substrate at a relatively high energy. Thereafter, a P-type impurity, for example, B11 ions is deeply implanted into the semiconductor substrate at an energy range higher than the energy of the impurity layer 3 for implanting N wells, preferably 1.5 MeV or more, A buried layer (4) is formed. In this process, the thickness of the first mask pattern 2 causes the P-type buried layer 4 to have a step difference of about the thickness of the first mask pattern 2, as shown in FIG.

At this time, the P-type buried layer 4 is formed so as to surround the periphery of the N-well 3 to prevent the latch-up phenomenon, and at the same time, the P-well formation process is eliminated.

With respect to subsequent steps, although not shown in the drawings, A process of forming a field oxide film, a process of forming a gate electrode, and a series of processes of forming a junction region are performed to form a Cmos transistor in the optimized N well and P well.

However, according to the conventional method as described above, the P-type buried layer 4 is formed by ion implantation in a state in which the first mask pattern 2 for N well formation formed by the photolithography process is formed. At this time, the vertical boundary surface of the first mask pattern 2 is formed in a shape perpendicular to the substrate, and in the ion implantation for forming the P-type buried layer, the ion implantation direction is injected perpendicular to the substrate surface, And the P-type buried layer 4 is disconnected at the bottom of the vertical interface. If the buried layer is cut off as described above, the portion of the N-well 3 is not surrounded by the buried layer, so that the latch-up phenomenon still occurs and the characteristics of the C-MOS transistor deteriorate.

In order to achieve the above-mentioned object of the present invention, the present invention provides a method for forming a p-type buried layer, comprising the steps of: tilting and implanting a P- Type buried layer formed on a semiconductor substrate.

1A and 1B are cross-sectional views for explaining a conventional method of manufacturing a semiconductor device.

2A and 2B are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to the present invention.

Description of the Related Art [0002]

1: semiconductor substrate 2: first mask pattern

3: N well 4: P-type buried layer

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a first mask pattern on a semiconductor substrate having a field oxide film so that a predetermined N well region is exposed; Forming an N well in the semiconductor substrate exposed from the first mask pattern; Implanting a P-type impurity into the entire surface of the resultant structure through an energy range sufficient to pass the first mask pattern; And removing the first mask pattern. In the step of implanting the P-type impurity, the P-type impurity is ion-implanted while being tilted to the left by a predetermined angle.

According to the present invention, there is provided a method of manufacturing a semiconductor device having a BILLI structure for preventing a latch-up phenomenon of a CMOS transistor, comprising the steps of: forming a P-type buried layer surrounding an N- So that a P-type buried layer is formed continuously, whereby the latch-up phenomenon of the C-MOS transistor is prevented.

[Example]

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention. Referring to FIGS. 2A and 2B, The field oxide film 10 is formed on the predetermined region of the P-type silicon substrate on the element isolation region by a selective oxidation method. Subsequently, the field oxide film 10 is formed on the upper surface of the semiconductor substrate 1 By a known photolithography process, a mask pattern 2 is formed. Thereafter, impurity ions for forming N wells, preferably P31 ions, are implanted into the exposed semiconductor substrate to form N wells 3.

Then, as shown in FIG. 2B, in order to simultaneously form the N-well protection layer and the P-well for preventing the C-MOS latch-up phenomenon in the semiconductor substrate in which the N-well 3 is formed, the N-well 3 A P-type impurity, preferably B11 ion, is implanted at an energy greater than the ion implantation energy of the impurity to be formed, for example, 1.5 to 2 MeV. At this time, in order to prevent a single layer of the P-type buried layer at the lower end of the mask pattern 2, the ion implantation angle is inclined about 7 to 45 degrees to the left with respect to the vertical end of the mask pattern , A continuous P-type buried layer 4 is formed.

Although not shown in the drawings, the subsequent steps include a step of forming a threshold voltage adjusting layer, a step of forming a gate electrode, a step of forming a junction region, a metal wiring step, and the like, A C-MOS transistor having no up-state is formed.

As described in detail above, according to the present invention, there is provided a method of manufacturing a semiconductor device having a BILLI structure for preventing a latch-up phenomenon of a CMOS transistor, comprising the steps of: forming a P-type buried When the layer is formed, the p-type impurity is injected while being inclined by a predetermined angle, whereby a continuous P-type buried layer is formed, thereby preventing latch-up phenomenon of the C-MOS transistor.

Claims (3)

Forming a first mask pattern on a semiconductor substrate provided with a field oxide film so that a predetermined N well region is exposed; Forming an N well in the semiconductor substrate exposed from the first mask pattern; Implanting an impurity for forming a P-type buried layer on the entire surface of the resultant structure in an energy range sufficient to pass the first mask pattern; And And removing the first mask pattern. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of implanting the P-type impurity, the P-type impurity is ion-implanted while being tilted to the left by a predetermined angle. The method of manufacturing a semiconductor device according to claim 1, wherein the P-type impurity is ion-implanted to the left with respect to the vertical end of the mask pattern by an angle of 7 to 45 degrees. The method of manufacturing a semiconductor device according to claim 1, wherein the energy for ion implantation in the ion implantation step is 1.5 to 2 MeV.