KR20010026809A - Method of forming an isolation film in a semiconductor device - Google Patents

Method of forming an isolation film in a semiconductor device Download PDF

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KR20010026809A
KR20010026809A KR1019990038272A KR19990038272A KR20010026809A KR 20010026809 A KR20010026809 A KR 20010026809A KR 1019990038272 A KR1019990038272 A KR 1019990038272A KR 19990038272 A KR19990038272 A KR 19990038272A KR 20010026809 A KR20010026809 A KR 20010026809A
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South Korea
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layer
film
forming
trench
semiconductor substrate
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KR1019990038272A
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Korean (ko)
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서을규
임재영
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박종섭
현대전자산업 주식회사
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Priority to KR1019990038272A priority Critical patent/KR20010026809A/en
Publication of KR20010026809A publication Critical patent/KR20010026809A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

PURPOSE: A method for manufacturing an isolating layer of a semiconductor device is provided to compensate for damage of boron in an active region of an n-type metal-oxide-semiconductor(MOS) field transistor by inducing a borosilicate glass(BSG) layer in forming a shallow trench isolation(STI) layer. CONSTITUTION: A pad oxide layer and a pad nitride layer are sequentially formed on a semiconductor substrate(11). The pad nitride layer, the pad oxide layer and the semiconductor substrate are etched to form a trench. After a borosilicate glass(BSG) layer(15) is formed on the entire structure having the trench, an oxide layer(16) for isolation is formed to sufficiently bury the trench. A chemical mechanical polishing(CMP) process and a process for eliminating the pad nitride layer and the pad oxide layer are carried out to form an isolating layer(56). An annealing process is performed to increase the density of the isolating layer, and boron contained in the BSG layer is diffused into the semiconductor substrate during the annealing process.

Description

반도체 소자의 소자 분리막 형성 방법 {Method of forming an isolation film in a semiconductor device}Method of forming an isolation film in a semiconductor device

본 발명은 반도체 소자의 소자 분리막 형성 방법에 관한 것으로, 특히 NMOS 전계 효과 트랜지스터의 액티브 영역을 분리시키기 위한 샬로우 트렌치 소자 분리막(shallow trench isolation; STI)을 형성할 때, 반도체 기판과 소자 분리막과의 경계에서 보론(boron; B)의 세그러게이션(segregation)으로 손실되는 보론을 보충하여 INWE를 감소시킬 수 있는 반도체 소자의 소자 분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to forming a shallow trench isolation (STI) for separating an active region of an NMOS field effect transistor. The present invention relates to a method of forming a device isolation layer of a semiconductor device capable of reducing INWE by supplementing boron lost due to the segregation of boron B at a boundary.

일반적으로, 반도체 소자의 소자 분리막은 LOCOS(LOCal Oxidation of Silicon)법 및 PBL(Poly Buffered LOCOS)법으로 산화막을 성장시키거나, 트렌치를 형성하여 절연막을 매립시켜 형성시킨다.In general, a device isolation layer of a semiconductor device is formed by growing an oxide film by LOCOS (Poly Oxidation of Silicon) and PBL (Poly Buffered LOCOS) or by forming a trench to fill an insulating film.

샬로우 트렌치 소자 분리막을 형성하는 공정은 안정된 공정 구축시 그 이점은 다른 소자 분리막 형성 기술보다 우수하다. 그러나, NMOS 전계 효과 트랜지스터의 액티브 영역을 분리시키기 위해 샬로우 트렌치 소자 분리막 형성 공정을 적용할 경우, 반도체 기판과 소자 분리막과의 경계에서 보론(boron; B)의 세그러게이션(segregation)이 발생되고, 이로 인하여 액티브 영역의 가장자리에서의 보론 농도가 감소하게 되어 NMOS 전계 트랜지스터의 문턱 전압(Vt)이 예상보다 낮게 나오며, 또한 채널 폭(channel width)이 감소함에 따라 그 효과는 더 커지게 되어 INEW가 발생한다. 이와 같이, 채널 폭에 따라 NMOS 전계 트랜지스터의 문턱 전압이 변하게 되어 회로 설계뿐만 아니라, 소자 설계에도 많은 문제점이 발생하게 된다.The process of forming the shallow trench isolation layer has advantages over the construction of a stable process over other device isolation layer formation techniques. However, when the shallow trench isolation layer forming process is applied to separate the active region of the NMOS field effect transistor, boron (B) segregation occurs at the boundary between the semiconductor substrate and the isolation layer. As a result, the boron concentration at the edge of the active region is reduced, resulting in lower than expected threshold voltage (Vt) of the NMOS field transistor, and the effect becomes greater as the channel width decreases, causing INEW to increase. Occurs. As such, the threshold voltage of the NMOS field transistor changes according to the channel width, which causes many problems not only in circuit design but also in device design.

따라서, 본 발명은 NMOS 전계 효과 트랜지스터의 액티브 영역을 분리시키기 위한 샬로우 트렌치 소자 분리막을 형성할 때, 반도체 기판과 소자 분리막과의 경계에서 보론의 세그러게이션으로 손실되는 보론을 보충하여 INWE를 감소시킬 수 있는 반도체 소자의 소자 분리막 형성 방법을 제공함에 그 목적이 있다.Therefore, when the shallow trench device isolation film for separating the active region of the NMOS field effect transistor is formed, the present invention compensates for the boron lost by the segmentation of boron at the boundary between the semiconductor substrate and the device isolation film to reduce INWE. It is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device.

이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 소자 분리막 형성 방법은 반도체 기판 상에 패드 산화막 및 패드 질화막을 순차적으로 형성하는 단계; 상기 패드 질화막, 패드 산화막 및 반도체 기판을 식각하여 트렌치를 형성하는 단계; 상기 트렌치를 포함한 전체 구조의 표면에 BSG막을 형성한 후, 상기 트렌치가 충분히 매립되도록 소자 분리용 산화막을 형성하는 단계; 화학기계적 연마 공정과 상기 패드 질화막 및 패드 산화막 제거공정을 실시하여 소자 분리막을 형성하는 단계; 및 상기 소자 분리막의 밀도를 높이기 위한 열처리 공정을 실시하며, 이 열처리 공정 동안 상기 BSG막내에 함유된 보론이 상기 반도체 기판으로 확산되는 단계를 포함하여 이루어지는 것을 특징으로 한다.The device isolation film forming method of the semiconductor device of the present invention for achieving the above object comprises the steps of sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate; Etching the pad nitride film, the pad oxide film, and the semiconductor substrate to form a trench; Forming a BSG film on the surface of the entire structure including the trench, and then forming an oxide film for isolation of the device such that the trench is sufficiently buried; Forming a device isolation layer by performing a chemical mechanical polishing process and removing the pad nitride layer and the pad oxide layer; And performing a heat treatment process for increasing the density of the device isolation film, wherein the boron contained in the BSG film is diffused into the semiconductor substrate during the heat treatment process.

도 1a 내지 도 1d는 본 발명의 실시 예에 따른 반도체 소자의 소자 분리막 형성 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of devices for describing a method of forming a device isolation film of a semiconductor device in accordance with an embodiment of the present invention.

＜도면의 주요 부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

11: 반도체 기판 12: 패드 산화막11: semiconductor substrate 12: pad oxide film

13: 패드 질화막 14: 트렌치13: pad nitride layer 14: trench

15: BSG막 16: 소자 분리용 산화막15: BSG film 16: oxide film for element isolation

56: 소자 분리막56: device separator

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명의 실시 예에 따른 반도체 소자의 소자 분리막 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for describing a method of forming a device isolation layer of a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하며, 반도체 기판(11)상에 패드 산화막(12) 및 패드 질화막(13)을 순차적으로 형성하고, 소자 분리 마스크를 사용한 식각 공정으로 패드 질화막(13), 패드 산화막(12) 및 반도체 기판(11)을 일정 깊이 식각하여 트렌치(14)를 형성한다.Referring to FIG. 1A, the pad oxide film 12 and the pad nitride film 13 are sequentially formed on the semiconductor substrate 11, and the pad nitride film 13, the pad oxide film 12, and the etching process using an element isolation mask. The trench 14 is formed by etching the semiconductor substrate 11 at a predetermined depth.

상기에서, 트렌치(14)는 약 3500Å의 깊이로 형성된다.In the above, the trench 14 is formed to a depth of about 3500 kPa.

도 1b를 참조하면, 트렌치(14)를 포함한 전체 구조의 표면에 BSG막(borosilicate glass; 15)을 형성한 후, 트렌치(14)가 충분히 매립되도록 소자 분리용 산화막(16)을 형성한다.Referring to FIG. 1B, after forming a BSG film (borosilicate glass) 15 on the surface of the entire structure including the trench 14, an oxide film 16 for element isolation is formed to sufficiently fill the trench 14.

상기에서, 통상 소자 분리막을 형성하기 위해 증착되는 산화막의 두께가 약7000Å일 경우, BSG막(15)을 약 1000Å의 두께로 증착하고, 소자 분리용 산화막(16)을 고밀도 플라즈마 화학기상증착법(HDP CVD)을 이용하여 약 6000Å의 두께로 증착한다.In the above, when the thickness of the oxide film deposited to form the device isolation film is usually about 7000 kPa, the BSG film 15 is deposited to a thickness of about 1000 kPa, and the device separation oxide film 16 is dense plasma chemical vapor deposition (HDP). CVD) to deposit a thickness of about 6000 mm 3.

도 1c를 참조하면, 화학기계적 연마(CMP) 공정과 패드 질화막(13) 및 패드 산화막(12) 제거공정을 실시하여 소자 분리막(56)을 형성한다.Referring to FIG. 1C, the device isolation layer 56 may be formed by performing a chemical mechanical polishing (CMP) process, and removing the pad nitride layer 13 and the pad oxide layer 12.

도 1d를 참조하면, 소자 분리막(56)의 밀도를 높이기 위한 열처리 공정을 실시하며, 이 열처리 공정 동안 BSG막(15)내에 함유된 보론이 반도체 기판(11)으로 확산되며, 이 보론은 반도체 기판과 소자 분리막과의 경계에서 보론의 세그러게이션으로 손실되는 보론을 보충하는 역할을 한다.Referring to FIG. 1D, a heat treatment process is performed to increase the density of the device isolation film 56, and boron contained in the BSG film 15 is diffused into the semiconductor substrate 11 during this heat treatment process. It supplements boron that is lost due to boron segmentation at the boundary with the device separator.

상술한 바와 같이, 본 발명은 샬로우 트렌치 소자 분리막(STI) 형성 공정에 BSG막을 도입하므로, NMOS 필드 트랜지스터의 액티브 영역에서 보론 손실이 보충되어 INWE를 감소시킬 수 있으며, 또한 소자 분리막의 밀도를 높이기 위한 열처리 공정을 연마 공정 후에 실시하므로, INWE 뿐만 아니라 디스로케이션 디펙트(dislocation defect)를 감소시킬 수 있어, 소자의 신뢰성 및 수율을 향상시킬 수 있다.As described above, the present invention introduces the BSG film into the shallow trench device isolation film (STI) forming process, so that boron loss can be compensated for in the active region of the NMOS field transistor, thereby reducing INWE and increasing the density of the device isolation film. Since the heat treatment process is performed after the polishing process, it is possible to reduce not only INWE but also dislocation defects, thereby improving the reliability and yield of the device.

Claims (3)

반도체 기판 상에 패드 산화막 및 패드 질화막을 순차적으로 형성하는 단계;Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate; 상기 패드 질화막, 패드 산화막 및 반도체 기판을 식각하여 트렌치를 형성하는 단계;Etching the pad nitride film, the pad oxide film, and the semiconductor substrate to form a trench; 상기 트렌치를 포함한 전체 구조의 표면에 BSG막을 형성한 후, 상기 트렌치가 충분히 매립되도록 소자 분리용 산화막을 형성하는 단계;Forming a BSG film on the surface of the entire structure including the trench, and then forming an oxide film for isolation of the device such that the trench is sufficiently buried; 화학기계적 연마 공정과 상기 패드 질화막 및 패드 산화막 제거공정을 실시하여 소자 분리막을 형성하는 단계; 및Forming a device isolation layer by performing a chemical mechanical polishing process and removing the pad nitride layer and the pad oxide layer; And 상기 소자 분리막의 밀도를 높이기 위한 열처리 공정을 실시하며, 이 열처리 공정 동안 상기 BSG막내에 함유된 보론이 상기 반도체 기판으로 확산되는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 소자 분리막 형성 방법.And performing a heat treatment process to increase the density of the device isolation film, wherein the boron contained in the BSG film is diffused into the semiconductor substrate during the heat treatment process. 제 1 항에 있어서,The method of claim 1, 상기 트렌치는 약 3500Å의 깊이로 형성하는 것을 특징으로 하는 반도체 소자의 소자 분리막 형성 방법.And forming the trench at a depth of about 3500 microns. 제 1 항에 있어서,The method of claim 1, 상기 BSG막은 약 1000Å의 두께로 증착하고, 상기 소자 분리용 산화막은 고밀도 플라즈마 화학기상증착법을 이용하여 약 6000Å의 두께로 증착하는 것을 특징으로 반도체 소자의 소자 분리막 형성 방법.Wherein the BSG film is deposited to a thickness of about 1000 GPa, and the oxide film for device isolation is deposited to a thickness of about 6000 GPa using a high density plasma chemical vapor deposition method.
KR1019990038272A 1999-09-09 1999-09-09 Method of forming an isolation film in a semiconductor device KR20010026809A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801053B1 (en) * 2006-10-27 2008-02-04 삼성전자주식회사 Method of isolating a device and method of forming an image device using the same
KR100885287B1 (en) * 2002-07-10 2009-02-23 매그나칩 반도체 유한회사 Method for forming the semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100885287B1 (en) * 2002-07-10 2009-02-23 매그나칩 반도체 유한회사 Method for forming the semiconductor device
KR100801053B1 (en) * 2006-10-27 2008-02-04 삼성전자주식회사 Method of isolating a device and method of forming an image device using the same

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