KR20000045893A - Method for forming device isolation layer of semiconductor device - Google Patents

Method for forming device isolation layer of semiconductor device Download PDF

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Publication number
KR20000045893A
KR20000045893A KR1019980062504A KR19980062504A KR20000045893A KR 20000045893 A KR20000045893 A KR 20000045893A KR 1019980062504 A KR1019980062504 A KR 1019980062504A KR 19980062504 A KR19980062504 A KR 19980062504A KR 20000045893 A KR20000045893 A KR 20000045893A
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South Korea
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trench
oxide film
film
device isolation
forming
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KR1019980062504A
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Korean (ko)
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KR100519511B1 (en
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김수호
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Abstract

PURPOSE: A method for forming a device isolation layer of a semiconductor device is provided to prevent cavities from occurring on the device isolation layer. CONSTITUTION: A method for forming a device isolation layer of a semiconductor device includes following steps. At the first step, a pad oxide layer(20) and a nitride layer(30) are vaporized on a substrate(10). At the second step, a photoresist layer(40) including a contact portion at which the device isolation layer is to be formed is accumulated. At the third step, a trench is formed through the contact portion of the photoresist layer, and a trench oxide layer is formed inside the semiconductor substrate. At the fourth step, the useless part of the trench oxide layer is removed by using a rinsing step. At the fifth step, a gap-fill oxide layer is formed inside the trench under high pressure, and the gap-fill oxide layer is flattened by using an annealing process. At the sixth step, the result of the preceding steps is converted to a device isolation layer(80) by using a rinsing and polishing process.

Description

반도체장치의 소자분리막 형성방법Method of forming device isolation film in semiconductor device

본 발명은 STI공정으로 소자분리막을 형성하는 방법에 관한 것으로서, 특히, 트렌치의 기판 내벽면에 트렌치산화막을 형성한 후 세정공정을 수행하여 트렌치산화막을 제거하고, 이 트렌치내에 고압의 LP-TEOS 갭필링산화막을 증착하여 식각으로 소자분리막을 형성하여 소자분리막에 공극이 발생되는 것을 방지하도록 하는 반도체장치의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film by the STI process, in particular, to form a trench oxide film on the inner surface of the substrate of the trench and then to perform a cleaning process to remove the trench oxide film, the high pressure LP-TEOS gap in the trench The present invention relates to a method of forming a device isolation film of a semiconductor device, by depositing a peeling oxide film to form an device isolation film by etching to prevent voids in the device isolation film.

일반적으로, 반도체기판 상에 트랜지스터와 커패시터등을 형성하기 위하여 반도체기판에는 전기적으로 통전이 가능한 활성영역(Active Region)과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리영역(Isolation region)을 형성하게 된다.In general, in order to form transistors and capacitors on a semiconductor substrate, an isolation region is formed in the semiconductor substrate to prevent electrical conduction with an electrically energized active region and to separate devices from each other. Will form.

이와 같이, 소자를 분리시키기 위하여 패드산화막을 성장시켜 소자분리막을 형성시키기 위한 공정에는 반도체기판에 패드산화막과 나이트라이드막을 마스킹공정으로 나이트라이드막을 식각하고 그 식각된 소자분리영역이 형성될부위에 소자분리을 형성시키는 LOCOS공정(Local Oxidation of silicon)이 있으며, 그 외에 상기 LOCOS공정의 패드산화막과 나이트라이드막 사이에 버퍼역할을 하는 폴리실리콘막을 개재하여 완충역할을 하여 소자분리막을 성장시키는 PBL(Poly Buffered LOCOS)공정 등이 사용되고 있다.As described above, in the process of forming a device isolation film by growing a pad oxide film to separate the devices, the nitride film is etched by masking a pad oxide film and a nitride film on a semiconductor substrate, and the device is formed on the region where the etched device isolation region is to be formed. There is a LOCOS process (Local Oxidation of silicon) to form a separation, in addition to the PBL (Poly Buffered) to grow a device isolation layer by acting as a buffer through a polysilicon film that serves as a buffer between the pad oxide film and the nitride film of the LOCOS process LOCOS) process is used.

또한, 반도체기판에 일정한 깊이를 갖는 트렌치(Trench)를 형성하고서 이 트렌치에 산화막을 증착키고서 화학기계적연마공정(Chemical Mechanical Polishing)공정으로 이 산화막의 불필요한 부분을 식각하므로 소자분리영역을 반도체기판에 형성시키는 STI(Shallow Trench Isolation)공정이 최근에 많이 이용되고 있으며, 본 발명은 STI공정을 이용하여 소자분리막을 형성하는 새로운 공정을 제안하고 있다.In addition, by forming a trench having a constant depth in the semiconductor substrate, depositing an oxide film on the trench, and etching an unnecessary portion of the oxide film by a chemical mechanical polishing process, an element isolation region is formed on the semiconductor substrate. The STI (Shallow Trench Isolation) process is widely used in recent years, and the present invention proposes a new process for forming an isolation layer using the STI process.

종래의 반도체장치에서 트렌치를 형성하여 소자분리막을 형성하는 상태를 개략적으로 설명하면, 반도체기판 상에 소정의 두께를 갖고서 절연을 하도록 패드산화막을 적층하고, 그 위에 상,하층간에 보호 역할을 하는 나이트라이드막을 도포하고서, 감광막을 도포하여서 식각공정을 통하여 트렌치를 형성한다.In the semiconductor device, a trench is formed to form an isolation layer in a conventional semiconductor device. A pad oxide film is stacked on the semiconductor substrate to be insulated with a predetermined thickness, and a knight serves to protect the upper and lower layers thereon. A trench is formed by applying a ride film and then applying a photosensitive film to the etching process.

그리고, 이 트렌치가 형성된 부분에 전계효과(Field Effect) 집중으로 인한 누설 전류를 방지하기 위하여 트렌치의 내벽면을 산화 성장시켜 트렌치산화막을 형성한 후 소자분리막의 측면부분에 발생되는 모트(Moat)를 방지하기 위하여 라이너산화막(Liner Oxidation)의 트렌치의 내벽면에 재차 형성하도록 한다.Then, in order to prevent leakage current due to the concentration of field effects in the trench, the trench is formed by oxidizing and growing the inner wall of the trench to form a trench oxide film. In order to prevent this, it is formed again on the inner wall surface of the trench of the liner oxide film.

그리고, 연속하여 상기 트렌치내에 캡필링(Gap Filling)공정으로 캡필링산화막을 충진시킨 후에 식각으로 불필요한 부분을 제거하여 소자분리막을 형성하게 되는 것이다.Subsequently, after filling the trench with a cap filling oxide film in the trench, a device isolation film is formed by removing unnecessary portions by etching.

그런데, 상기한 바와 같이, 종래의 STI공정을 이용하여 소자분리막을 형성하는 경우 셀(Cell)지역 및 주변회로지역의 패드산화막의 식각이 심화되어 공극(Void) 현상이 발생되어지며, 이 공극부분에서 발생된 단차를 줄이기 위하여 화학기계적연마공정 및 후속 세정공정을 거치면서 소자분리막의 측면부분에 침강현상이 심화되어 모트(Moat)가 발생되는 것으로, 종래의 모트 형성 방지를 위하여 라이너 산화막을 트렌치내에 적층하더라도 충분하게 모트를 방지하지 못하는 문제점을 지니고 있었다.However, as described above, in the case of forming the device isolation layer using the conventional STI process, the etching of the pad oxide layer in the cell region and the peripheral circuit region is intensified, and thus a void phenomenon occurs. In order to reduce the step difference caused by the chemical mechanical polishing process and the subsequent cleaning process, the sedimentation phenomenon deepens in the side portion of the device isolation film, and moat is generated, and the liner oxide film is formed in the trench to prevent the formation of a conventional mote. Even lamination had a problem that does not sufficiently prevent the mort.

본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판상에 패드산화막 및 나이트라이드막을 적층하여 식각으로 트렌치를 형성하고 기판의 내벽면에 트렌치산화막을 형성한 후 세정공정을 수행하여 트렌치산화막을 제거하고, 이 트렌치내에 고압의 LP-TEOS 갭필링산화막을 증착하여 식각으로 형성한 소자분리막에 공극이 발생되는 것을 방지하는 것이 목적이다.The present invention has been made in view of the above-described problems, and a trench is formed by laminating a pad oxide film and a nitride film on a semiconductor substrate, forming a trench by etching, and forming a trench oxide film on the inner wall surface of the substrate to remove the trench oxide film. The purpose of the present invention is to prevent the generation of voids in the device isolation film formed by etching by depositing a high pressure LP-TEOS gap peeling oxide film in the trench.

도 1 내지 도 5는 본 발명에 따른 STI공정을 이용하여 소자분리막을 형성하는 상태를 도시한 도면이다.1 to 5 are views illustrating a state in which a device isolation film is formed using an STI process according to the present invention.

-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing

10 : 반도체기판 20 : 패드산화막10: semiconductor substrate 20: pad oxide film

30 : 나이트라이드막 40 : 감광막30: nitride film 40: photosensitive film

45 : 콘택부위 50 : 트렌치45: contact part 50: trench

55 : 트렌치산화막 60 : 갭필링산화막55 trench oxide film 60 gap gap oxide film

70 : 식각부위 80 : 소자분리막70: etching part 80: device isolation film

이러한 목적은 반도체기판 상에 패드산화막 및 나이트라이드막을 적층한 후 그 위에 소자분리막이 형성될 부분에 콘택부위를 갖는 감광막을 적층하는 단계와; 상기 단계 후에 감광막의 콘택부위를 통하여 트렌치를 형성한 후 이 트렌치의 반도체기판 내벽면에 데미지를 줄이도록 하는 트렌치산화막을 형성하는 단계와; 상기 단계 후에 트렌치산화막으로 반도체기판의 데미지를 줄인 후 트렌치산화막에서 불필요한 부분을 세정공정으로 제거하는 단계와; 상기 단계 후에 트렌치 내에 고압의 상태에서 갭필링산화막을 적층한 후 어닐링공정으로 조직을 균질화하고, 연이서 갭필링산화막을 연마공정 및 세정공정으로 소자분리막으로 형성하는 단계로 이루어진 반도체소자의 소자분리막 형성방법을 제공함으로써 달성된다.The object of the present invention is to laminate a pad oxide film and a nitride film on a semiconductor substrate, and then, depositing a photoresist film having a contact portion on a portion where a device isolation film is to be formed; Forming a trench through the contact portion of the photoresist film after the step and forming a trench oxide film to reduce damage on the inner wall of the semiconductor substrate of the trench; Reducing the damage of the semiconductor substrate with the trench oxide film after the step, and then removing unnecessary portions of the trench oxide film by a cleaning process; After the step of forming a device isolation film of the semiconductor device comprising the step of laminating a gap peeling oxide film in the trench at high pressure, homogenizing the structure by an annealing process, and subsequently forming the gap peeling oxide film as a device isolation film by a polishing process and a cleaning process. By providing a method.

그리고, 상기 트렌치산화막은 950 ∼ 1200℃의 온도에서 50 ∼ 1000Å의 두께로 형성하고, 상기 갭필링산화막은 LP-TEOS산화막을 3500 ∼ 7000Å의 두께로 적층하며, 상기 갭필링산화막은 1 ∼ 5 Torr의 압력과 500 ∼ 800℃의 온도로 적층하도록 한다.The trench oxide film is formed at a thickness of 50 to 1000 kPa at a temperature of 950 to 1200 ° C., and the gap peeling oxide film is laminated to an LP-TEOS oxide film at a thickness of 3500 to 7000 kPa, and the gap peeling oxide film is 1 to 5 Torr. It is laminated at a pressure of 500 to 800 ° C.

또한, 상기 갭필링산화막은 10 ∼ 1000sccm의 TEOS가스와, 1000sccm이하의 N2가스와, 100이하의 O2가스를 사용하여 형성하도록 하고, 상기 갭필링산화막은 In-Situ공정으로 복수개의 층을 적층하여 하나의 층으로 형성하도록 한다.The gap peeling oxide film may be formed using a TEOS gas of 10 to 1000 sccm, an N 2 gas of 1000 sccm or less, and an O 2 gas of 100 or less, and the gap peeling oxide film may be formed of a plurality of layers by an in-situ process. It is laminated to form one layer.

이하, 첨부한 도면에 의거하여 본 발명의 바람직한 일실시예에 대하여 상세히 살펴보도록 한다.Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 반도체기판(10) 상에 15 ∼ 200Å정도의 두께로 패드산화막(20)을 적층하고, 연속하여 그 위에 식각방지막으로서 작용하도록 나이트라이드막(30)을 500 ∼ 4000Å정도의 두께로 증착한 후 그 위에 소자분리막이 형성될 부분에 콘택부위(45)를 갖는 감광막(40)을 적층하는 상태를 도시하고 있다.1, the pad oxide film 20 is laminated on the semiconductor substrate 10 with a thickness of about 15 to 200 microns, and the nitride film 30 is subsequently deposited to a thickness of about 500 to 4000 microns to act as an etch stop layer thereon. After that, the photoresist film 40 having the contact portion 45 is laminated on the portion where the device isolation film is to be formed.

도 2는 상기 단계 후에 감광막(40)의 콘택부위(45)를 통하여 트렌치(50)를 1500 ∼ 6000Å정도의 깊이로 형성하고, 이 트렌치(50)의 반도체기판(10) 내벽면에 데미지(Damage)를 줄이도록 하는 트렌치산화막(55)을 950 ∼ 1200℃의 온도에서 50 ∼ 1000Å의 두께로 형성하는 상태를 도시하고 있다.FIG. 2 shows that the trench 50 is formed to a depth of about 1500 to 6000 microns through the contact portion 45 of the photoresist film 40 after the above step, and damage to the inner wall surface of the semiconductor substrate 10 of the trench 50 is shown. The trench oxide film 55 is formed to have a thickness of 50 to 1000 Pa at a temperature of 950 to 1200 占 폚.

도 3은 상기 단계 후에 트렌치산화막(55)으로 반도체기판(10)의 데미지를 줄인 후 트렌치산화막(55)에서 불필요한 부분을 세정공정으로 제거하고, 이 트렌치(50)내에 고압의 상태에서 갭필링산화막(60)을 적층한 후 800 ∼ 1200℃의 온도로 어닐링(Annealing)공정을 진행하여 조직을 균질화하는 상태를 도시하고 있다.3 shows that the trench oxide film 55 reduces damage of the semiconductor substrate 10 after the step, and then removes unnecessary portions of the trench oxide film 55 by a cleaning process, and a gap peeling oxide film is formed at a high pressure in the trench 50. After laminating (60), the annealing process is performed at the temperature of 800-1200 degreeC, and the state which homogenizes a structure is shown.

이때, 상기 갭필링산화막(60)은 LP-TEOS산화막을 3500 ∼ 7000Å의 두께로 적층하고, 1 ∼ 5 Torr의 압력과 500 ∼ 800℃의 온도로 적층하도록 한다.At this time, the gap peeling oxide film 60 is laminated to the LP-TEOS oxide film to a thickness of 3500 ~ 7000 kPa, a pressure of 1 to 5 Torr and a temperature of 500 ~ 800 ℃.

그리고, 상기 갭필링산화막(60)은 10 ∼ 1000sccm의 TEOS가스와, 1000sccm이하의 N2가스와, 100sccm이하의 O2가스를 사용하여 인-시튜(In-Situ)공정으로 복수개의 층을 적층하여 하나의 층으로 형성하는 복층구조(예를들면, 두 개의 층이 각각 2500Å의 두께를 갖고, 이 두층이 겹쳐져서 한 층을 이루어 5000Å의 두께인 복층을 형성한 경우)를 이루도록 한다.The gap peeling oxide layer 60 is formed by stacking a plurality of layers by an in-situ process using a TEOS gas of 10 to 1000 sccm, an N 2 gas of 1000 sccm or less, and an O 2 gas of 100 sccm or less. To form a multi-layer structure (for example, when two layers each have a thickness of 2500 mW, and the two layers overlap to form a multi-layered layer having a thickness of 5000 mW).

도 4는 상기 갭필링산화막(60)을 화학기계적연마(CMP; Chemical Mechanical polishing)공정 및 세정공정을 수행하여 반도체기판(10)으로 150 ∼500Å 정도 높이로 돌출된 상태를 도시하고 있다.FIG. 4 illustrates a state in which the gap peeling oxide layer 60 protrudes to the semiconductor substrate 10 at a height of about 150 to 500 kPa by performing a chemical mechanical polishing (CMP) process and a cleaning process.

도 5는 상기 갭필링산화막(60)이 식각된 후의 잔류된 나이트라이드막(30)을 제거하여 소자분리막(80)을 최종적으로 형성하는 상태를 도시하고 있다.FIG. 5 illustrates a state in which the device isolation layer 80 is finally formed by removing the nitride layer 30 remaining after the gap filling oxide layer 60 is etched.

따라서, 상기한 바와 같이 본 발명에 따른 반도체장치의 소자분리막 형성방법을 이용하게 되면, 반도체기판상에 패드산화막 및 나이트라이드막을 적층하여 식각으로 트렌치를 형성하고 기판의 내벽면에 트렌치산화막을 형성한 후 세정공정을 수행하여 트렌치산화막을 제거하고, 이 트렌치내에 고압의 상태에서 LP-TEOS 갭필링산화막을 증착하여 식각으로 형성한 소자분리막에 공극이 발생되는 것을 방지하므로 반도체소자의 성능 향상시키도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the device isolation film forming method of the semiconductor device according to the present invention is used, a trench is formed by etching a pad oxide film and a nitride film on a semiconductor substrate, and a trench oxide film is formed on an inner wall surface of the substrate. A post-cleaning process is performed to remove the trench oxide film, and the LP-TEOS gap peeling oxide film is deposited in the trench at high pressure to prevent voids in the device isolation film formed by etching, thereby improving performance of the semiconductor device. It is a very useful and effective invention.

Claims (6)

반도체기판 상에 패드산화막 및 나이트라이드막을 적층한 후 그 위에 소자분리막이 형성될 부분에 콘택부위를 갖는 감광막을 적층하는 단계와;Stacking a pad oxide film and a nitride film on a semiconductor substrate and then stacking a photosensitive film having a contact portion on a portion where a device isolation film is to be formed; 상기 단계 후에 감광막의 콘택부위를 통하여 트렌치를 형성한 후 이 트렌치의 반도체기판 내벽면에 트렌치산화막을 형성하는 단계와;Forming a trench through the contact portion of the photosensitive film after the step, and then forming a trench oxide film on the inner wall of the semiconductor substrate of the trench; 상기 단계 후에 트렌치산화막에서 불필요한 부분을 세정공정으로 제거하는 단계와;Removing unnecessary portions of the trench oxide film by a cleaning process after the step; 상기 단계 후에 트렌치 내에 고압의 상태에서 갭필링산화막으로서 LP-TEOS 막을 형성한 후 어닐링공정으로 조직을 균질화하고, 연이서 연마공정 및 세정공정을 하여 소자분리막으로 형성하는 단계를 포함한 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.After the step of forming a LP-TEOS film as a gap peeling oxide film in the trench at high pressure, homogenizing the structure by an annealing process, and subsequently forming a device isolation film by performing a polishing process and a cleaning process Device isolation film formation method of the device. 제 1 항에 있어서, 상기 트렌치산화막은 950 ∼ 1200℃의 온도에서 50 ∼ 1000Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.The method of claim 1, wherein the trench oxide film is formed to a thickness of 50 to 1000 Pa at a temperature of 950 to 1200 ℃. 제 1 항에 있어서, 상기 갭필링산화막은 3500 ∼ 7000Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.2. The method of claim 1, wherein the gap filling oxide film is formed to a thickness of 3500 to 7000 GPa. 제 1 항 또는 제 2 항에 있어서, 상기 갭필링산화막은 1 ∼ 5 Torr의 압력과 500 ∼ 800℃의 온도로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.The method of claim 1 or 2, wherein the gap peeling oxide film is formed at a pressure of 1 to 5 Torr and a temperature of 500 to 800 ° C. 제 1 항 또는 제 2 항에 있어서, 상기 갭필링산화막은 10 ∼ 1000sccm의 TEOS가스와, 1000sccm이하의 N2가스와, 100이하의 O2가스를 사용하여 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.The semiconductor device according to claim 1 or 2, wherein the gap peeling oxide film is formed using a TEOS gas of 10 to 1000 sccm, an N 2 gas of 1000 sccm or less, and an O 2 gas of 100 or less. Separator Formation Method. 제 1 항 또는 제 2 항에 있어서, 상기 갭필링산화막은 In-Situ공정으로 복수개의 층을 적층하여 하나의 층으로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.The method of claim 1, wherein the gap peeling oxide film is formed by stacking a plurality of layers by an In-Situ process to form a single layer.
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