KR100687857B1 - Method For Forming The Isolation Layer Using The Trench - Google Patents
Method For Forming The Isolation Layer Using The Trench Download PDFInfo
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- KR100687857B1 KR100687857B1 KR1020000076468A KR20000076468A KR100687857B1 KR 100687857 B1 KR100687857 B1 KR 100687857B1 KR 1020000076468 A KR1020000076468 A KR 1020000076468A KR 20000076468 A KR20000076468 A KR 20000076468A KR 100687857 B1 KR100687857 B1 KR 100687857B1
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- 238000002955 isolation Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 125000006850 spacer group Chemical group 0.000 claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 238000007517 polishing process Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 230000006866 deterioration Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 12
- 238000000151 deposition Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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Abstract
본 발명은, 트렌치를 이용한 소자분리산화막 형성방법에 관한 것으로서, 특히, 반도체기판 상에 패드산화막 및 CVD질화막을 적층하고, 트렌치형성부위에 패턴을 형성하고, 이 CVD질화막의 내측벽면에 스페이서산화막을 형성한 후, 반도체기판에 트렌치를 형성하고, 이 트렌치 내부에 소자분리막을 과도식각하여 형성한 후 트렌치의 모서리부분에 열산화막을 형성하고, 이 결과물 상에 캡핑층을 적층하여서 식각하므로 소자의 전기적인 특성이 저하되는 것을 방지하도록 하는 매우 유용하고 효과적인 발명에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation oxide film using a trench, and in particular, a pad oxide film and a CVD nitride film are laminated on a semiconductor substrate, a pattern is formed on the trench formation portion, and a spacer oxide film is formed on the inner wall surface of the CVD nitride film. After the formation, a trench is formed in the semiconductor substrate, the device isolation film is excessively etched into the trench, and then a thermal oxide film is formed at the corner of the trench, and a capping layer is stacked on the resultant to be etched. The invention relates to a very useful and effective invention to prevent the deterioration of the characteristics.
트렌치 CVD질화막 스페이서막 갭필링산화막 Trench CVD Nitride Spacer Gap Filling Oxide
Description
도 1 내지 도 7은 본 발명의 소자분리산화막 형성방법을 순차적으로 보인 도면이다.
1 to 7 are views sequentially showing a method of forming a device isolation oxide film of the present invention.
-도면의 주요부분에 대한 부호의 설명- Explanation of symbols on the main parts of the drawing
10 : 반도체기판 15 : 패드산화막10: semiconductor substrate 15: pad oxide film
20 : 패드질화막 25 : 트렌치20: pad nitride film 25: trench
30 : 스페이서산화막 35 : 갭필링산화막30
35' : 소자분리산화막 40 : 열산화막35 ': device isolation oxide film 40: thermal oxide film
45 : 캡핑층 50 : CVD산화막45
본 발명은 트렌치(Trench)를 이용하여 소자분리산화막을 형성하는 방법에 관한 것으로서, 특히, 반도체기판 상에 패드산화막 및 CVD질화막을 적층하고, 트렌치형성부위에 패턴을 형성하고, 이 CVD질화막의 내측벽면에 스페이서산화막을 형성한 후, 반도체기판에 트렌치를 형성하고, 이 트렌치 내부에 소자분리막을 과도식각하여 형성한 후 트렌치의 모서리부분에 열산화막을 형성하고, 이 결과물 상에 캡핑층을 적층하여서 식각을 하므로 소자의 전기적인 특성이 저하되는 것을 방지하도록 하는 트렌치를 이용한 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation oxide film using a trench, and in particular, a pad oxide film and a CVD nitride film are laminated on a semiconductor substrate, a pattern is formed on the trench formation portion, and the inside of the CVD nitride film is formed. After the spacer oxide film is formed on the wall surface, a trench is formed in the semiconductor substrate, the device isolation film is excessively etched in the trench, and a thermal oxide film is formed on the corner of the trench, and a capping layer is laminated on the resultant. The present invention relates to a method of forming a device isolation layer using a trench for etching to prevent deterioration of electrical characteristics of a device.
일반적으로, 반도체기판 상에 트랜지스터와 커패시터등을 형성하기 위하여 반도체기판에는 전기적으로 통전이 가능한 활성영역(Active Region)과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리영역(Isolation region)을 형성하게 된다. In general, in order to form transistors and capacitors on a semiconductor substrate, an isolation region is formed in the semiconductor substrate to prevent electrical conduction with an electrically energized active region and to separate devices from each other. Will form.
이와 같이, 소자를 분리시키기 위하여 패드산화막을 성장시켜 형성되는 필드산화막을 형성시키기 위한 공정에는 반도체기판에 패드산화막과 나이트라이드막을 마스킹공정으로 나이트라이드막을 식각하고 그 식각된 소자분리영역이 형성될 부위에 필드산화막(이하; 소자분리산화막이라 함)을 형성시키는 LOCOS공정(Local Oxidation of silicon)이 있으며, 그 외에 상기 LOCOS공정의 소자분리산화막과 나이트라이드막 사이에 버퍼역할을 하는 폴리실리콘막을 개재하여 완충역할을 하여 산화막을 성장시키는 PBL(Poly Buffered LOCOS)공정 등이 사용되고 있다. As such, in the process for forming the field oxide film formed by growing the pad oxide film to separate the devices, the nitride film is etched by masking the pad oxide film and the nitride film on the semiconductor substrate and the etched device isolation region is formed. There is a LOCOS process (Local Oxidation of Silicon) to form a field oxide film (hereinafter referred to as a device isolation oxide film), and in addition, a polysilicon film acting as a buffer between the device isolation oxide film and the nitride film of the LOCOS process PBL (Poly Buffered LOCOS) process for growing an oxide film by acting as a buffer is used.
또한, 반도체기판에 일정한 깊이를 갖는 트렌치(Trench)를 형성하고서 이 트렌치에 산화막을 증착시켜 화학기계적연마(Chemical Mechanical Polishing)공정으로 이 산화막의 불필요한 부분을 식각하므로 소자분리영역을 반도체기판에 형성시 키는 STI(Shallow Trench Isolation)공정이 최근에 많이 이용되고 있다, 본 발명은 STI공정을 이용하여 소자분리산화막을 형성하는 새로운 공정을 제안하고 있다. In addition, by forming a trench having a predetermined depth in the semiconductor substrate and depositing an oxide film on the trench, the chemical mechanical polishing process is used to etch unnecessary portions of the oxide film to form device isolation regions in the semiconductor substrate. The key is a recent STI (Shallow Trench Isolation) process has been widely used, the present invention proposes a new process for forming a device isolation oxide film using the STI process.
종래의 소자분리 산화막 형성방법을 순차적으로 살펴 보면, 반도체기판 상에패드산화막을 적층하고, 그 위에 상,하층간에 보호 역할을 하는 질화막을 도포하고서, 트렌치를 형성할 부분의 질화막 상에 마스킹 식각공정으로 트렌치(Trench)를 형성하도록 한다.Referring to the conventional method of forming a device isolation oxide film, a pad oxide film is laminated on a semiconductor substrate, a nitride film acting as a protective layer is applied on the upper and lower layers, and a masking etching process is performed on the nitride film of the portion where the trench is to be formed. To form trenches.
그리고, 상기 트렌치의 내부에 갭필링산화막을 매립하여서 화학기게적연마법으로 갭필링산화막을 평탄화하여 소자분리산화막을 형성 한 후, 소자분리산화막의 모서리부분에 산화막을 CVD증착법으로 증착하여 식각을 진행하여 스페이서막을 형성하도록 한다.Then, the gap filling oxide film is embedded in the trench to planarize the gap peeling oxide film by chemical mechanical polishing to form a device isolation oxide film, and then an oxide film is deposited on the edge of the device isolation oxide film by CVD deposition to perform etching. A spacer film is formed.
그런데, STI공정을 이용하여 소자분리산화막 형성공정에서 트렌치의 탑 모서리부분의 리세스(모트부; Moat) 및 후속공정에서 열 사이클(Heat Cycle) 공정에서 수분침투에 의한 STI측면부의 옥시데이션 인헨스 스트레스(Oxidation Enhanced Stress)가 발생되고, 보론 분리현상에 의한 문턱전압(Threshold Voltage)의 저하를 유발하고 이로 인하여 결함증가 및 문턱전압 임플랜트 도오즈량의 증가로 인하여 디램셀 트랜지스터(DRAM Cell Transitor)의 리프레쉬 시간을 악화시키므로 결함요소(Cricital Factor)로 작용하는 문제점을 지닌다. However, by using the STI process, the oxidative enhancement of the recess at the top edge of the trench (Moat) in the device isolation oxide film forming process and the STI side part by moisture penetration in the heat cycle process in the subsequent process Oxidation Enhanced Stress is generated, which causes the threshold voltage to be lowered due to boron separation, thereby increasing defects and increasing the dose voltage of the implant voltage of the DRAM cell transistor. Deteriorating the refresh time has a problem that acts as a defect factor (Cricital Factor).
이와 같은 문제를 개선하기 위하여 STI후 라이너(Liner) 열산화막을 형성한 후, 얇은 질화막을 사용하여서 이를 개선하는 방법을 사용하기도 하지만 이는 반도체기판의 실리콘을 뒤틀리게 하는 문제를 지니며, 트렌치의 탑 코너(Top Corner)부 위의 리세스에 의한 모트 부위 발생을 억제하는 한계를 지닌 단점을 지닌다.
In order to improve this problem, a post-STI liner thermal oxide film may be formed, and then a thin nitride film may be used to improve it. (Top Corner) has the disadvantage of having a limit of suppressing the generation of the mote by the recess on the top.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판 상에 패드산화막 및 CVD질화막을 적층하고, 트렌치형성부위에 패턴을 형성하고, 이 CVD질화막의 내측벽면에 스페이서산화막을 형성한 후, 반도체기판에 트렌치를 형성하고, 이 트렌치 내부에 소자분리막을 과도식각하여 형성한 후 트렌치의 모서리부분에 열산화막을 형성하고, 이 결과물 상에 캡핑층을 적층하여서 식각하므로 소자의 전기적인 특성이 저하되는 것을 방지하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and a semiconductor substrate is formed by laminating a pad oxide film and a CVD nitride film on a semiconductor substrate, forming a pattern on the trench formation portion, and forming a spacer oxide film on the inner wall surface of the CVD nitride film. A trench is formed in the trench, the device isolation film is excessively etched into the trench, a thermal oxide film is formed at the corners of the trench, and a capping layer is stacked on the resultant to etch to reduce the electrical characteristics of the device. The purpose is to prevent.
이러한 목적은, 반도체기판 상에 패드산화막 및 CVD질화막을 적층한 후, 소자분리산화막이 형성될 부위를 개방하도록 패드산화막 및 CVD질화막을 식각하는 단계와; 상기 CVD질화막의 내벽면에 스페이서산화막을 라운드지게 형성한 후, 식각공정으로 반도체기판에 트렌치를 형성하는 단계와; 상기 트렌치의 내부에 갭필링산화막을 매립한 후, 화학기계적연마공정으로 트렌치의 상부 라운드부분이 드러나도록 스페이서산화막 및 갭필링산화막을 연마하여 소자분리산화막을 형성하는 단계와; 상기 트렌치의 상부 모서리부분을 라운드지게 형성하기 위하여 열산화막을 형성한 후, 결과물 상에 캡핑층(Capping)을 적층하는 단계와; 상기 캡핑층의 함몰부위에 CVD산화막을 매립한 후, 소자분리영역만 CVD산화막이 남고 패드산화막이 노출되도록 식각하는 단계와; 상기 결과물에서 잔류된 CVD산화막 및 실리콘기판 상의 패드산화막을 식각으로 모두 제거하는 단계를 포함하여 트렌치를 이용한 소자분리산화막 형성방법을 제공함으로써 달성된다.The object of the present invention is to stack a pad oxide film and a CVD nitride film on a semiconductor substrate, and then etching the pad oxide film and the CVD nitride film to open a portion where the device isolation oxide film is to be formed; Forming a trench in the semiconductor substrate by etching the spacer oxide film roundly formed on the inner wall surface of the CVD nitride film; Filling the gap filling oxide film in the trench, and then polishing the spacer oxide film and the gap peeling oxide film to expose the upper round portion of the trench by a chemical mechanical polishing process to form a device isolation oxide film; Depositing a capping layer on the resultant after forming a thermal oxide film to roundly form an upper corner portion of the trench; Embedding the CVD oxide film in the recessed portion of the capping layer, and then etching the device isolation region so that the CVD oxide film remains and the pad oxide film is exposed; It is achieved by providing a method of forming a device isolation oxide film using a trench, including the step of removing all of the remaining CVD oxide film and the pad oxide film on the silicon substrate by etching.
그리고, 상기 스페이서산화막은, 50 ∼ 500Å의 두께로 적층하는 것이 바람직 하다.The spacer oxide film is preferably laminated at a thickness of 50 to 500 GPa.
그리고, 상기 트렌치의 깊이는, 0.1 ∼ 0.5㎛인 것이 바람직 하다.And it is preferable that the depth of the said trench is 0.1-0.5 micrometer.
또한, 상기 소자분리산화막을 형성할 때, 50 ∼ 1000Å의 두께를 과도식각하도록 한다.In addition, when the device isolation oxide film is formed, a thickness of 50 to 1000 kPa is excessively etched.
그리고, 상기 캡핑층은, 50 ∼ 1000Å의 두께로 적층되는 것이 바람직 하다.The capping layer is preferably laminated to a thickness of 50 to 1000 kPa.
이하, 첨부한 도면에 의거하여 본 발명에 따른 트렌치를 이용한 소자분리산화막 형성방법에 대하여 상세히 살펴보도록 한다. Hereinafter, a device isolation oxide film forming method using a trench according to the present invention will be described in detail with reference to the accompanying drawings.
도 1에 도시된 바와 같이, 반도체기판(10) 상에 패드산화막(15) 및 CVD질화막(20)을 적층한 후, 소자분리산화막이 형성될 부위를 개방하도록 패드산화막(15) 및 CVD질화막(20)을 식각하도록 한다.As shown in FIG. 1, after the
그리고, 상기 CVD질화막(20)의 내벽면에 스페이서산화막(30)을 형성하고 이를 블랭킷 식각하여 라운드지게 형성한 후, 식각공정으로 반도체기판(10)에 트렌치(25)를 형성하도록 한다.Then, the
상기 트렌치(25)의 깊이는, 0.1 ∼ 0.5㎛인 것이 바람직 하다. It is preferable that the depth of the said
이 때, 상기 스페이서산화막(30)은, 50 ∼ 500Å의 두께로 적층하도록 한다.At this time, the
도 2 및 도 3에 도시된 바와 같이, 상기 트렌치(25)의 내부에 갭필링산화막을 매립한 후, 화학기계적연마공정으로 트렌치(25)의 상부 라운드부분이 드러나도 록 스페이서산화막(30) 및 갭필링산화막(35)을 연마하여 소자분리산화막(35')을 형성하도록 한다.As shown in FIG. 2 and FIG. 3, after the gap filling oxide film is buried in the
그리고, 상기 트렌치(25)의 상부 라운드부분을 라운드지게 형성하기 위하여 열산화막(40)을 형성하도록 한다.Then, the
상기 소자분리산화막(35')을 형성할 때, 50 ∼ 1000Å의 두께를 과도식각하여 반도체기판(10)의 모서리부분이 드러나도록 하는 것이 바람직 하다.When the device isolation oxide film 35 'is formed, it is preferable that the edge portion of the
그리고, 도 4에 도시된 바와 같이, 상기 결과물 상에 캡핑층(45)을 적층하도록 한다.As shown in FIG. 4, the
상기 캡핑층(45)은, 50 ∼ 1000Å의 두께로 적층되는 것이 바람직 하다.The
도 5에 도시된 바와 같이, 상기 캡핑층(45)의 함몰부위에 CVD산화막(50)을 매립하도록 한다.As shown in FIG. 5, the
도 6에 도시된 바와 같이, 상기 소자분리영역만 CVD산화막(50)이 남고, 패드산화막(15)이 노출되게 식각하도록 한다.As shown in FIG. 6, only the device isolation region is etched such that the
도 7에 도시된 바와 같이, 상기 결과물에서 잔류된 CVD산화막(50) 및 실리콘기판(10) 상에 있는 패드산화막(15)을 식각으로 모두 제거하도록 한다.
As shown in FIG. 7, the
따라서, 상기한 바와 같이, 본 발명에 따른 트렌치를 이용한 소자분리산화막 형성방법을 이용하게 되면, 반도체기판 상에 패드산화막 및 CVD질화막을 적층하고, 트렌치형성부위에 패턴을 형성하고, 이 CVD질화막의 내측벽면에 스페이서산화막을 형성한 후, 반도체기판에 트렌치를 형성하고, 이 트렌치 내부에 소자분리막을 과도식각하여 형성한 후 트렌치의 모서리부분에 열산화막을 형성하고, 이 결과물 상에 캡핑층을 적층하여서 식각하므로 소자의 전기적인 특성이 저하되는 것을 방지하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the device isolation oxide film forming method using the trench according to the present invention is used, a pad oxide film and a CVD nitride film are laminated on a semiconductor substrate, a pattern is formed on the trench forming portion, and the CVD nitride film is formed. After the spacer oxide film is formed on the inner wall surface, a trench is formed in the semiconductor substrate, the device isolation film is excessively etched in the trench, and a thermal oxide film is formed on the corner of the trench, and a capping layer is stacked on the resultant. It is a very useful and effective invention to prevent the degradation of the electrical properties of the device by etching.
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