KR20030068832A - Method of fabricating CMOS devices - Google Patents
Method of fabricating CMOS devices Download PDFInfo
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- KR20030068832A KR20030068832A KR1020020008477A KR20020008477A KR20030068832A KR 20030068832 A KR20030068832 A KR 20030068832A KR 1020020008477 A KR1020020008477 A KR 1020020008477A KR 20020008477 A KR20020008477 A KR 20020008477A KR 20030068832 A KR20030068832 A KR 20030068832A
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- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 150000002500 ions Chemical class 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 16
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 3
- 150000004706 metal oxides Chemical class 0.000 abstract description 3
- 230000000295 complement effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Abstract
Description
본 발명은 씨모스 소자의 제조 방법에 관한 것으로, 보다 상세하게는, 씨모스 소자를 제조하기 위한 제조공정을 단순화한 씨모스 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a CMOS device, and more particularly, to a method for manufacturing a CMOS device, which simplifies a manufacturing process for manufacturing a CMOS device.
씨모스(CMOS) 소자는 대개 NMOS(N-type Metal Oxide Semiconductor) 및PMOS(P-type Metal Oxide Semiconductor) 트랜지스터들로 이루어지고, 상기 트랜지스터들의 형성공정은 서로 동일하다.CMOS devices are usually composed of N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) transistors, and the process of forming the transistors is the same.
종래의 씨모스 소자의 제조기술에서는 예를 들면, 0.5㎛ 1폴리(Poly) 3메탈(Metal) 로직 프로세스의 경우 필요로 하는 마스크의 수가 14개이고, 포토레지스트의 수가 17개가 요구된다.In the conventional CMOS device fabrication technique, for example, in the case of a 0.5 µm 1 poly 3 metal logic process, the number of masks required is 14 and the number of photoresists is required 17.
이러한 마스크 및 포토레지스트가 사용되는 예를 도면을 참조하여 설명한다. 도 1a 내지 도 1d는 종래의 씨모스 소자의 제조과정을 보여주는 공정 단면도이다.An example in which such a mask and photoresist is used will be described with reference to the drawings. 1A to 1D are cross-sectional views illustrating a manufacturing process of a conventional CMOS device.
먼저, 도 1a를 참조하면, 반도체 기판(10)에 P-웰(Well, 12)과 N-웰(14)을 형성하고 LOCOS(LOCal Oxidation of Silicon)에 의한 산화막(16)을 형성한 후 N-웰(14) 영역에 포토레지스트를 도포한 후 노광 및 현상에 의한 마스크(18)를 형성한다. 상기 마스크(18)가 형성되어 있지 않은 P-웰(12) 영역에는 NMOS 채널 형성용 이온주입을 실시한다.First, referring to FIG. 1A, a P-well 12 and an N-well 14 are formed on a semiconductor substrate 10, and an oxide film 16 formed by LOCOS (LOCal Oxidation of Silicon) is formed. After the photoresist is applied to the well 14 region, a mask 18 is formed by exposure and development. NMOS channel formation ion implantation is performed in the region of the P-well 12 where the mask 18 is not formed.
도 1b를 참조하면, NMOS 채널 형성을 위한 이온주입이 완료되면 마스크(18)를 제거한 후에 P-웰(12) 영역에 마스크(20)를 형성하여 PMOS 채널 형성을 위한 이온주입이 이루어진다. 그리고, 마스크(20)는 제거된다.Referring to FIG. 1B, when the ion implantation for forming the NMOS channel is completed, the mask 18 is removed and then the mask 20 is formed in the P-well 12 region to perform ion implantation for forming the PMOS channel. Then, the mask 20 is removed.
도 1c를 참조하면, 폴리막(22)이 형성된 후 NMOS/PMOS 접합(Junction) 형성을 위한 이온주입이 이루어진다. 포토레지스트를 이용한 마스크(24)가 P-웰(12) 영역에 형성되고, N-웰(14) 영역에 이온주입이 실시된다. 그리고, 이온주입이 완료되면 도 1d에서 보는 바와 같이, 마스크(24)가 제거되고, 반대로 N-웰(14) 영역에 마스크(26)가 형성되고 P-웰(12) 영역에 이온주입이 실시된다.Referring to FIG. 1C, after the poly film 22 is formed, ion implantation for forming an NMOS / PMOS junction is performed. A mask 24 using photoresist is formed in the P-well 12 region, and ion implantation is performed in the N-well 14 region. When the ion implantation is completed, as shown in FIG. 1D, the mask 24 is removed, on the contrary, the mask 26 is formed in the N-well 14 region and the ion implantation is performed in the P-well 12 region. do.
이와 같이 살펴본 바와 같이, 종래의 씨모스 소자 제조과정은, P-웰 및 N-웰에 불순물을 주입하기 위해 반복적으로 마스크를 형성하기 때문에 그에 따른 공정증가와 더불어 제조비용이 증가되는 문제점을 안고 있다.As described above, the conventional CMOS device manufacturing process has a problem in that the manufacturing cost is increased and the manufacturing cost is increased because the mask is repeatedly formed to inject impurities into the P-well and the N-well. .
상기의 문제점을 해결하기 위한 본 발명의 목적은, 씨모스 소자의 제조공정을 단순화하여 제조비용을 절감하기 위한 씨모스 소자의 제조 방법을 제공하는 것이다.An object of the present invention for solving the above problems is to provide a method for manufacturing a CMOS device for reducing the manufacturing cost by simplifying the manufacturing process of the CMOS device.
본 발명의 다른 목적은, 씨모스 소자의 제조시 마스크를 형성하지 않은 상태에서 이온주입을 블랭크로 실시하여 별도의 마스크 형성공정이 생략되어 공정단순화를 이루도록 하는 씨모스 소자의 제조 방법을 제공하는 것이다.It is another object of the present invention to provide a method for manufacturing a CMOS device, in which the implantation is performed by a blank in the state where a mask is not formed at the time of manufacturing the CMOS device, thereby eliminating a separate mask forming step, thereby achieving a process simplification. .
도 1a 내지 도 1d는 종래의 씨모스 소자의 제조과정 중 일부를 보여주는 공정 단면도이다.1A to 1D are cross-sectional views illustrating a part of a manufacturing process of a conventional CMOS device.
도 2a 내지 도 2d는 본 발명의 씨모스 소자의 제조과정에 대한 실시예를 보여주는 공정 단면도이다.2A to 2D are cross-sectional views illustrating an embodiment of a manufacturing process of the CMOS device of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10, 30 : 반도체 기판12, 32 : P-웰10, 30: semiconductor substrate 12, 32: P-well
14, 34 : N-웰16, 36 : 산화막14, 34: N-well 16, 36: oxide film
18, 20, 22, 26, 38, 42 : 포토레지스트18, 20, 22, 26, 38, 42: photoresist
22, 40 : 폴리막22, 40: poly film
상기 목적을 달성하기 위한 본 발명에 의한 씨모스 소자의 제조 방법은, 반도체 기판에 피(P)-웰과 엔(N)-웰을 형성하고, 산화막을 형성하는 단계와, 엔모스(NMOS) 채널 조절을 위한 제 1 이온이 블랭크 상태로 상기 반도체 기판 전면에 주입되는 단계와, 상기 제 1 이온이 주입된 후, 반도체 기판 전면에 제 1 포토레지스트를 도포하여 피(P)-마스크를 사용하며 피모스(PMOS) 영역의 포토레지스트를 제거하는 단계와, 상기 포토레지스트가 제거된 반도체 기판에 피모스 채널 조정용 제 2 이온이 주입되는 단계와, 상기 제 1 포토레지스트를 제거한 후 폴리막질을 형성하는 단계와, 상기 폴리막질이 형성된 후 모스 접합 형성을 위한 제 3 이온이 주입되는 단계와, 상기 제 3 이온이 주입된 후 제 2 포토레지스트를 도포하여엔(N)-마스크를 사용하고 엔모스 영역의 포토레지스트를 제거하는 단계와, 상기 포토레지스트가 제거된 영역에 엔모스용 제 4 이온을 주입하는 단계, 그리고, 상기 제 2 포토레지스트를 제거하는 단계를 포함하는 것을 특징으로 한다.The method for manufacturing a CMOS device according to the present invention for achieving the above object comprises the steps of forming a P-well and an N-well on a semiconductor substrate, forming an oxide film, and an NMOS. Implanting the first ions for channel control in the blank state onto the front surface of the semiconductor substrate, and applying the first photoresist to the front surface of the semiconductor substrate after the first ions are implanted, thereby using a P-mask. Removing the photoresist in the PMOS region, implanting second ions for PMOS channel adjustment into the semiconductor substrate from which the photoresist is removed, and forming a poly film after removing the first photoresist; And implanting third ions for forming a MOS junction after the polymembrane is formed, and applying a second photoresist after implanting the third ions to use an N-mask and an enmos region. Photos of And removing the registry, implanting ions for the fourth region of the photoresist is removed NMOS, and further characterized in that it comprises a step of removing the second photoresist.
이때 상기 제 3 이온의 주입은 상기 반도체 기판 전면에 걸쳐서 포토레지스트를 도포하지 않고 블랭크 상태로 실시되는 것이 바람직하다.In this case, the implantation of the third ions is preferably performed in a blank state without applying a photoresist over the entire surface of the semiconductor substrate.
이하, 본 발명의 실시예에 대한 설명은 첨부된 도면을 참조하여 더욱 상세하게 설명한다. 아래에 기재된 본 발명의 실시예는 본 발명의 기술적 사상을 예시적으로 설명하기 위한 것에 불과한 것으로, 본 발명의 권리범위가 여기에 한정되는 것으로 이해되어서는 안될 것이다. 아래의 실시예로부터 다양한 변형, 변경 및 수정이 가능함은 이 분야의 통상의 지식을 가진 자에게 있어서 명백한 것이다.Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings. The embodiments of the present invention described below are merely for illustrating the technical idea of the present invention by way of example, it should not be understood that the scope of the present invention is limited thereto. Various modifications, changes and variations are possible in the following examples which will be apparent to those of ordinary skill in the art.
먼저, 도 2a를 참조하면, 반도체 기판(30)에 P-웰(32)과 N-웰(34)을 형성하고, 산화막(36)을 형성한 후 포토레지스트를 도포하지 않고 NMOS 채널 조절을 위한 이온을 블랭크(Blank) 상태로 주입한다.First, referring to FIG. 2A, the P-well 32 and the N-well 34 are formed on the semiconductor substrate 30, the oxide layer 36 is formed, and then the NMOS channel control is performed without applying photoresist. Ions are implanted in a blank state.
이 공정에서는 PMOS의 문턱전압 저절용 이온주입 공정의 포토레지스트 형성을 위한 공정을 생략할 수 있는 효과를 얻을 수 있다. 즉, 포토레지스트를 코팅하고, 노광, 현상 및 포토레지스트 제거공정이 필요치 않게 되어 그에 따른 제조비용의 절감효과를 얻을 수 있는 것이다.In this process, the effect of omitting the process for forming the photoresist of the PMOS threshold voltage reduction ion implantation process can be obtained. In other words, the photoresist is coated, and the exposure, development, and photoresist removal processes are not required, thereby reducing the manufacturing cost.
상기 이온이 주입된 후, 도 2b를 참조하면, 반도체 기판(30) 전면에 포토레지스트를 도포하고, 노광 및 현상하여 형성된 포토레지스트(38)를 P-마스크로 사용하며, PMOS 영역의 포토레지스트를 제거하고 나서 PMOS 채널 조정용 이온주입을 실시하고 포토레지스트(38)를 제거한다. 이때 그 과정을 도시하지는 않았지만 반도체 기판(30) 위에는 게이트 형성을 위한 폴리막(40)이 형성된다.After the ions are implanted, referring to FIG. 2B, a photoresist is formed on the entire surface of the semiconductor substrate 30, the photoresist 38 formed by exposure and development is used as a P-mask, and the photoresist in the PMOS region is used. After removal, ion implantation for PMOS channel adjustment is performed to remove the photoresist 38. Although not shown, the poly film 40 for gate formation is formed on the semiconductor substrate 30.
도 2c를 참조하면, 상기 폴리막(40)이 형성된 후 NMOS/PMOS 접합 형성을 위한 이온주입이 이루어지는 것을 보여준다. 이때에도 도 2a의 예와 같이 포토레지스트를 도포하지 않고 PMOS용 엘디디(LDD ; Lightly Doped Drain) 접합 형성을 위한 이온주입을 P-웰(32) 및 N-웰(34) 영역에 걸쳐서 블랭크로 실시한다. 그에 따라 PMOS 엘디디 접합 형성을 위한 별도의 사진공정이 필요치 않게 되어 그에 대한 비용이 절감되는 효과를 얻을 수 있다.Referring to FIG. 2C, ion implantation for forming an NMOS / PMOS junction is performed after the poly film 40 is formed. Also, as in the example of FIG. 2A, ion implantation for forming a lightly doped drain (LDD) junction for a PMOS is applied as a blank over the P-well 32 and N-well 34 regions without applying photoresist. Conduct. This eliminates the need for a separate photo process for forming PMOS LED junctions, resulting in cost savings.
그리고, 도 2d를 참조하면, 포토레지스트를 도포하여 N-마스크를 사용하고 NMOS 영역의 포토레지스트를 제거하고 나서 NMOS용 이온주입을 실시한다. 그리고, 도포된 포토레지스트(42)를 제거한 후 후속공정을 실시한다.Referring to FIG. 2D, the photoresist is applied, an N-mask is used, the photoresist in the NMOS region is removed, and ion implantation for NMOS is performed. Subsequently, the coated photoresist 42 is removed and then a subsequent step is performed.
이상의 과정을 살펴보면, 종래의 씨모스 소자의 제조기술에서는 0.5㎛ 1폴리(Poly) 3메탈(Metal) 로직 프로세스의 경우 필요로 하는 마스크의 수가 14개이고, 포토레지스트의 수가 17개가 요구된 것에 반해, 본 실시예에서는 포토레지스트를 사용하는 공정이 2개가 필요치 않게 되는 것을 알 수 있다.Looking at the above process, in the conventional CMOS device fabrication technology, the number of masks required in the case of 0.5 μm 1 poly 3 metal logic process is 14, while the number of photoresist 17 is required, In this embodiment, it can be seen that two steps using the photoresist are not required.
상기한 바와 같이 본 발명에 의한 실시예에 의하면, NMOS 채널 조정용 이온주입시 및 PMOS용 P-마스크 이온주입시 모두 블랭크로 실시하기 때문에 별도의 포토레지스트 도포과정이 생략되므로 공정이 단순화되며, 그만큼 제조 비용이 절감되는 이점이 있다.As described above, according to the embodiment of the present invention, since both the NMOS channel adjusting ion implantation and the PMOS P-mask ion implantation are performed with a blank, a separate photoresist coating process is omitted, thereby simplifying the process. The cost is reduced.
따라서, 본 발명에 의하면, 씨모스 소자의 제조시 마스크를 형성하지 않은 상태에서 이온주입이 블랭크로 실시되어 별도의 마스크 형성공정이 생략되며, 그에 따른 공정단순화가 이루어져서 제조비용이 절감되어 원가경쟁력을 확보할 수 있는 효과가 있다.Therefore, according to the present invention, the ion implantation is performed as a blank in the state of not forming a mask when manufacturing the CMOS element, and a separate mask forming process is omitted, thereby simplifying the process, thereby reducing the manufacturing cost and improving cost competitiveness. There is an effect that can be secured.
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