JP2000269357A - Method of producing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce man-hours in a production process by forming the same conductivity wells forming a plurality of MOS transistors on a silicon substrate with impurity of substantially the same concentration, and ion-implanting the reverse conductivity impurity to the impurity in the wafer in gate-through. SOLUTION: A field isolation region film 12 is formed on a silicon substrate 10, a protective through-oxide film is formed thereon for ion-implantation, and photoresists 13 for forming a 1.8 V n-well and a 3.3 V n-well are patterned. The patterned photoresists 13 are used as masks to implant phosphorus three times continuously under a specified condition, and As is then implanted under a specified condition to form an n-well 16 for a 1.8 V-pMOS and a well 17 for a 3.3 V-pMOS. Phosphorus is ion-implanted as impurity for each of wells 16 and 17 through As having the reverse conductivity in gate-through.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device driven by a plurality of power supplies.

[0002]

2. Description of the Related Art Recent semiconductor devices have to be driven by a plurality of power supply voltages in accordance with the demand for multifunctional circuits and miniaturization. For example, 3.3V M
When a 1.8 V MOS transistor capable of high-speed operation is incorporated in a semiconductor chip including an OS transistor, the external power supply uses 3.3 V as it is, and a 1.8 V voltage is generated from the external power supply by a step-down circuit. 1.8V system and 3.3V
The system MOS transistors have different gate lengths, different thicknesses of gate oxide films, and different threshold voltages (V _th ).

[0003] Such 1.8 V and 3.3 V MOs
A conventional method for manufacturing a semiconductor device when S transistors are mixed in one chip is performed as follows.

FIGS. 1 to 11 show 1.8 V-pMOS,
1.8V-nMOS, 3.3V-pMOS, 3.3V-
It is sectional drawing which shows each manufacturing process at the time of manufacturing an nMOS on one chip. Note that the manufactured MOS transistor has an LDD structure.

As shown in FIG. 1, first, a silicon substrate 1
0 on the field isolation region (SiO _TwoFilm 12)
After that, a through oxide film for protection against ion implantation (illustration
Not formed) and a photoresist for forming a 1.8 V n-well is formed.
Patterning the dying (PR) 14 and using it as a mask
And ion-implant a donor impurity to obtain 1.8V-pMOS.
N well 16 is formed.

Next, as shown in FIG. 2, a photoresist 18 for forming an n-well for 3.3 V is patterned, and a donor impurity is ion-implanted using the photoresist 18 as a mask.
An n-well 20 for V-pMOS is formed.

Next, as shown in FIG. 3, a photoresist 22 for forming a 1.8 V p-well is patterned, and using this as a mask, acceptor impurities are ion-implanted.
A p-well 24 for 1.8 V-nMOS is formed.

Next, as shown in FIG. 4, a photoresist 26 for forming a 3.3 V p-well is patterned, and using this as a mask, acceptor impurities are ion-implanted.
A p-well 28 for 3.3V-nMOS is formed.

The M ions produced by the above-described respective ion implantations.
The threshold voltage of the OS transistor is adjusted.

Next, the through oxide film formed in the step of FIG. 1 is removed by etching the entire surface.

Next, as shown in FIG. 5, after removing the photoresist 26, a first gate oxide film (SiO ₂ ) 30 is formed, and then a photoresist 3 for etching an oxide film is formed.
2 is removed to remove the first oxide film 30 in the 1.8 V transistor region.

Next, as shown in FIG. 6, the photoresist 32 is removed, and a second gate oxide film (SiO ₂ ) 34 is formed.
To form As a result, the 3.3 V region is additionally oxidized, and a gate oxide film 36 thicker than the 1.8 V region is formed. Subsequently, polysilicon 38 for a gate is deposited, and a photoresist 40 for forming a gate is patterned.
Using the photoresist 40 as a mask, the polysilicon 38
And oxide films 34 and 36 are patterned to form a gate oxide film and a gate.

FIG. 7 shows a gate oxide film and a gate formed. In FIG. 7, reference numerals 42 and 44 denote 1.8V MOs.
The gate oxide film and gate of the S transistor are shown.
Reference numerals 46 and 48 indicate a gate oxide film and a gate of the 3.3 V MOS transistor.

Next, as shown in FIG. 3, a source / drain (SD) -extension of each transistor is formed. The expression SD-extension means a region having a higher concentration than the LDD but a lower concentration than the source / drain.

First, as shown in FIG. 8, 1.8 V-pM
The photoresist 50 for forming the SD-extension of the OS is patterned, and acceptor impurities are ion-implanted, and the SD-extension of 1.8 V-pMOS is formed.
n52 and 54 are formed. Although not shown, the SD
Ion implantation of an acceptor impurity different from the acceptor impurity used for forming the extension
A pocket region is formed in contact with D-extension. This is to reduce the short channel effect.

Next, as shown in FIG. 9, 1.8 V-nM
The photoresist 56 for forming the SD-extension of the OS is patterned, donor impurities are ion-implanted, and the SD-extension 5 of 1.8 V-nMOS is formed.
8 and 60 are formed, and pocket regions are formed as described above, although not shown.

Next, as shown in FIG.
MOS LDD (Lightly Doped Drain)
The photoresist 62 for forming an n-source) is patterned, and a donor impurity is ion-implanted.
The nMOS LDDs 64 and 66 are formed.

Next, as shown in FIG.
The photoresist 68 for forming the LDD of the MOS is patterned, and an acceptor impurity is ion-implanted.
LDDs 70 and 72 of pMOS are formed.

In the subsequent steps, although not shown, a gate side wall is formed, a source and a drain are formed by ion implantation, the source and the drain are activated by heat treatment, and finally, a gate, a source and a drain electrode are formed. Then, a semiconductor device is completed.

As described above, in the 3.3 V-MOS, VDD is used.
The reason for setting the extension to 1.8 V-MOS is that 3.3 V-MOS applies a high voltage.
A low-concentration LDD is used to suppress the source / drain breakdown, while a low-concentration LDD is applied to the 1.8 V-MOS because a low voltage is applied. Since the operation speed is too low, the so-called high concentration LDD, ie, exte
This is because it is necessary to use the ntion.

[0021]

SUMMARY OF THE INVENTION In the conventional manufacturing method,
As shown in FIGS. 1 to 4, in order to set the threshold voltage of a MOS transistor to a target value, a photoresist must be formed for each transistor to perform ion implantation (FIG. 1). 4, the photoresist is formed four times), and there is a problem that the number of steps is large.

An object of the present invention is to provide a semiconductor device including a MOS transistor driven by a plurality of power supplies.
The purpose is to reduce the number of steps in the manufacturing process.

[0023]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a plurality of MOS transistors having different thicknesses of gate oxide films, the method comprising forming the plurality of MOS transistors on a silicon substrate. Forming a well with substantially the same concentration of impurities; and adjusting the threshold voltage according to the thickness of the gate oxide film by passing an impurity of the opposite conductivity type to that of the well through the gate. And a step of implanting ions.

The impurity concentration in the channel region is reduced by ion implantation through the gate through, so that the threshold voltage can be adjusted. Thereby, the step of providing a photoresist at the time of forming a well can be reduced.

When ion implantation is performed by gate through, a defect may occur in a gate oxide film below the gate. Therefore, after ion implantation, heat treatment is performed,
The generated defect can be recovered.

Although the above has focused on the thickness of the gate oxide film,
The difference in the thickness of the gate oxide film is due to the fact that the MOS transistors are driven by power supplies of different voltages.

According to the present invention, in a method of manufacturing a semiconductor device having a plurality of MOS transistors driven by a plurality of power supplies, a substrate region of the same conductivity type forming the plurality of MOS transistors is formed by using Ion implantation to form an impurity concentration such that the threshold voltage of the MOS transistor driven by the minimum voltage power supply is set; and driving by a power supply having a voltage higher than the minimum voltage. Adjusting the threshold voltage of the MOS transistor by implanting ions of a conductivity type opposite to that of the impurity in the substrate region through a gate through.

[0028]

FIG. 12 to FIG. 26 are sectional views showing steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

In this embodiment, as described with reference to FIGS. 1 to 11, 1.8V-pMOS and 1.8V-nMO
S, 3.3V-pMOS and 3.3V-nMOS will be described. In FIGS. 12 to 26, the same elements as those in FIGS. 1 to 11 are denoted by the same reference numerals.

As shown in FIG. 12, first, a field isolation region (SiO ₂ ) film 12 is formed on a silicon substrate 10, and a through oxide film (not shown) for protecting against ion implantation is formed to a thickness of 15 nm. And 1.8 V and 3.3
The photoresist 13 for forming the n-well for V is patterned, and using this as a mask, phosphorus is used at an acceleration voltage and a dose of 700 keV, 1.5 × 10 ¹³ cm ⁻² ; 480 ke.
V, 2 × 10 ¹² cm ⁻² ; 200 keV, 2 × 10 ¹² cm
Injecting three times continuously under the condition of ^-2 , and finally, in order to adjust the threshold voltage (Vth) for 1.8 V-pMOS,
As is implanted under the conditions of 100 keV and 8 × 10 ¹² cm ⁻² . Thereby, the n-well 16 for 1.8 V-pMOS
And a well 17 for 3.3V-pMOS is formed.
Since the As implantation condition is set so as to set the threshold voltage of 1.8 V-pMOS, the impurity concentration of the well 17 is higher than the desired concentration, and therefore the 3.3 V-pMOS of the 3.3 V-pMOS to be formed is formed. The threshold voltage is higher than the target value.

Next, as shown in FIG. 13, a photoresist 21 for forming p-wells for 1.8V and 3.3V is patterned, and using this as a mask, boron is applied for 300k.
eV, 2 × 10 ¹³ cm ⁻² ; 150 keV, 2 × 10 ¹² c
Injection is performed twice consecutively under the condition of m ^-2 , and finally, boron is adjusted to 3 V to adjust the threshold voltage for 1.8 V-nMOS.
The implantation is performed under the conditions of 0 keV and 7 × 10 ¹² cm ⁻² . As a result, the p-well 24 for 1.8 V-nMOS and 3.p.
A p-well 25 for 3V-nMOS is formed. Well 2
The impurity concentration of No. 8 is higher than the desired concentration, and therefore, the threshold voltage of the 3.3 V-nMOS to be formed is higher than the target value.

In the above-described step of forming the well, the photoresist is formed twice, and the number of steps is half that of the conventional method of FIG. However, since the impurity concentration of the 3.3V-system wells 20 and 28 is not a desired concentration, it is necessary to adjust the impurity concentration by ion implantation in a later step.

Next, the through oxide film formed in the step of FIG. 12 is removed by etching the entire surface.

Next, as shown in FIG. 14, after removing the photoresist 21, the first gate oxide film (SiO ₂ ) 30 is formed to a thickness of 7.5 by wet oxidation or dry oxidation.
Then, the photoresist 32 for etching the oxide film is patterned to remove the first oxide film 30 in the 1.8 V transistor region.

Next, as shown in FIG. 15, the photoresist 32 is peeled off, and a second gate oxide film (SiO ₂ ) having a thickness of 3.8 nm is formed by wet oxidation or dry oxidation.
Form. As a result, in the 1.8 V region, a 3.8 nm oxide film 34 is formed, and in the 3.3 V region, additional oxidation is performed for 7.5 nm, so that an 8 nm thick gate oxide film 36 is formed.

Subsequently, a gate polysilicon 38 is deposited to a thickness of 150 nm, and a gate forming photoresist 40 is formed.
Is patterned. Using the photoresist 40 as a mask, the polysilicon 38 and the oxide films 34 and 36 are patterned to form a gate oxide film and a gate.

FIG. 16 shows the gate oxide film and the gate formed. In FIG.
The figure shows a gate oxide film and a gate (for example, a gate length of 0.18 μm) of the OS transistor.
2 shows a gate oxide film and a gate (for example, a gate length of 0.35 μm) of a 3V MOS transistor.

Next, as shown in FIG.
The photoresist 62 for forming the LDD of the MOS is patterned, and first, phosphorus is implanted into the channel by gate through under conditions of 130 keV and 1.5 × 10 ¹² cm ⁻² for adjusting the threshold voltage (Vth). The desired threshold voltage is obtained by reducing the impurity concentration of the channel region. Subsequently, phosphorus is obliquely implanted at an angle of 20 ° under the conditions of 50 keV and 6 × 10 ¹³ cm ⁻² to form LDDs 64 and 66.

Next, as shown in FIG.
Patterning photoresist 68 for forming LDD of MOS
First, boron for adjusting the threshold voltage (Vth)
50 keV, 3 × 10¹²cm^-2Gate-through under conditions
Implanted into the channel, and the impurity concentration in the channel region
And a desired threshold voltage is obtained. Then, BF _Two
50 keV, 4 × 10¹³cm^-2Inject under the condition of LDD
70 and 72 are formed.

Next, as shown in FIG. 19, after the photoresist 68 is peeled off, side oxidation is performed by wet oxidation or dry oxidation to form an oxide film (SiO ₂ ) 80 having a thickness of 5 mm.
nm. At the time of this side oxidation, LDD ions are diffused, and defects generated in the gate oxide film 46 during the ion implantation shown in FIGS. 17 and 18 are recovered.

Next, as shown in FIG.
Photoresist for forming SD-extension of MOS
Patterning the dist 50, BF_TwoIs 5 keV, 1 ×
10 ¹⁴cm^-21.8 V-pM
Form SD-extensions 52 and 54 of OS
You. Although not shown, As is further set to 70 keV, 2 × 1
0¹³cm^-2Under the conditions of the above, the oblique injection is performed at an angle of 25 °,
Form pocket area in contact with SD-extension
To achieve. This is to reduce short channel effects.
You.

Next, as shown in FIG. 21, 1.8V-n
Photoresist for forming SD-extension of MOS
The strike 56 is patterned, and As is 100 keV, 4 ×
10 ¹⁴cm^-2Ion implantation under the condition of 1.8 V-nMO
S58 and S60 are formed, and although not shown, BF_Two
30 keV, 4 × 10¹³cm^-225 ° angle
Injection at a rotation angle and contact with SD-extension
To form a pocket region.

Next, as shown in FIG. 22, an SiO ₂ film is deposited to a thickness of 100 to 120 nm by the CVD method, and is etched back by anisotropic etching.
Only the gate side wall 84 is left.

Next, as shown in FIG. 24, SiO ₂ film 8
6 is deposited to a thickness of 10 nm by a CVD method. This is to protect the surface against SD ion implantation in the next step.

Next, as shown in FIG. 25, the photoresist 88 for forming the SD for the pMOS is patterned and ion-implanted to perform 1.8V-pMOS and 3.3V-pMOS.
-Form source 90 and drain 92 of pMOS.

Next, as shown in FIG. 26, the photoresist 94 for forming the SD for the nMOS is patterned and ion-implanted to perform 1.8V-nMOS and 3.3V.
Forming a source 96 and a drain 98 of the nMOS;

In the above embodiment, 1.8 V and 3.3 V
PMOS and nMOS driven by two types of power supply V
The method of manufacturing the semiconductor device including the semiconductor device described above has been described. For example, a semiconductor device driven by three or more types of power sources including 2.5 V and 5.0 V is also used. The impurity concentration is reduced by setting the impurity concentration to set the threshold voltage, and in the subsequent process, the impurity concentration is reduced by performing gate-through ion implantation on the channel of the MOS transistor using the power supply of a higher voltage as the target threshold voltage. You can get it.

In the above embodiment, the nMOS and p
Although an example in which MOSs are mixed has been described, it is apparent that the present invention can be applied to a semiconductor device in which a MOS of only one channel type exists.

[Brief description of the drawings]

FIG. 1 shows 1.8V-pMOS, 1.8-nMOS, and 3.V-pMOS.
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3V-pMOS and 3.3V-nMOS on one chip.

FIG. 2 shows 1.8V-pMOS, 1.8-nMOS, and 3.V-pMOS.
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3V-pMOS and 3.3V-nMOS on one chip.

FIG. 3 shows 1.8V-pMOS, 1.8-nMOS, and 3.V-pMOS.
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3V-pMOS and 3.3V-nMOS on one chip.

FIG. 4 shows 1.8V-pMOS, 1.8-nMOS, and 3.V-pMOS.
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3V-pMOS and 3.3V-nMOS on one chip.

FIG. 5 shows 1.8V-pMOS, 1.8-nMOS and 3.V-pMOS.
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3V-pMOS and 3.3V-nMOS on one chip.

FIG. 6 shows 1.8V-pMOS, 1.8-nMOS, and 3.V-pMOS.
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3V-pMOS and 3.3V-nMOS on one chip.

FIG. 7 shows 1.8V-pMOS, 1.8-nMOS, and 3.VMOS.
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3V-pMOS and 3.3V-nMOS on one chip.

FIG. 8 shows 1.8V-pMOS, 1.8-nMOS, and 3.VMOS.
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3V-pMOS and 3.3V-nMOS on one chip.

FIG. 9 shows 1.8V-pMOS, 1.8-nMOS, and 3.VMOS.
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3V-pMOS and 3.3V-nMOS on one chip.

FIG. 10 shows 1.8V-pMOS, 1.8-nMOS,
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3.3V-pMOS and 3.3V-nMOS on one chip.

FIG. 11 shows 1.8V-pMOS, 1.8-nMOS,
It is sectional drawing which shows each manufacturing process of the conventional manufacturing method when manufacturing 3.3V-pMOS and 3.3V-nMOS on one chip.

FIG. 12 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 13 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 14 is a cross-sectional view showing each step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 15 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 16 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 17 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 18 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 19 is a cross-sectional view showing each step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 20 is a cross-sectional view showing each step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 21 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 22 is a cross-sectional view showing each step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 23 is a cross-sectional view showing each step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 24 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 25 is a cross-sectional view showing each step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 26 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 10 silicon substrate 12 field isolation region 13, 21, 32, 38, 40, 50, 56, 62, 6
8,88,94 Photoresist 16 n-well for 1.8V-pMOS 17,20 n-well for 3.3V-pMOS 24 1.8p-well for 1.8V-nMOS 25,28 p-well for 3.3V-nMOS Well 30 First gate oxide film 34 Second gate oxide film 36 Gate oxide film 38 Polysilicon 52, 54, 58, 60, 64, 66, 70, 72 S
D-extension 64, 66, 70, 72 LDD 80, 82 SiO ₂ film 84 Side wall

Claims (10)

[Claims] A plurality of MOS transistors each having a different thickness of a gate oxide film;
In the method for manufacturing a semiconductor device having a transistor, a step of forming the same conductivity type substrate region in which the plurality of MOS transistors are formed with substantially the same concentration of impurities; Performing a gate-through ion implantation of an impurity of a conductivity type opposite to that of the substrate region to adjust a threshold voltage. 2. A plurality of MOS transistors each having a different gate oxide film thickness.
Forming a plurality of MOS transistors of the same conductivity type in a silicon substrate with substantially the same concentration of impurities in a silicon substrate; Implanting an impurity of a conductivity type opposite to that of the well with a gate through in order to adjust the threshold voltage. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing a heat treatment for recovering a defect generated in the gate oxide film by the ion implantation by the gate through. Method. 4. The semiconductor device according to claim 1, wherein said plurality of MOS transistors include only one conductivity type MOS transistors or one conductivity type and opposite conductivity type MOS transistors. Production method. 5. The semiconductor device according to claim 1, wherein the MOS transistor is an LDD-type MOS transistor.
5. The method according to claim 4, wherein the method is an OS transistor. 6. A method of manufacturing a semiconductor device having a plurality of MOS transistors driven by a plurality of power supplies, wherein a substrate region of the same conductivity type forming the plurality of MOS transistors is formed by a minimum of the plurality of power supplies. Ion implantation so as to have an impurity concentration such that a threshold voltage of a MOS transistor driven by a voltage power supply is set; and MO driven by a power supply having a voltage higher than the minimum voltage.
Performing a gate-through ion implantation of an impurity of a conductivity type opposite to that of the impurity in the substrate region to adjust a threshold voltage of the S transistor. 7. A method for manufacturing a semiconductor device having a plurality of MOS transistors driven by a plurality of power supplies, wherein a well of the same conductivity type forming the plurality of MOS transistors is formed on a silicon substrate. Ion implantation so as to have an impurity concentration such that the threshold voltage of a MOS transistor driven by the minimum voltage power supply is set; and driving by a power supply having a voltage higher than the minimum voltage. MO
Performing a gate-through ion implantation of an impurity having a conductivity type opposite to that of the well in order to adjust a threshold voltage of the S-transistor. 8. The method according to claim 6, further comprising the step of performing a heat treatment to recover a defect generated in the gate oxide film by the ion implantation by the gate through.
Or a method for manufacturing a semiconductor device according to item 7. 9. The semiconductor device according to claim 6, wherein said plurality of MOS transistors include only one conductivity type MOS transistors or one conductivity type and opposite conductivity type MOS transistors. Production method. 10. A method according to claim 9, wherein said MOS transistor is an LDD type MOS transistor.