476110 5 83 8twf. doc/0 06 五、發明說明（/ ) (請先閱讀背面之注意事項再填寫本頁) 本發明是有關於一種積體電路(1C)的製程，且特別是 有關於一種防止淺溝渠隔離(Shallow Trench Isolation ; STI) 降低金氧半電晶體啓始電位(threshold voltage ; VT)之方法。 積體電路一般包括週邊電路(periphery circuit)與核心 電路（core circuit)，週邊電路負責積體電路之輸入/輸出 (I/O)，而核心電路則負責執行此積體電路之主要功能。若 將二者整合在同一片晶片上，因爲週邊電路一般要承受較 大之操作電壓，所以在製作週邊電路之週邊電路區的閘極 氧化層時，一般需比製作在核心電路之元件區的閘極氧化 層要厚。例如，若週邊電路區的閘極施加電壓爲3.3伏特 時，其閘極氧化層厚度約需爲80埃，且其啓始電位爲0.8 伏特。若核心電路區的閘極施加電壓爲2.5伏特時，則閘 極氧化層厚度約需爲55埃，且其啓始電位爲0.55伏特。 又因爲核心電路區內的積體電路較爲密集，並且具有較小 的閘極線寬以及通道寬度，所以會有較嚴重的啓始電位下 降現象。 經濟部智慧財產局員工消費合作社印製 請同時參照第1A圖與第1B圖，第1A圖爲第1B圖 之俯視圖，而第1B圖爲第1A圖之Ι-Γ切線的剖面圖。在 矽基底100上，形成有淺溝渠隔離102，此淺溝渠隔離102 係圍繞在主動區108的周圍。多晶矽閘極104形成在矽基 底100與淺溝渠隔離102的上方，施加閘極電壓會使多晶 矽閘極104到矽基底100之間產生電場，尤其矽基底100 在多晶矽閘極104下方並且靠近淺溝渠隔離102的邊緣106 處，因爲成一轉角之故，在此處之電場會比矽基底100在 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） ' 476110 5 83 8twf . doc /006 jsj 五、發明說明（2) 多晶矽閘極104下方的其他位置之電場還高。因此，當電 晶體處於關（off)的狀態時，矽基底1〇〇在靠近淺溝渠隔離 102的邊緣106會感應出較高的漏電流(leakage current)， 而當電晶體處於開的狀態時則其啓始電位會較低。 在閘極線寬（gate linewidth)110爲0.25微米以下的金 氧半電晶體（Metal Oxide Semiconductor，M0S)中，當通道 寬度(channel width)112減小時，主動區108之邊緣106部 分所佔通道寬度112的比例會增加’使得邊緣106對金氧 半電晶體的啓始電位影響更加顯著，造成金氧半電晶體的 啓始電位降低更多。 請參照第2圖，在閘極線寬爲〇·18微米之P型金氧 半電晶體中，當通道寬度112爲5微米時，啓始電位約爲-〇·35至-0.31伏特，當通道寬度112縮小到1微米時，啓始 電位下降到-0.33至-0.28伏特，當通道寬度112再縮小到0.3 至〇·2微米時，啓始電位更下降到-0.32至-0.21伏特。 經濟部智慧財產局員工消費合作社印製 請參照第3圖，在閘極線寬爲0.18微米之Ν型金氧 半場效應電晶體中，當通道寬度112爲5微米時，啓始電 位約爲0.41至0.34伏特，當通道寬度112縮小到1微米時， 啓始電位下降到0.40至0.31伏特，當通道寬度112再縮 小到0.3至0.2微米時，啓始電位更下降到0.37至0.22伏 特。 如第2圖以及第3圖所示，就整體而言，啓始電位均 隨著通道寬度112的縮小而下降，然而，理想的情況卻是 希望啓始電位不受通道寬度112的縮小而下降，而能與例 4 本紙張尺度適用中國國家標準（CNS)A〗規格（210 X 297公釐） 476110 5838twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（>) _ 如5微米通道寬度之金氧半電晶體擁有相同的啓始電位。 在習知技藝中通常採用圓形化氧化法（Rounding Oxidation)、間隙壁保護法（Spacer Protection)以及氮化物後 退法(Nitride Pull Back)來修飾矽基底靠近淺溝渠隔離的邊 緣，使其暴露出來的部分減至最小’以降低此處的電場。 然而，在製造上卻很複雜以及難以控制。 本發明提供一種防止淺溝渠隔離降低金氧半電晶體 啓始電位之方法，其係在基底中形成有複數個淺溝渠隔離 以隔開複數個第一主動區與第二主動區。其中第一主動區 位於核心電路區內，第二主動區位於週邊電路區內。然後 對第一主動區與第二主動區進行第一離子植入步驟，以分 別於第一與第二主動區之基底中形成複數個井摻雑區。接 下來，對第二主動區與第一主動區之邊緣進行第二離子植 入步驟，以分別於第二主動區形成第二通道離子摻雜區與 適度增加第一主動區邊緣之離子濃度。最後，對第一主動 區進行第三離子植入步驟，以於第一主動區形成第一通道 離子摻雜區。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明 如下： 圖式之簡單說明： 第1A圖係繪示淺溝渠隔離的俯視圖； 第1B圖係繪示第ία圖之Ι-Γ切線的剖面圖； 第2圖係繪示閘極線寬爲0.18微米之p型金氧半場 5 本紙張尺度_中關家標準（&)Λ4規格⑵Qx 297公P " -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 476110 5838twf.doc/006 A7 B7 五、發明說明（午） 效應電晶體，其啓始電位對通道寬度的變化圖； 第3圖係繪示閘極線寬爲0.18微米之N型金氧半場 效應電晶體，其啓始電位對通道寬度的變化圖； 第4A圖係繪示本發明之一種防止淺溝渠隔離降低金 氧半電晶體啓始電位之方法，在進行第一離子植入步驟時 的俯視圖； 第4B圖左/右係繪示第4A圖之ΙΙ-ΙΓ切線/111-111，切線 的剖面圖； 第5A圖係繪示本發明之一種防止淺溝渠隔離降低金 氧半電晶體啓始電位之方法，在進行第二離子植入步驟時 的俯視圖； 第5B圖左/右係繪示第5A圖之ΙΙ-ΙΓ切線/ΙΙΙ-ΙΙΓ切線 的剖面圖；' 第5C圖係繪示第5A圖之IV-IV'切線的放大剖面圖， 以說明第二光阻層的陰影效應； 第6A圖係繪示本發明之一種防止淺溝渠隔離降低金 氧半電晶體啓始電位之方法，在進行第三離子植入步驟時 的俯視圖； 第6B圖左/右係繪示第6A圖之ΙΙ-ΙΓ切線/ΠΙ-ΙΙΓ切線 的剖面圖； 第6C圖係繪示第6A圖之ΙΙΙ-ΙΙΓ切線的放大剖面圖； 第7A圖係繪示本發明之一種防止淺溝渠隔離降低金 氧半電晶體啓始電位之方法，在形成閘極時的俯視圖；以 及 6 (請先閱讀背面之注意事項再填寫本頁) _ · ·ϋ ϋ I n I n ϋ I ·1 ϋ n ϋ an ϋ I · 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（以〇 x 公t ) 經濟部智慧財產局員工消費合作社印製 476110 5838twf.doc/006 A? _B7 五、發明說明（f ) 第7B圖左/右係繪示第7A圖之ΙΙ-ΙΓ切線/ΙΙΙ-ΙΙΓ切線 的剖面圖。 標號說明： 100、200 :矽基底 102、202 :淺溝渠隔離 104 :多晶矽閘極 106、224 :邊緣 108、204、206 :主動區 110 :閘極線寬（gate linewidth) 112 :通道寬度 208、216、232 :光阻層 210、212、218、220、234 :窗口 214 :第一型離子 215 :第一型井摻雜區 222 :第一型離子 226 :寬度 228 :厚度 230 :植入角 236 :第一型離子 238 :閘極 250、255a :通道離子植入區 255 :淺層摻雜區 實施例 請同時參照第4A圖與第4B圖，第4A圖爲第4B圖 本紙張尺度適用中國國家標準（CNS)/\4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---- Φ 476110 A7 5 83 8twf. doc/006 ___B7__________ 五 發明說明（g) 之俯視圖，而第4B圖左/右爲第4A圖之ΙΙ-ΙΓ切線/ ΙΠ-ΙΙΓ 切線的剖面圖。在矽基底200中形成有淺溝渠隔離202將 主動區204、206隔離開來，主動區204是位於週邊電路區 上，主動區206是位於核心電路區上。 接著，在砂基底200上形成圖案化的光阻層208 ’其 在週邊電路區內的窗口 210暴露出主動區204，在核心電 路區內的窗口 212則暴露出主動區206。然後以此光阻層 208爲罩幕，對所暴露出之主動區進行第一離子植入步驟， 植入第一型離子214於暴露出之主動區204、206中，以形 成第一型井(Well)摻雜區215。 經濟部智慧財產局員工消費合作社印製 請同時參照第5A圖與第5B圖，第5A圖爲第5B圖 之俯視圖，而第5B圖左/右爲第5A圖之ΙΙ-ΙΓ切線/ΙΙΙ-ΙΙΓ 切線的剖面圖。去除光阻層208之後，在矽基底200上形 成圖案化光阻層216，其在週邊電路區內的窗口 218暴露 出主動區204，在核心電路區內的窗口 220則暴露出主動 區206之邊緣，此邊緣係爲稍後將形成之閘極(此處以長條 狀虛線框標示)所通過之處。然後以此光阻層216爲罩幕， 進行第二離子植入步驟，植入第一型離子222於暴露出之 主動區204的淺層區域與主動區206之邊緣的淺層區域， 形成通道離子植入區250與主動區206之邊緣的淺層摻雜 區255。此第二離子植入步驟具有一傾斜角230,其原因 將於稍後說明。 此第二離子植入步驟除了調整週邊電路區內金氧半 電晶體之啓始電位之外，也一倂增加核心電路區內在淺溝 8 本紙張尺度適用中國國家標準（CNS)/y規格（21〇χ 297公釐） 476110 A7 5838twf.doc/006 五、發明說明（1 ) 渠隔離20¾邊緣之部分主動區206的第一型離子的植入劑 量。如此，可以提升位在核心電路區內的金氧半電晶體之 啓始電位，解決習知之核心電路區內的金氧半電晶體因其 積集度（Integration)較高，較易受淺溝渠隔離影響而導致啓 始電位下降的問題。於是可在不增加額外步驟之下，達成 提升核心電路區內金氧半電晶體之啓始電壓，使其穩定之 目的。 如第5C圖所示，第5C圖爲第5A圖之IV-IV’切線的 放大剖面圖。在進行第二離子植入步驟時，因爲在主動區 204的通道離子植入區250之離子植入劑量，其與主動區 206之邊緣的淺層摻雜區255之離子植入劑量並不一樣。 在必須兼顧主動區204之通道離子植入區250與主動區206 之邊緣的淺層摻雜區255的不同離子植入劑量需求下，應 用陰影效應（shadowing effect)以調整離子植入於暴露出之 主動區206的邊緣224之劑量。亦即由光阻層216在窗口 220之寬度226、窗口 220與主動區206之邊緣224之間的 相對位置、光阻層216的厚度228，以及第一型離子222 之植入角230等四個因素來調整第一型離子222植入於主 動區206之邊緣224處的離子劑量，以適度地提升核心電 路區內金氧半電晶體的啓始電壓。在上述各參數中，光阻 層216的厚度228介於〇.5μηι至2μιη之間，且第一型離子 222之植入角230介於0°至45°之間。 請同時參照第6Α圖與第6Β圖，第6Α圖爲第6Β圖 之俯視圖，而第6Β圖左/右爲第6Α圖之ΙΜΓ切線/ΙΙΙ-ΙΙΓ -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制衣 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476110 5838twf.doc/006 A7 B7 五、發明說明（？） 切線的剖面圖。去除光阻層216之後，在基底上形成圖案 化光阻層232，其在核心電路區內的窗口 234暴露出主動 區206。然後以此光阻層232爲罩幕’進行第三離子植入 步驟，植入第一型離子236於主動區206之淺層區域，形 成通道離子植入區255a，以調整核心電路區內金氧半電晶 體之啓始電位。之後，去除光阻層232。 如第6C圖所示，第6C圖爲第6A圖之ΙΙΙ-ΙΙΓ切線的 放大剖面圖，淺層摻雑區255與通道離子植入區255a在主 動區206的邊緣重疊，在主動區206的邊緣224具有比通 道離子植入區255a還要高的離子摻雜濃度。因此，可以 提昇核心電路區內金氧半電晶體的啓始電位，以減小啓始 電位因淺溝渠隔離之影響而下降的程度。 除了上述之步驟順序之外，亦可先進行第6A至6C 圖所述之步驟，再進行第5A至5C圖所述之步驟，仍然可 以得到相同的結果。 對週邊電路區與核心電路區中的CMOS而言，其 NM0S主動區與PM0S主動區中必須分別植入P型與η型 離子。如果上述主動區204、206爲NMOS(PMOS)主動區， 且爲第一型離子爲p型(η型)離子，則在PMOS(NMOS)主 動區中植入η型(p型)離子時，亦需重複進行第4A圖至第 6C圖所述之步驟，只要將其中第一至第三離子植入步驟 所用之Ρ型(η型）離子改爲η型(ρ型)離子即可。因此本發 明總共進行六次的離子植入步驟，與習知相比較’並不需 要增加額外的離子植入步驟。 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------^^^1 經濟部智慧財產局員工消費合作社印制衣 476110 經濟部智慧財產局員工消費合作社印製 5838twf.doc/006 五、發明說明（Y ) 請同時參照第7A圖與第7B圖，第7A圖爲第7B圖 之俯視圖，而第7B圖左/右爲第7A圖之ΙΙ-ΙΓ切線/ΙΙΙ-ΙΙΓ 切線的剖面圖。在主動區204與主動區206上形成複數個 閘極238。後續形成源極/汲極等（圖上未示出）之完成金氧 半電晶體的製造步驟爲熟悉此技藝者所熟知，不再贅述 之。 上述之主動區206之通道離子植入劑量（即在第三離 子植入步驟時)若約爲3x 1013原子/平方公分左右時，主動 區206邊緣所需調整之離子濃度(即在第二離子植入步驟時) 可約爲lx 1013原子/平方公分左右。 如上所述，本發明係提出一種防止淺溝渠隔離降低 金氧半電晶體啓始電位之方法。其中使用一圖案化的光阻 層，其窗口同時曝露出週邊電路區內之主動區，以及核心 電路區內之主動區邊緣。在進行週邊電路區之通道離子植 入步驟時（即上述之第二離子植入步驟），同時對位於核心 電路區內之主動區邊緣應用陰影效應與以某種植入角來同 時進行離子植入。再加上位於核心電路區內之主動區之另 一次通道離子植入步驟（即上述之第三離子植入步驟），如 此可以增加位於核心電路區內之主動區邊緣的離子植入劑 量，以提升其啓始電位。 因此應用本發明，具有不需要再加任何額外的離子 植入步驟或其他的製程步驟，即可在調整週邊電路區內金 氧半電晶體的啓始電位之時，同時也調整核心電路區內金 氧半電晶體的啓始電位之優點。 -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476110 5838twf.doc/006 A7 _B7_ 五、發明說明（川） 綜上所述，雖然本發明已以較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂--------- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）476110 5 83 8twf. Doc / 0 06 V. Description of the invention (/) (Please read the notes on the back before filling this page) The present invention relates to a process of integrated circuit (1C), and in particular to a Prevent Shallow Trench Isolation (STI) to reduce the threshold voltage (VT) of the metal-oxide semiconductor transistor. The integrated circuit generally includes a peripheral circuit and a core circuit. The peripheral circuit is responsible for the input / output (I / O) of the integrated circuit, and the core circuit is responsible for performing the main functions of the integrated circuit. If the two are integrated on the same chip, because the peripheral circuit generally needs to withstand a larger operating voltage, the gate oxide layer in the peripheral circuit area of the peripheral circuit generally needs to be fabricated more than the component oxide area in the core circuit area. The gate oxide must be thick. For example, if the applied voltage of the gate of the peripheral circuit area is 3.3 volts, the thickness of the gate oxide layer needs to be about 80 angstroms, and its initial potential is 0.8 volts. If the applied voltage of the gate of the core circuit area is 2.5 volts, the thickness of the gate oxide layer needs to be about 55 angstroms, and its initial potential is 0.55 volts. Also, because the integrated circuits in the core circuit area are denser and have smaller gate line widths and channel widths, there will be a more serious drop in initial potential. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics Please refer to Figures 1A and 1B at the same time. Figure 1A is a top view of Figure 1B, and Figure 1B is a cross-sectional view taken along the line Ⅰ-Γ of Figure 1A. On the silicon substrate 100, a shallow trench isolation 102 is formed, and the shallow trench isolation 102 surrounds the active region 108. The polycrystalline silicon gate 104 is formed above the silicon substrate 100 and the shallow trench isolation 102. The application of a gate voltage will generate an electric field between the polycrystalline silicon gate 104 and the silicon substrate 100, especially the silicon substrate 100 is under the polycrystalline silicon gate 104 and close to the shallow trench. At the edge 106 of the isolation 102, because of a corner, the electric field here will be 3 paper sizes than the silicon substrate 100 applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) '476110 5 83 8twf. doc / 006 jsj V. Description of the invention (2) The electric field at other positions below the polycrystalline silicon gate 104 is still high. Therefore, when the transistor is in the off state, the silicon substrate 100 will induce a higher leakage current near the edge 106 of the shallow trench isolation 102, and when the transistor is in the on state Then its starting potential will be lower. In a metal oxide semiconductor (MOS) with a gate line width 110 of 0.25 micrometers or less, when the channel width 112 decreases, the edge 106 of the active region 108 occupies the channel The proportion of the width 112 will increase ', so that the edge 106 has a more significant effect on the initial potential of the metal-oxide semiconductor, causing the initial potential of the metal-oxide semiconductor to decrease more. Please refer to Fig. 2. In a P-type metal-oxide semiconductor transistor having a gate line width of 0.18 microns, when the channel width 112 is 5 microns, the initial potential is approximately -0.35 to -0.31 volts. When the channel width 112 is reduced to 1 micron, the initial potential decreases to -0.33 to -0.28 volts. When the channel width 112 is further reduced to 0.3 to 0.2 micron, the initial potential decreases to -0.32 to -0.21 volts. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 3. In an N-type metal-oxygen half-field effect transistor with a gate line width of 0.18 microns, when the channel width 112 is 5 microns, the initial potential is about 0.41. When the channel width 112 is reduced to 1 micron to 0.34 volts, the initial potential decreases to 0.40 to 0.31 volts, and when the channel width 112 is further reduced to 0.3 to 0.2 micrometers, the initial potential decreases to 0.37 to 0.22 volts. As shown in Fig. 2 and Fig. 3, as a whole, the starting potential decreases as the channel width 112 decreases. However, ideally, it is desired that the starting potential does not decrease without decreasing the channel width 112. The paper size can be used in accordance with Example 4. This paper size is in accordance with Chinese National Standard (CNS) A. Specifications (210 X 297 mm) 476110 5838twf.doc / 006 A7 B7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs ;) _ For example, a gold-oxygen semitransistor with a channel width of 5 microns has the same starting potential. In conventional techniques, Rounding Oxidation, Spacer Protection, and Nitride Pull Back are used to modify the edge of the silicon substrate near the shallow trench isolation to expose it. To minimize the 'to reduce the electric field here. However, manufacturing is complex and difficult to control. The invention provides a method for preventing shallow trench isolation to reduce the initial potential of a metal-oxide-semiconductor. A method is to form a plurality of shallow trench isolations in a substrate to separate a plurality of first active regions from a second active region. The first active area is located in the core circuit area, and the second active area is located in the peripheral circuit area. Then, a first ion implantation step is performed on the first active region and the second active region to form a plurality of well-doped erbium-doped regions in the substrates of the first and second active regions, respectively. Next, a second ion implantation step is performed on the edges of the second active region and the first active region to form a second channel ion-doped region in the second active region and increase the ion concentration at the edges of the first active region appropriately. Finally, a third ion implantation step is performed on the first active region to form a first channel ion-doped region in the first active region. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies the preferred embodiments and the accompanying drawings in detail, as follows: Brief description of the drawings: FIG. 1A is a drawing Top view of shallow trench isolation; Figure 1B is a cross-sectional view of the Ια-Γ tangent line in Figure ία; Figure 2 is a p-type metallo-oxygen half field with a gate line width of 0.18 microns 5 paper dimensions_Zhongguan &Amp; Standard Λ4 Specification ⑵Qx 297 Male P " ----------- Installation -------- Order --------- (Please read the first Note: Please fill in this page again) 476110 5838twf.doc / 006 A7 B7 V. Description of the invention (noon) Effect transistor, its initial potential versus the channel width; Figure 3 shows the gate line width is 0.18 microns Figure 4A shows the change of the initial potential of the N-type metal-oxide-semiconductor field-effect transistor with respect to the channel width. FIG. 4A illustrates a method for preventing shallow trench isolation and reducing the initial potential of a metal-oxide-semiconductor transistor in the present invention. A top view of an ion implantation step; FIG. 4B left / right shows a tangent line 111-111 of FIG. 4A, a cross-sectional view of tangent line 111-111; FIG. 5A A method for preventing shallow trench isolation and reducing the initial potential of a metal-oxide-semiconductor crystal according to the present invention is shown in a top view during the second ion implantation step; FIG. 5B left / right shows FIG. 5A in FIG. Tangent line / ΙΙΙ-ΙΙΓ tangent cross-section; 'Figure 5C shows an enlarged cross-section of the tangent of Figure 5A IV-IV' to illustrate the shadow effect of the second photoresist layer; Figure 6A shows the present invention A method for preventing shallow trench isolation from lowering the initial potential of the metal-oxide semiconductor transistor, a top view of the third ion implantation step; FIG. 6B left / right shows the tangent line III-III in FIG. 6A / Π- A cross-sectional view of the ΙΓΓ tangent line; FIG. 6C is an enlarged cross-sectional view of the tangent line of FIG. , Top view when the gate is formed; and 6 (Please read the precautions on the back before filling out this page) _ · · ϋ ϋ I n I n ϋ I · 1 ϋ n ϋ an ϋ I The paper size printed by the consumer cooperative is applicable to the Chinese National Standard (CNS) A 4 Specifications (in 0x t) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476110 5838twf.doc / 006 A? _B7 V. Description of the invention (f) Figure 7B left / right shows Figure 7A Figure ΙΙ- A cross-sectional view of the ΙΓ tangent line / ΙΙΙ-ΙΙΓ tangent line. Explanation of symbols: 100, 200: silicon substrate 102, 202: shallow trench isolation 104: polysilicon gate 106, 224: edge 108, 204, 206: active area 110: gate linewidth 112: channel width 208, 216, 232: photoresist layer 210, 212, 218, 220, 234: window 214: first type ion 215: first type well doped region 222: first type ion 226: width 228: thickness 230: implantation angle 236: the first type ion 238: the gate electrode 250, 255a: the channel ion implantation region 255: the shallow doped region embodiment Please refer to FIG. 4A and FIG. 4B at the same time, and FIG. 4A is FIG. 4B China National Standard (CNS) / \ 4 specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page) Installation -------- Order ---- Φ 476110 A7 5 83 8twf doc / 006 ___B7__________ The top view of the fifth invention description (g), and the left / right of FIG. 4B is a cross-sectional view of the tangent line ΙΙ-ΙΓ / ΙΠ-ΙΙΓ of Figure 4A. A shallow trench isolation 202 is formed in the silicon substrate 200 to isolate the active regions 204 and 206. The active region 204 is located on the peripheral circuit region and the active region 206 is located on the core circuit region. Next, a patterned photoresist layer 208 'is formed on the sand substrate 200. The window 210 in the peripheral circuit region exposes the active region 204, and the window 212 in the core circuit region exposes the active region 206. Then, using the photoresist layer 208 as a mask, a first ion implantation step is performed on the exposed active area, and a first type ion 214 is implanted into the exposed active areas 204 and 206 to form a first type well. (Well) Doped region 215. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figures 5A and 5B. Figure 5A is a top view of Figure 5B, and Figure 5B is the left / right of Figure 5A. A cross-sectional view of the tangent line. After the photoresist layer 208 is removed, a patterned photoresist layer 216 is formed on the silicon substrate 200. The window 218 in the peripheral circuit area exposes the active area 204, and the window 220 in the core circuit area exposes the active area 206. The edge is where the gate (here indicated by a long dashed box) passes through the gate that will be formed later. Then, using the photoresist layer 216 as a mask, a second ion implantation step is performed, and the first type ions 222 are implanted into the shallow area of the exposed active area 204 and the shallow area of the edge of the active area 206 to form a channel. A shallow doped region 255 at the edges of the ion implantation region 250 and the active region 206. This second ion implantation step has a tilt angle 230, and the reason will be described later. In addition to adjusting the initial potential of the metal-oxide-semiconductor in the peripheral circuit area, this second ion implantation step also increases the shallow groove in the core circuit area. The paper size is applicable to Chinese National Standards (CNS) / y specifications ( 21〇χ 297 mm) 476110 A7 5838twf.doc / 006 V. Description of the invention (1) The implantation dose of the first type ion in the active region 206 of the part of the channel isolation 20¾ edge. In this way, the initial potential of the metal-oxide-semiconductor transistor located in the core circuit region can be increased, and the conventional metal-oxide-semiconductor crystal region in the core circuit region is known to be more susceptible to shallow trenches due to its higher integration degree. Isolation effects that cause the initial potential to drop. Therefore, the purpose of increasing the initial voltage of the metal-oxide-semiconductor transistor in the core circuit region to stabilize it can be achieved without adding additional steps. As shown in Fig. 5C, Fig. 5C is an enlarged sectional view taken along the line IV-IV 'of Fig. 5A. During the second ion implantation step, because the ion implantation dose in the channel ion implantation region 250 in the active region 204 is different from the ion implantation dose in the shallow doped region 255 at the edge of the active region 206 . Under the different ion implantation dose requirements of the channel ion implantation region 250 of the active region 204 and the shallow doped region 255 at the edge of the active region 206, a shadowing effect is applied to adjust the ion implantation to the exposed region. The dose of the edge 224 of the active area 206. That is, the relative position of the photoresist layer 216 between the width 226 of the window 220, the window 220 and the edge 224 of the active region 206, the thickness 228 of the photoresist layer 216, and the implantation angle 230 of the first type ion 222. These factors adjust the ion dose of the first type ions 222 implanted at the edge 224 of the active region 206 to moderately increase the starting voltage of the metal-oxide semiconductor transistor in the core circuit region. In the above parameters, the thickness 228 of the photoresist layer 216 is between 0.5 μm and 2 μm, and the implantation angle 230 of the first type ion 222 is between 0 ° and 45 °. Please refer to Figure 6A and Figure 6B at the same time, Figure 6A is a top view of Figure 6B, and Figure 6B is the left / right is the ΙΓΓ tangent of Figure 6A / ΙΙΙ-ΙΙΓ ----------- Packing -------- Order --------- (Please read the notes on the back before filling out this page) The printed paper size of the garments printed by the employee consumer cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies Chinese national standards (CNS) A4 specification (210 X 297 mm) 476110 5838twf.doc / 006 A7 B7 V. Description of the invention (?) Sectional view of tangent line. After the photoresist layer 216 is removed, a patterned photoresist layer 232 is formed on the substrate, and the window 234 in the core circuit region exposes the active region 206. Then use the photoresist layer 232 as a mask to perform the third ion implantation step, implant the first type ions 236 into the shallow area of the active area 206, and form a channel ion implantation area 255a to adjust the gold in the core circuit area. The initial potential of an oxygen semitransistor. After that, the photoresist layer 232 is removed. As shown in FIG. 6C, FIG. 6C is an enlarged cross-sectional view of the III-III line of FIG. 6A. The shallow erbium-doped region 255 and the channel ion implantation region 255a overlap at the edge of the active region 206, The edge 224 has a higher ion doping concentration than the channel ion implantation region 255a. Therefore, the initial potential of the metal-oxide semiconductor transistor in the core circuit region can be increased to reduce the extent to which the initial potential drops due to the influence of shallow trench isolation. In addition to the sequence of steps described above, the steps described in Figures 6A to 6C can be performed first, and then the steps described in Figures 5A to 5C can be used to obtain the same results. For the CMOS in the peripheral circuit area and the core circuit area, P-type and n-type ions must be implanted in the NM0S active area and PM0S active area, respectively. If the active regions 204 and 206 are NMOS (PMOS) active regions and the first type ions are p-type (n-type) ions, when n-type (p-type) ions are implanted in the PMOS (NMOS) active region, The steps described in FIGS. 4A to 6C also need to be repeated, as long as the P-type (η-type) ions used in the first to third ion implantation steps are changed to η-type (ρ-type) ions. Therefore, a total of six ion implantation steps are performed in the present invention, and no additional ion implantation step is required in comparison with the conventional method. 10 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page). -------- Order ------- -^^^ 1 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476110 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5838twf.doc / 006 V. Description of the Invention (Y) Please refer to Figures 7A and 7B at the same time FIG. 7A is a top view of FIG. 7B, and left / right of FIG. 7B is a cross-sectional view of the tangent line II-IΓ / tangent line III-IΓ of FIG. 7A. A plurality of gates 238 are formed on the active region 204 and the active region 206. The manufacturing steps of the completed gold-oxygen semi-transistor, which subsequently forms a source / drain, etc. (not shown in the figure), are well known to those skilled in the art and will not be described in detail. If the ion implantation dose of the channel in the active region 206 (that is, in the third ion implantation step) is about 3 × 1013 atoms / cm 2, the ion concentration at the edge of the active region 206 needs to be adjusted (that is, in the second ion The implantation step) may be about lx 1013 atoms / cm2. As described above, the present invention proposes a method for preventing shallow trench isolation from reducing the initial potential of a metal-oxide semiconductor transistor. A patterned photoresist layer is used, and its window simultaneously exposes the active area in the peripheral circuit area and the edge of the active area in the core circuit area. When performing the channel ion implantation step in the peripheral circuit area (ie the second ion implantation step described above), simultaneously apply the shadow effect to the edge of the active area located in the core circuit area and perform ion implantation at a certain implantation angle at the same time Into. In addition, another channel ion implantation step (ie, the third ion implantation step described above) in the active region in the core circuit region can increase the ion implantation dose at the edge of the active region in the core circuit region. Raise its starting potential. Therefore, the application of the present invention can adjust the initial potential of the metal-oxide semiconductor transistor in the peripheral circuit area without adjusting any additional ion implantation steps or other process steps, while also adjusting the core circuit area. Advantages of the initial potential of the metal-oxide semiconductor. ----------- Installation -------- Order --------- (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS) A4 specification (210 X 297 mm) 476110 5838twf.doc / 006 A7 _B7_ V. Description of the invention (Sichuan) In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit The present invention, anyone skilled in the art can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application. (Please read the precautions on the back before filling out this page) Packing -------- Order --------- Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs CNS) A4 size (210 X 297 mm)