經濟部中央標準局員工消費合作社印製 A7 ____._B7_ 五、發明説明（） 發明領Μ : 本發明係與一種電晶體有關，特別是有關於一種具有 自行對準石夕化金屬接觸（self-aligned silixided contact)及延 伸源及極接面（extended source/drain junction)的極短通道 (ultra-short channel)金氧半場效電晶體（metal oxide semiconductor Held effect transistor; MOSFET)形成之方 法。 發明背景： 自從第一個積體電路於西元I960年首先發明以來，半 導體製程中單一晶片上的元件數目，即以爆炸性的速度快 速成長’隨著現階段的半導體製程技術已邁入超大型積體 電路（ultra larg? scale integration; ULSI)、甚至更高密度的 時代’單一晶片上的元件數目也由以往的數千個元件，增 加至數百萬個元件’甚至可達到單一晶片上製作數千萬個 或是更多個元件的密度。 單一晶片上元件數目的大幅增加，形成對半導體製程 技術的一大挑戰，每一個半導體元件皆必須在不影響其功 能的前提下’進一步縮減其尺寸或占用的面積，而在更高 的積集度（packing density)之下，整體元件或電路之功能仍 須維持不變、甚至必須具有更好的可靠度、工作壽命 '並 同時加入低功率消耗及低發熱率的特性。因此半導體製程 本紙張尺度適用中國國家標準（CNS ) A4规格（21〇x^^J7 (請先閱讀背面之注意事項再填寫本頁) .裝. 訂 U線卜 五、發明説明（） A7 B7 經濟部中央標準局負工消費合作社印製 中的五大製程技術，也就是包含微影、蝕刻、沈積、離子 佈植、及熱製程的五大製程技術，必須同時的研究與發展， 以達成下一代積體電路的發展目標。 s 在一般的積體電路中，最常被應用的元件之丄即是具 有控制特性的電晶體，尤其是所謂的金氧半場效電晶體 (MOSFET)，隨著元件尺寸的曰益縮減，次微米尺寸的金氧 半場效電晶體同時面臨更多的挑戰。當積體電路中每一個 金氧半場效電晶體所占的長度與寬度縮小時，電晶體的通 道長度亦隨之縮減，而導致如_效應、洩漏電流、接觸 電阻等問起的加重，因而降低@導體製程的良率及元件 的可靠度。 為了發展未來高速度的超大型積體電路（ULSI)、未來 的金氧半場效電晶體，必須使用如極短通道（ultra_sh〇rt junction)、自行對準矽化金屬接觸、以及極淺的延伸源汲 極接面（extended ultra-shallow source/drain junction)等技 術。在 B. Davari 所發表的論文 “CM〇S Technology Scaling， 0.1 β m and Beyond” (in IEDM Tech. Dig., p. 555, 1 996 IEEE)中’即提到對未來尺寸縮小化的互補式金氧半場效電 晶體（complementary MOS FET; CMOS FET)的預測，並提出 如操作特性、密度、及功率消耗特性的性能的重要性。為 了進一步將互補式金氧半場效電晶體的尺寸縮小至約〇_1 微米（micrometer) ’ 在如啟始電壓（threshold voltage)、導線 的電阻·電容延遲效應（RC delay)、軟錯記率（soft error (請先閲讀背面之注意事項再填寫本頁) -裝 訂· v-線一 .U— 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標隼局員工消費合作社印掣 A7 __B7_ 五、發明説明（） rate)、功率密度的問題必須能夠加以解決。Printed by A7 ____._ B7_ of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention () Invention Field M: The present invention relates to a transistor, especially to a self-aligned petrified metal contact (self- aligned silixided contact) and an ultra-short channel metal oxide semiconductor Held effect transistor (MOSFET) forming an extended source / drain junction. Background of the Invention: Since the first integrated circuit was first invented in I960, the number of components on a single wafer in the semiconductor process has grown rapidly at an explosive rate. With the current stage of semiconductor process technology, ultra-large Ultra-larg? Scale integration (ULSI), and even higher-density era, the number of components on a single wafer has increased from thousands of components in the past to millions of components, and it can even reach the number of fabrications on a single wafer. Tens of thousands or more components. The significant increase in the number of components on a single wafer poses a major challenge to semiconductor process technology. Each semiconductor component must 'further reduce its size or occupied area without affecting its function, and at a higher accumulation Below the packing density, the function of the overall component or circuit must still remain the same, and it must even have better reliability, working life, and at the same time add the characteristics of low power consumption and low heating rate. Therefore, the paper size of the semiconductor process applies to the Chinese National Standard (CNS) A4 specification (21〇x ^^ J7 (please read the precautions on the back before filling out this page). Assemble. Order U line. 5. Description of the invention () A7 B7 The five major process technologies in the printing of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, that is, the five major process technologies including lithography, etching, deposition, ion implantation, and thermal processes must be researched and developed simultaneously to achieve the next generation The development goals of integrated circuits. S In general integrated circuits, one of the most commonly used components is the transistor with control characteristics, especially the so-called metal-oxide-semiconductor field-effect transistor (MOSFET). As the size shrinks, sub-micron-sized MOSFETs face more challenges at the same time. When the length and width of each MOSFET in the integrated circuit are reduced, the channel length of the transistor is reduced. It will also shrink, which will lead to aggravation of questions such as _effect, leakage current, contact resistance, etc., which will reduce the yield and reliability of the @Conductor process. In order to develop the future high speed Ultra-large integrated circuits (ULSI), future metal-oxide-semiconductor half-effect transistors, such as ultra-short channel (ultra_short junction), self-aligned silicon metal contacts, and very shallow extended source drain junctions ( extended ultra-shallow source / drain junction). In the paper "CM〇S Technology Scaling, 0.1 β m and Beyond" (in IEDM Tech. Dig., p. 555, 1 996 IEEE) published by B. Davari. 'That is to mention the prediction of the future reduction in size of complementary metal-oxide-semiconductor field-effect transistors (CMOS FETs) and the importance of performance such as operating characteristics, density, and power consumption characteristics. In order to further The size of the complementary metal-oxide-semiconductor half-field-effect transistor has been reduced to about 0_1 micrometers. 'In terms of threshold voltage, lead resistance, capacitance delay effect (RC delay), and soft error rate (soft error) (Please read the precautions on the back before filling out this page)-Binding · v-line one. U— This paper size applies to China National Standard (CNS) A4 (210X297 mm) Employees of the Central Bureau of Standards, Ministry of Economic Affairs Consumption cooperative stamp A7 __B7_ 5. Description of the invention () rate), the problem of power density must be able to be solved.
然而’受限於目前的微影製程技術，在傳統的半導體 製程中要定義0.1微米以下的閘極寬度，有相s當的困難。j Tanaka 等人於其著作 “A Sub-0.1 " m Gr〇〇ved GaU MOSFET with High Immunity to Short Channel effects，，中 (IEDM Tech. Dig.，p. 537, 1993 IEEE)，即提出針對定義 〇1 微米以下的閘極寬度，必須使用相移式的微影製程技術 (phase-shifted lithography) ’並配合自行對準.的氧化層間隙 壁才能加以達成。 1 在超大型積體電路（ULSI)或是大型積體電路（VLSI)的 電晶體元件中，自行對準的矽化金屬技術，是用以提昇微 米尺寸元件操作速度的關鍵，但相對來說，使用自行對準 的矽化金屬技術也必須面臨許多的挑戰般而言，自行 對準矽化金屬的技術會導致金屬入侵半導體基材的現象， 而產生接面處有洩漏電流的問題；而於自行對準石夕化金屬 的過程中，往往會有未完全去除的金屬層殘餘於閘極兩側 的間隙壁上，而導致鄰近區域間橋接（bridging)或短路（short) 等的效應。有關使用自行對準矽化金屬的技術上負面的效 應，可參考 C.Y. Lu 等人所發表的研究結果 （“process Limitation and Device Design Tradeoffs of Self-Aligned TiSi2 Junction Formation in Submicrometer CMOS Devices55, IEEE Trans. Electron Devices, vol. ED-38, No. 2, 1991) » 其 中提出在應用自行對準矽化金屬技術與淺接面技術兩者 間，在設計上所需面臨的取捨。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) .裝· 訂 k! Β7 五、 發明説明（However, it is limited by the current lithography process technology. In the traditional semiconductor process, it is difficult to define a gate width below 0.1 micron. j Tanaka et al. in his book "A Sub-0.1 " m Gr〇〇ved GaU MOSFET with High Immunity to Short Channel effects," (IEDM Tech. Dig., p. 537, 1993 IEEE), that is, the definition of Gate widths below 1 micron can only be achieved by using phase-shifted lithography 'in conjunction with self-aligned oxide spacers. 1 In ultra-large integrated circuit (ULSI ) Or large-scale integrated circuit (VLSI) transistor components, self-aligned silicide technology is the key to improve the operation speed of micron-sized components, but relatively speaking, the use of self-aligned silicide technology also Many challenges must be faced. Generally speaking, the technology of self-aligning metal silicide will cause the metal to invade the semiconductor substrate, which will cause the leakage current at the interface. In the process of self-aligning the metallization of petrified metal, Often, the metal layer that has not been completely removed remains on the gap walls on both sides of the gate, causing bridging or shorting between adjacent areas. For the technical negative effects of quasi-silicides, refer to the research results published by CY Lu et al. ("Process Limitation and Device Design Tradeoffs of Self-Aligned TiSi2 Junction Formation in Submicrometer CMOS Devices55, IEEE Trans. Electron Devices, vol. ED -38, No. 2, 1991) »It proposes the trade-offs in design between the application of self-aligned metal silicide technology and shallow junction technology. This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page). Binding and ordering k! Β7 V. Description of the invention (
經濟部中央標準局員工消費合作社印製 本發明的目的為提供一種電晶體的形成方法 本發明的另一目的為提供一種具有延伸源汲 jar . w 卸的 極知通道金氧半場效電晶體（MOSFET)形成之方法。 ^ 本發明的再一目的為提供一種具自行對準接觸的金氧 半場效電晶體形成之方法。 本發明的再一目的為提供金氧半場效電晶體形成之方 法’可使金氧半場效電晶體具有低接觸電阻及低拽漏電流 的特性，並可形成極淺的延伸源汲極接面區域。 η 本發明的再一目的為提供金氧半場效電晶體形成之方 法’可突破目前微影技術最小尺寸的限制，形成極短通道 的金氧半場效電晶體，以進一步提昇半導體元件的積集 度。 本發明中形成電晶體之方法可包含以下步驟：首先形 成一墊絕緣層於基材上；並形成一堆疊層於墊絕緣層上； 再去除部分之堆疊層，以形成一開口於第一墊絕緣層之上 方；並形成一第一間隙壁於開口之内側，以定義—閘極空間 於第一墊絕緣層之上方；之後植入第一型離子，於閘極空 間下方之半導體基材内，以形成一防隧穿區；再去除部分 第一墊絕緣層，以於閘極空間及堆疊層下方之半導體基材 上方，形成一底切空間；並形成一第二墊絕緣層於底切空 間内’以及閘極空間下方之半導體基材上；接著形成一閉 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閱讀背面之注意事項再填寫本頁〕 .裝 -訂 Ό線 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明（） 極於閘極空間内；並去除堆疊層及第一間隙壁；再形成一 第二間隙壁於閘極之側壁；之後去除位於第二間隙壁外之 第一墊絕緣層，以保留一閘極絕緣層於閘極友第二間隙壁 下方；並去除第二間隙壁；再形成一矽層於半導體基材 上；接著形成一第三間隙壁於閘極外側之矽層上；並植入 第二型離子於矽層内；再形成一金屬層於矽層及第三間隙 壁上方；之後對半導體基材進行一第一熱處理，以使矽層 上方之金屬層形成一矽化金屬層；再對半導體基材植入第 三型離子；並對半導體基材進行一第二熱處理，以使第三 型離子於半導體基材内形成一接面區；接著去除金屬層及 第三間隙壁；並去除第三間隙壁下方之矽層；並植入第四 型離子於閘極兩側之半導體基材内，以形成一延伸接面 區。 而本發明中之方法，可再加入以下步驟，以形成對主 動區域的電性連接：包含形成一絕緣層於半導體基材上； 並對半導體基材進行一第三熱處理；及對半導體基材進行 一連線製程。 圖式簡單說明： 第一、圖 顯示本發明中形成墊絕緣層與堆疊層於一 基材上之截面示意圖。 第二舅 顯示本發明中形成一開口-於墊絕祿層·上本 之截面示意圖。 (請先閱讀背面之注意事項再填寫本頁) .装· 、?! 線· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A 7 B7 五、發明説明（) 第三圖 顯示丰發明中形成形成第—一間一隙壁於開口， 之内側，以定義一閘極一空一間於第一塾絕緣層 之，上方之截面示意._圖。 : 1 第四t圖 顯示本發明中去除部分第一〜塾j邑緣層，以於， .閘極空間及堆疊層下方之半導體基材上. 方，形成一底切空間之截面示_意圖。 第五圖 顯示本發明中形成一第二羞絕緣層於底边 .家間内及！閘極空間下方之半導-體基材上之、 截面示意圖。 第六圖. 顯示本發明中形成一閘極於.閘極空間内之 截面示意圖。 第七圖 顯示本發明中去除堆疊層及第一間隙壁，並 形成一第二間隙壁於閘極-之側壁_ 4截面示 意圖。 第八圖 ·顯示本發明中去除位於第士間.隙壁外之第 一墊絕緣層，以保留一閘極、絕缘層於閘極及_ 第二間隙壁下方之截面示意圖。 第九圖 顯示本發明中去除第二間-隙壁，並形成一砍- 層於半導體基材上之截面示意圖。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 第十圖 顯示本發明中形成一第三間隙壁於閘極外 、 .側之梦層上，並植入第二型離子於第三間隙… 壁…内_之截__面示意圖。 第十一圖 顯示本發明中形成一金屬層於破_層及第〜三 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 ___B7五、發明説明（） 間隙壁上方，並對半導體基材進行—第一熱 處理，以使矽層上方之金屬層成—為矽化: 屬層之截面示意圖。 S 第十二圖顯示本發明中對·半導體基材植〜入-第三..型離 子之截面示意圖。 第十.三圖顯示本發明中去除金.屬層及第三f4隙壁，並 去除第三間隙壁―下方之矽層之戴面示意 圖。 第十四圖顯示本發明中植入第四型離子於閘極兩側 , 之半導體基材内，以形成一延伸接面區支截 面示意圖。 第十五圖顯示本發明中形成一絕緣層於半導體基材 上之截面示意圖。 第十六圖顯示本發明中對半導體基材進行一表線製 ”程之截面示意圖。 發明詳細說明： 本發明中提供一種具自行對準接觸及延伸源汲極接面 的極短通道金氧半場效電晶體（MOSFET)形成之方法，M丄 稽由 一第一間隙壁的結構，可突破目前微影技術的限制，定義 一小尺寸、短通道的閘極，並利用一第三間隙壁結構的形 成及去除，消除自行對準矽化金屬過程中金屬層的殘餘效 應，因而減少鄰近區域間橋接（bridging)或短路（short)等的 本紙張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐） f請先閲讀背面之注意事項再填寫本頁j •裝 ，、17. 線' 、發明説明（ 經濟部中央標隼局員工消費合作社印製 問題.’以增進丰这 - 氧半場效電曰：二! 靠性及良率，並同時提再金 欢電日日體的操作速度與特性。 體製2:限制本發明的精神及應用範圍下，苡下以-半導 λ 形成 Ν通道之金氧半場效電晶體（NMOS)為 例’介紹本發明之眘#，工# _ ., 實施 而熟此領域技藝者，可利相同之 万法’以形成' —p .S >入β 通道之金氧半場效電晶體（PMOS)，其變 =節即不”述。參見第-圖所示，…供-半導 本〇,半導體基材10可為一矽材質、晶向為<1〇〇>么 基材，並形成一第一墊絕緣層12於半導體基材1〇 ，，如圖中所示，第一墊絕緣層可為一氧化層，此氧化肩 於-含氧環境中’由半導體基# iq #熱氧化成長而 氧化層12之厚度可為約2〇埃（angstroms)至400埃之 2 之後形成_堆#層14於氧化層12上以本實施例而 » ，堆疊層14可使用一氮化矽層，氮化矽層14之形成< 使用洗積方式達成，例如使用化學氣相沈積法等此氮牝 梦層14之厚度約為1〇〇〇埃至2500埃之間。 參見第二圖所示，接著再去除部分的氮化矽層1 6，以 形成一開口 18於氮化矽層14内，也就是氧化層12的上方β 去除部分氮化矽層丨4以形成開口丨8的步驟，可利用一 _ 案化的製程進行，圖案化的程序包含先形成一光阻層16於 1化梦層14上，並定義開口 18區域的圖案於光阻層ι6上， 再以光阻層16為一罩幕，以蝕刻的方式去除部分的氮化矽 層14 ’即形成如圖中所示的開口 18，並於圖案化程序完成 (請先閲讀背面之注意事項存填寫冬ίο .装 ▲Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economics The purpose of the present invention is to provide a method for forming a transistor. Another object of the present invention is to provide a well-known channel metal-oxygen half field effect transistor with an extended source drain. MOSFET). ^ Another object of the present invention is to provide a method for forming a gold-oxygen half field effect transistor with self-aligned contact. Yet another object of the present invention is to provide a method for forming a metal-oxide-semiconductor half-field-effect transistor. region. η Another object of the present invention is to provide a method for forming a gold-oxygen half-field-effect transistor, which can break through the limitation of the smallest size of the current lithography technology, and form a gold-oxygen half-field-effect transistor with an extremely short channel, so as to further improve the accumulation of semiconductor elements. degree. The method for forming a transistor in the present invention may include the following steps: firstly forming a pad insulating layer on the substrate; and forming a stacked layer on the pad insulating layer; and then removing a part of the stacked layer to form an opening in the first pad Above the insulating layer; and forming a first gap wall inside the opening to define-the gate space is above the first pad insulating layer; then implanting the first type ions in the semiconductor substrate below the gate space To form a tunnel prevention area; and then remove part of the first pad insulation layer to form an undercut space above the gate space and the semiconductor substrate below the stacked layer; and form a second pad insulation layer undercut In the space 'and on the semiconductor substrate under the gate space; then a closed paper size is applied to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (please read the precautions on the back before filling this page). -Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, A7 B7 V. Description of the invention () Extremely in the gate space; and remove the stacking layer and the first gap wall; and then form a second gap On the side wall of the gate; then remove the first pad insulation layer outside the second gap wall to keep a gate insulation layer under the gate gap second gap wall; and remove the second gap wall; then form a silicon layer On the semiconductor substrate; then forming a third gap wall on the silicon layer outside the gate; and implanting the second type ions in the silicon layer; forming a metal layer over the silicon layer and the third gap wall; A first heat treatment is performed on the semiconductor substrate so that the metal layer above the silicon layer forms a silicided metal layer; a third type ion is implanted into the semiconductor substrate; and a second heat treatment is performed on the semiconductor substrate to make the first The third type ions form a junction area in the semiconductor substrate; then the metal layer and the third spacer are removed; the silicon layer under the third spacer is removed; and the fourth type ions are implanted on the semiconductor substrate on both sides of the gate. Material to form an extended junction area. In the method of the present invention, the following steps can be added to form an electrical connection to the active area: including forming an insulating layer on the semiconductor substrate; and Proceed one Three heat treatments; and a connection process for the semiconductor substrate. Brief description of the drawings: First, the figure shows a schematic cross-sectional view of a pad insulation layer and a stacked layer formed on a substrate in the present invention. The second figure shows the present invention Form an opening-a schematic diagram of the insulation layer on the pad · The upper section. (Please read the precautions on the back before filling out this page). Installation · · ?! Line · This paper size applies the Chinese National Standard (CNS) A4 specification ( 210X297 mm) A 7 B7 V. Description of the invention (3) The third figure shows that the first-and-one-gap wall is formed in the opening of Fengfeng Invention to define a gate and a space in the first insulating layer. The upper cross-section is schematic. _ Figure.: 1 The fourth t figure shows the removal of part of the first ~ 塾 j eup margin layer in the present invention, so that the gate space and the semiconductor substrate under the stacked layer are above the square. A cross section of an undercut space shows the intent. The fifth figure shows that a second insulation layer is formed on the bottom side of the present invention. A schematic cross-sectional view of a semiconductor-body substrate below the gate space. Fig. 6 is a schematic cross-sectional view showing the formation of a gate electrode in the gate space in the present invention. The seventh figure shows the cross-sectional view of removing the stacking layer and the first spacer and forming a second spacer on the side wall of the gate electrode in the present invention. Figure 8 · Shows a schematic cross-sectional view of the present invention in which the first pad insulation layer outside the gap between the first and second gaps is removed to retain a gate electrode and the insulating layer below the gate electrode and the second gap wall. The ninth figure is a schematic cross-sectional view of removing a second interstitial wall and forming a chopped layer on a semiconductor substrate in the present invention. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). The tenth figure shows that a third gap wall is formed on the dream layer on the side of the gate outside the gate and is planted in the present invention. Schematic diagram of section __ of the second type ion in the third gap ... wall ... The eleventh figure shows that a metal layer is formed in the present invention and the third paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ___B7 2. Description of the invention () Above the barrier wall, the semiconductor substrate is subjected to a first heat treatment so that the metal layer above the silicon layer is formed into a silicide: a schematic cross-sectional view of a metal layer. S The twelfth figure is a schematic cross-sectional view of the implantation of the semiconductor substrate to the third-type ion in the present invention. The tenth and third figures show the schematic diagram of the wearing surface of the present invention in which the metal layer and the third f4 gap wall are removed, and the third gap wall—the lower silicon layer is removed. The fourteenth figure is a schematic cross-sectional view of implanting a fourth type ion in the semiconductor substrate on both sides of the gate to form an extended junction area in the present invention. Fig. 15 is a schematic cross-sectional view showing the formation of an insulating layer on a semiconductor substrate in the present invention. The sixteenth figure shows a schematic cross-sectional view of the process of performing a surface wire process on a semiconductor substrate in the present invention. Detailed description of the invention: The present invention provides a very short channel metal oxide with self-aligned contact and extended source-drain junctions. The method of forming a half field effect transistor (MOSFET) uses a structure of a first gap wall, which can break through the limitations of the current lithography technology, define a small size, short channel gate, and use a third gap wall The formation and removal of the structure eliminates the residual effect of the metal layer in the process of self-aligning the silicided metal, thereby reducing bridging or shorting between adjacent areas. This paper standard applies to China National Standard (CNS) A4 specifications ( 210X297 mm) f Please read the notes on the back before filling in this page. J • equipment, 17. line ', invention description (printed by the staff consumer cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs.' To enhance Feng this-oxygen half field Effective electricity said: Two! Reliability and yield, and at the same time improve the operating speed and characteristics of Jinhuandian solar system. System 2: Limit the spirit and application of the present invention, Majestic--conducting λ shape Metal Oxide Half Field-Effect Transistor (NMOS) forming an N channel is taken as an example. "Introduction of the present invention is careful # ， 工 # _., And those skilled in the art can implement the same method to form" -p .S > Metal Oxide Half-Field-Effect Transistor (PMOS) into the β channel, its change = section is not ". See the figure -... for-semiconductors 0, the semiconductor substrate 10 can be a silicon material, The crystal orientation is < 100, > and a first pad insulating layer 12 is formed on the semiconductor substrate 10, as shown in the figure, the first pad insulating layer may be an oxide layer, and this oxidation Shoulder-in an oxygen-containing environment, the semiconductor layer # iq # grows by thermal oxidation and the thickness of the oxide layer 12 may be about 20 angstroms to 400 angstroms. Then, a stack # layer 14 is formed on the oxide layer 12 to In this embodiment, the stacked layer 14 may be a silicon nitride layer. The formation of the silicon nitride layer 14 is achieved using a wash-out method, for example, using a chemical vapor deposition method. 100 Angstroms to 2500 Angstroms. As shown in the second figure, a portion of the silicon nitride layer 16 is then removed to form an opening 18 in the silicon nitride layer 14, and The step of removing a part of the silicon nitride layer β from the oxide layer 12 to form an opening 8 can be performed by a process of patterning, and the patterning process includes first forming a photoresist layer 16 and a dream layer. 14 and define a pattern of the area of the opening 18 on the photoresist layer ι6, and then use the photoresist layer 16 as a mask to remove a portion of the silicon nitride layer 14 'by etching to form an opening as shown in the figure. 18, and completed the patterning process (please read the precautions on the back and fill in the winter).
1:1 —H I I-----1 -1 本紙張尺度適用中國國家標準（CMS ) A4規格（2!0'乂297公釐） 五、發明説明（ A7 B7 經濟部中央標準局員工消費合作社印製 後將光阻層16去除。 參見第二圖所示，开^ 士、 t成一第一間隙壁2 0於開口 18之 内側，以定義一閘極空„ . 彼工間22於氧化層12的土方，本例中 之第一間隙壁20可使用 丁 尺用—氮化矽間隙壁，一般而言，氮化 矽間隙壁20的形成方沬 ， 可藉由沈積並回.姓一說化發的過 程即可完成。利用此H几伙ηη , 虱化矽間隙壁20，可進一步縮小原來 開口 1 8的寬度，並突/ 傳統微影製程所能定義的最小尺寸 的限制，而順利的腺 開極區域的寬度縮減至次微米（sub micrometer)、甚至熹承， 文小的尺寸範圍’並可由改變氮化％ 間隙壁30，自由的調敕 ^ ^ ^ I - * λα 正閘極區域的寬度，而不會受到微影 製程最小寬度的限制。 接著對半導體基材ln# 墙 , 何1 〇植入第一型離子，以於閘極空間 22的下方之半導體基鉍1Λ 材内形成一防隧穿區24，如第三 圖所，植入第一 ill j2_ 離子以形成防隧穿區24之步驟，可使 用一離子植入製程，读—也私， 透過进度較低而易於穿透的氧化層 12，將離子植入半導體其# _ 守遛基材10之中’植入之能量約為5Ke， 至lOOKeV，以使防隧穿ρ ο」θ 士 隨茅£ 24具有—離子濃度約為1Ε11至 1E14 atoms/cm2。以形成—Ν型之金氧半場效電晶體（nm〇s 來說，第一型離子可使用如硼離子或含硼離子等的離子； 但若以形成p型之金氧半場效電晶體（PM〇s)而言第一型 離子則可使用如砷離子及磷離子等的離子。 參見第四圖所示，去除部分之氧化層12，以於閘極空 間22及氮化發層14的下方，位於半導體基材1〇上方處， 10 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) d. -裝- 訂 線 經濟部中央標準局員工消費合作社印製 A7 _ B7 五、發明説明（） 形成一底切空間26;此一去除部分之氧化層12的步驟，可 使用一溼蝕刻的方式，利用其非等向性的蝕刻特性，來去 除氮化矽層14下方的氧化層12，以形成底Θ空間2 6。再1: 1 —HI I ----- 1 -1 This paper size is applicable to Chinese National Standard (CMS) A4 specification (2! 0 '乂 297 mm) V. Description of the invention (A7 B7 Staff consumption of Central Bureau of Standards, Ministry of Economic Affairs The photoresist layer 16 is removed after printing by the cooperative. As shown in the second figure, the first spacer 20 is formed inside the opening 18 to define a gate electrode space.. For the earthwork of the layer 12, the first spacer 20 in this example can be a T-silicon spacer, in general, the formation of the silicon nitride spacer 20 can be deposited and returned. The process of chemical hair treatment can be completed. With this group of ηη, the silicon spacer 20 can further reduce the width of the original opening 18, and highlight the limit of the minimum size that can be defined by the traditional lithography process, and The width of the smooth open-gland region is reduced to sub micrometers, or even smaller. The size range of the text is small and can be changed by nitriding%. The spacer 30 can be adjusted freely. ^ ^ ^ I-* λα Positive gate The width of the polar region is not limited by the minimum width of the lithography process. ln # wall, He 1 〇 implanted the first type ions to form a tunnel prevention region 24 in the semiconductor-based bismuth 1Λ material below the gate space 22, as shown in the third figure, implanted the first ill j2_ ion In order to form the tunnel prevention region 24, an ion implantation process can be used, which is also read-only. The ion is implanted into the semiconductor through the oxide layer 12 which is relatively slow and easy to penetrate. The implanted energy is about 5Ke to 10OKeV, so that the tunneling prevention ρ θθθθ is £ 24 with an ion concentration of about 1E11 to 1E14 atoms / cm2. In order to form -N type gold-oxygen half field effect Transistors (for nmOs, the first type of ions can use ions such as boron ions or boron-containing ions; but if the formation of p-type metal-oxide half field effect transistor (PM0s) for the first type ions Then, ions such as arsenic ions and phosphorus ions can be used. Referring to the fourth figure, a part of the oxide layer 12 is removed so as to be under the gate space 22 and the nitrided hair layer 14 and above the semiconductor substrate 10 10 paper sizes are applicable to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the (Please fill in this page for the matters needing attention) d. -Installation-Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _ B7 V. Description of the invention () Forming an undercut space 26; this step of removing part of the oxide layer 12 A wet etching method can be used to utilize its non-isotropic etching characteristics to remove the oxide layer 12 under the silicon nitride layer 14 to form a bottom Θ space 26.
I 形成一第二墊絕緣層28於底切空間26内及閘極空間22下 方之半導體基材 1 〇上；於本實施例中，第二墊絕緣層 2 8 可使用一氮氧化層，氮氧化層 28係於一含氮及氧之環境 中，由半導體基材10加熱成長而成，氮氧化層28之厚度 約為20埃（angstroms)至400埃。此處先將氧化層1 2去除， 再形成氮氧化層2 8的目的，即是為了增進閘極氧化層的品 質，以得刼更好的元件操作特性。藉由此一方法，可將受 到蝕刻及離子植入破壞，品質及均勻度較差的氧化層1 2去 除，並以重新成長的氮氧化層2 8，提供一介電特性良好， 高均一度的閘極氧化層。 接著形成一閘極3 0於閘極空間22内，如第六圖中所 示；一般來說，-閘極3 0可由沈積並回蝕一多晶矽層，而形 成如圖中所示的，填於閘極空間2 2内的閘極3 8，此多晶矽 層可由一低壓化學氣相沈積法來形成，而其回蝕則可由一 乾蝕刻之步驟來達成，藉由前述的氮化矽間隙壁3 0，本例 中的閘極30可縮小至約0.3微米至0.1微米，甚至是更小 的範圍。 參見第七圖所示，接著將氮化矽層1 4及氮化矽間隙壁 3 0去除，並形成一第二間隙壁3 2於閘極3 0的侧壁上；同 前所述，本例中之第二間隙壁3 2可同樣使用一氮化矽間隙 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ο—择衣—— (請先閱讀背面之注意事項再填寫本百〇 訂 經濟部中央標隼局員工消費合作社印製 A7 _______B7_五、發明説明（） 壁’ 一般而言’氮化石夕間隙壁32的形成方法’可藉由沈積 並回姓一氮化矽層的過程即可完成。之後去除位於氮化石夕 間隙壁3 2範圍之外的氧化層1 2，以保留所留苄的一小部分 氧化層12以及氮氧化層2 8，以做為一位於閘極3 0及氮化 矽間隙壁3 2下方的閘極絕緣層3 4，如第八圖所示。 再將氮化矽間隙壁32去除，如第九圖所示，並接著形 成一矽層36於半導體基材1〇上；此一矽層可藉由沈積一 厚度較薄之未摻雜多晶矽層，均勻的覆蓋於閘極30、閘極 絕緣層34、及半導體基材1〇上，其厚度約可為300埃 (angstroms)至2500埃之間。接著形成一第三間隙壁38於 閘極3 0外側之石夕層3 6上，如第十圖所示；同樣的，本例 中之第三間隙壁3 8可使用一氮化矽間隙壁，藉由沈積並回 蝕一氮化矽層的過程即可完成。 之後植入第二型離子於矽層36内；以本例而言，植入 第二型離子之步驟，可使用一離子植入製程，將離子植入 矽層36之中，植入之能量約為5Kev至1 OOKeV，以使矽層 36具有一離子濃度約為5E13至5E16atoms/cm2。第二麼離 子可使用含氮之離子，藉由含氮離子植入對砍層36產生的 表面處理效應，可對後續的自行對準梦化金屬的製程產生 正面的影響，而使自行對準矽化金屬的製程中形成 TiN/TiSi2的複合層，而能有效消除金屬層穿入基材的效應 (spiking effect) ° 接著即進行一自行對準矽化金屬的製程，如第十一圖 12 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本買)I forms a second pad insulation layer 28 on the semiconductor substrate 10 in the undercut space 26 and below the gate space 22; in this embodiment, a second pad insulation layer 28 can use a nitrogen oxide layer, nitrogen The oxide layer 28 is formed by heating and growing the semiconductor substrate 10 in an environment containing nitrogen and oxygen. The thickness of the nitrogen oxide layer 28 is about 20 angstroms to 400 angstroms. Here, the purpose of removing the oxide layer 12 and then forming the nitrogen oxide layer 28 is to improve the quality of the gate oxide layer and obtain better device operating characteristics. By this method, the oxide layer 1 2 which is damaged by etching and ion implantation and has poor quality and uniformity can be removed, and the re-grown oxynitride layer 2 8 can provide a good dielectric property and high uniformity. Gate oxide layer. Next, a gate 30 is formed in the gate space 22, as shown in the sixth figure; in general, the -gate 30 can be deposited and etched back a polycrystalline silicon layer to form as shown in the figure. In the gate 38 of the gate space 22, the polycrystalline silicon layer can be formed by a low-pressure chemical vapor deposition method, and its etch-back can be achieved by a dry etching step, through the aforementioned silicon nitride spacer 3 0, the gate electrode 30 in this example can be reduced to about 0.3 micrometers to 0.1 micrometers, or even a smaller range. Referring to the seventh figure, the silicon nitride layer 14 and the silicon nitride spacer 30 are removed, and a second spacer 32 is formed on the side wall of the gate 30. As described above, this The second spacer wall 32 in the example can also use a silicon nitride gap. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ο—choose clothes— (Please read the precautions on the back before filling The 100th order printed by the Consumers 'Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed A7 _______B7_ V. Description of the invention () Wall' Generally speaking, the method for forming the nitrided gap wall 32 can be deposited and returned to nitridation The process of the silicon layer can be completed. After that, the oxide layer 1 2 outside the range of the nitride wall 32 2 is removed, so as to retain a small part of the oxide layer 12 and the nitrogen oxide layer 2 8 remaining as a The gate insulating layer 34 located under the gate 30 and the silicon nitride spacer 32 is shown in the eighth figure. The silicon nitride spacer 32 is removed, as shown in the ninth diagram, and then a A silicon layer 36 is on the semiconductor substrate 10; this silicon layer can be deposited by thinner undoped The crystalline silicon layer uniformly covers the gate 30, the gate insulating layer 34, and the semiconductor substrate 10, and the thickness thereof may be about 300 angstroms to 2500 angstroms. Then, a third gap wall 38 is formed. On the stone layer 36 outside the gate 30, as shown in the tenth figure; similarly, the third spacer wall 38 in this example can use a silicon nitride spacer wall by depositing and etching back a The process of silicon nitride layer can be completed. Then, the second type ions are implanted in the silicon layer 36. In this example, the step of implanting the second type ions can use an ion implantation process to implant the ions. In the silicon layer 36, the implanted energy is about 5 Kev to 1 OOKeV, so that the silicon layer 36 has an ion concentration of about 5E13 to 5E16 atoms / cm2. As the second ion, a nitrogen-containing ion can be used. The surface treatment effect of the implantation on the cutting layer 36 can have a positive effect on the subsequent process of self-aligning the dream metal, and the TiN / TiSi2 composite layer can be formed in the process of self-aligning the silicide metal, which can effectively Eliminate the spiking effect of the metal layer penetrating the substrate ° Then a self-aligning silicon is performed The process of chemical metal, as shown in Figure 11 Figure 12 This paper size is applicable to China National Standards (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling in this purchase)
OI 裝. 訂 -線. 五、發明説明（） A7 B7 經濟部中央標準局員工消費合作社印t 所不’首先形成-金屬& 40於矽層36及氮化矽間隙壁38 的上方，金屬g 40的形成’可藉由濺鍍如鈦、姑、鎢、鎳、 及鉑等的金屬#質來it成；i再對帛導體基刼進行一第一 熱處理，可利用一熱爐管製程或是-快速加熱製程（rapid thermal processing; RTP)，以使矽層36上方之金屬層4〇之 金屬與矽反應，而成為一矽化金屬層4〇於矽層36上，而 氮化矽間隙壁38上的金屬層，由於未發生化學反應，故仍 維持其金屬材質。 接著對半導體基材植入第三型離子，可使用一離子植 入製程，將離子植入矽化金屬層40之中，而矽化金屬層4〇 中的離子，可於後續的熱製程中，擴散進入半導體基材1〇 之中’以於梦化金屬層40的下方之半導體基材1〇内形成 一接面區42，如第十二圖所示；植入第三型離子之植入能 量約為lOKev至150KeV，以產生一約為5E14至5E16 at oms/cm2之離·子濃度。以形成n型之金氧半場效電晶體 (NMOS)來說’第一型離子可使用如砷離子及鱗離子等的離 子；但若以形成P型之金氧半場效電晶體（PM〇s)而言，第 一型離子則可使用如離子或含棚離子等的離子。 並再對半導體基材進行一第二熱處理，同樣可利用前 述的熱爐管製程或是快速加熱製程 （RTP)，使梦化金屬層 40内的第三型離子、如砷離子或磷離子等，擴散進入基材 10，而形成如第十二圖中所示的接面區42。之後去除氮化 矽間隙壁3 8上未反應的金屬層以及氮化矽間隙壁3 8，如第 13 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） © (請先閱讀背面之注意事項再4·寫本頁) t Γ 線 五、發明説明（） A7 B7 經濟部中央標準局員工消費合作社印製 十三圖所示，藉由氮化矽間隙壁3 8的去除，即可完全去除 殘留之金屬’並可消除傳統製程中，因金屬層殘留於氮化 矽間隙壁38上，而導致鄰近區域間橋接（brfdging)或短路 (short)等的效應，因此可減少洩漏電流的產生，提昇元件 的可靠度。 接著去除原本位於氮化矽間隙壁3 8下方之矽層3 6，如 第十三圖所示’僅留下閘極絕緣層34於半導體基材1〇之 上，而使閘極3 0與其兩側之矽層3 6及上方的矽化金屬層 40組合成為新的閘極44。再植入第四型離子至位於於閘極 44兩側之半導體基材内，以形成一延伸接面區46，如 第十四圖中所示；植入第四型離子以形成延伸接面區46之 步驟，可使用一離子植入製程，透過密度較低而易於穿透 的氧化層12，將離子植入半導體基材1〇之中，植入之能量 約為O.lKev至20KeV ’以使延伸接面區46具有約為2E13 至2E15 atoms/cm2之離子濃度。以形成N型之金氧半場效 電晶體（NMOS)來說，第一型離子可使用如砷離子及磷離子 等的離子；但若以形成P型之金氧半場效電晶體（PM〇s)* 言’第一型離子則可使用如硼離子或含硼離子等的離子。 於電晶體的主要區域形成之後.，接下來即是進行後續 形成絕緣層及金屬連接的製程，參見第十五圖所示，首先 形成一絕緣層48於半導體基材1〇上，絕緣層.48於此實施 例中使用一沈積之氧化層；並接著對半導體基材10進行一 第三熱處理’可使用如熱爐管製程或是快速加熱製程 14 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） (請先閱讀背面之注意事項再填寫本頁} .裝. 訂 •-ο-線. 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） (RTP)，可使延伸接面區46内之第三型離子、如砷離子或 麟離子等，進一步的擴散並活化（activate)，而成為如圖中 所示之延伸接面區46;而沈積形成之氧化層18，可於此熱 Ϊ 處理過程中，因受熱而使其密度均一化而提昇其物理特 性。最後再對半導體基材1 0進行一次或是多次連線製程， 以形成對閘極44及接面區42的電性連接。金屬化導線連 接製程可包含一連串如形成接觸窗、填入導體層、以及平 坦化等的製程，其步驟為此領域中所熟知之技術，在此即 不多做介紹。 本發明中之電晶體，可利用氮化矽間隙壁3 8的形成及 去除，消除傳統製程中，因金屬層殘留而導致的橋接 (bridging)或短路（short)等的效應，以減少洩漏電流的產 生；並以離子植入及熱製程來形成極淺的延伸接面區46, 消除短通道效應，並減少因通道及閘極寬度縮短的負面效 果；並以埋入式接觸來提供更好的導電性，提供更好的元 件操作特性及可靠度。 本發明以一較佳實施例說明如上，僅用於藉以幫助了 解本發明之實施，非用以限定本發明之精神，而熟悉此領 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 範圍内，當可作些許更動潤飾及等同之變化替換，其專利 保護範圍當視後附之申請專利範圍及其等同領域而定。 (請先閱讀背面之注意事項再填寫本頁) 〇 裝· 訂 線 本紙張尺度適用中國國家標準（CNS ) A4規格（21 〇 X 297公釐）OI assembly. Order-line. V. Description of the invention () A7 B7 The Consumer Cooperative Society of the Central Bureau of Standards of the Ministry of Economy of the People ’s Republic of China shall first form-metal & 40 on the silicon layer 36 and the silicon nitride spacer 38, metal The formation of g 40 can be achieved by sputtering metal materials such as titanium, tungsten, tungsten, nickel, and platinum; and then performing a first heat treatment on the rhenium conductor substrate, which can be controlled by a hot furnace. Or-rapid thermal processing (RTP), so that the metal of the metal layer 40 above the silicon layer 36 reacts with the silicon to form a silicided metal layer 40 on the silicon layer 36, and the silicon nitride gap The metal layer on the wall 38 maintains its metal material because no chemical reaction occurs. A third type of ion is implanted into the semiconductor substrate. An ion implantation process can be used to implant the ions into the silicided metal layer 40, and the ions in the silicided metal layer 40 can be diffused in the subsequent thermal process. Into the semiconductor substrate 10 'so that a junction region 42 is formed in the semiconductor substrate 10 below the dream metal layer 40, as shown in FIG. 12; the implantation energy of the third ion implantation It is about lOKev to 150KeV to generate an ion concentration of about 5E14 to 5E16 at oms / cm2. For the formation of n-type metal-oxide-semiconductor field-effect transistors (NMOS), ions such as arsenic ions and scale ions can be used as the first type of ions; For example, ions such as ions or ions containing ions can be used as the first type ions. Then, a second heat treatment is performed on the semiconductor substrate. Similarly, the third type of ions, such as arsenic ions or phosphorus ions, in the dream metal layer 40 can be used by using the aforementioned heating furnace control process or rapid heating process (RTP). , Diffuses into the substrate 10, and forms a junction area 42 as shown in FIG. 12. After that, remove the unreacted metal layer on the silicon nitride spacer 38 and the silicon nitride spacer 38, such as the 13th paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) © (Please read the back first (Notes 4 and write this page) t Γ Line V. Description of the invention () A7 B7 The 13th figure printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs is shown in Figure 13. Residual metal can be completely removed and the effects of bridging or shorting between adjacent areas due to the metal layer remaining on the silicon nitride spacer 38 in the traditional process can be eliminated, thereby reducing leakage current The generation of components improves the reliability of components. Next, the silicon layer 36 originally located under the silicon nitride spacer wall 38 is removed, as shown in the thirteenth figure, 'only the gate insulating layer 34 is left on the semiconductor substrate 10, and the gate 30 and the The silicon layers 36 on both sides and the silicide metal layer 40 on the upper side are combined to form a new gate 44. A fourth type ion is implanted into the semiconductor substrate on both sides of the gate 44 to form an extended junction area 46, as shown in the fourteenth figure; a fourth type ion is implanted to form an extended junction In the step 46, an ion implantation process can be used to implant the ions into the semiconductor substrate 10 through a low-density and easily penetrated oxide layer 12. The implanted energy is about 0.1Kev to 20KeV ' Therefore, the extended junction area 46 has an ion concentration of about 2E13 to 2E15 atoms / cm2. For the formation of N-type metal-oxide-semiconductor field-effect transistors (NMOS), ions such as arsenic ions and phosphorus ions can be used as the first type of ions; ) * In the first type, ions such as boron ions or boron-containing ions can be used. After the main area of the transistor is formed, the next step is to perform a subsequent process of forming an insulating layer and a metal connection. As shown in FIG. 15, an insulating layer 48 is first formed on the semiconductor substrate 10 and an insulating layer. 48 In this embodiment, a deposited oxide layer is used; and then a third heat treatment is performed on the semiconductor substrate 10 'can be used, such as a furnace control process or a rapid heating process 14 The paper size applies to Chinese National Standard (CNS) A4 Specification (21〇X297mm) (Please read the notes on the back before filling in this page}. Binding. Order • -ο-line. Printed by A7 B7, Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () ( RTP), can make the third type ions in the extended interface area 46, such as arsenic ions or lin ions, further diffuse and activate (the extended interface area 46 as shown in the figure; and deposition The formed oxide layer 18 can be homogenized due to heat during the heat treatment process to improve its physical properties. Finally, the semiconductor substrate 10 is subjected to one or more connection processes to form a pair. Gate 44 and connected The electrical connection of the area 42. The metallization wire connection process may include a series of processes such as forming a contact window, filling a conductor layer, and planarizing, the steps of which are well known in the art, and are not described here. The transistor in the present invention can use the formation and removal of the silicon nitride spacers 38 to eliminate the effects of bridging or shorting caused by the residual metal layer in the traditional process to reduce leakage. Current generation; and use ion implantation and thermal processes to form a very shallow extended junction area 46 to eliminate short channel effects and reduce negative effects due to shortened channel and gate widths; and provide more contact with buried contacts Good conductivity, providing better device operating characteristics and reliability. The present invention is described above with a preferred embodiment, and is only used to help understand the implementation of the present invention, not to limit the spirit of the present invention, but to be familiar with it. After realizing the spirit of the present invention, those skilled in the art can make minor modifications and equivalent changes without departing from the spirit of the present invention. The accompanying claims and their equivalents field may be. (Please read the notes on the back of this page and then fill in) square-installed custom line of this paper scale applicable Chinese National Standard (CNS) A4 size (21 X 297 mm square)