KR20020027772A - Method for fabricating dual gate type MOS transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a dual-gate metal-oxide-semiconductor(MOS) transistor is provided to make a dual gate process used in forming high-capacity and high-precision low power products, by differentiating an ion implantation process for forming an active junction from an ion implantation process for gate doping. CONSTITUTION: A P well(104) is formed in an NMOS formation part(A) of a semiconductor substrate, and an N well(106) is formed in a PMOS formation part(B). A gate structure of an intrinsic polysilicon layer and a metal layer is formed on the P and N wells. An N-LDD region and a P-LDD region are formed in the substrate at both edges of the gate in the NMOS formation part and the PMOS formation part, respectively. An insulation spacer is formed on both sidewalls of the gate. N+ impurity ions are implanted into the NMOS formation part, and P+ impurity ions are implanted into the PMOS formation part. An interlayer dielectric is planarized until the metal of the gate is exposed. The metal layer on the gate is removed while the interlayer dielectric is left in the active region. N+ impurity ions are implanted into the NMOS formation part, and P+ impurity ions are implanted into the PMOS formation part. An N+ source/drain region(128a) and an N+ gate(110a') are formed in the NMOS formation part, and a P+ source/drain region(128b) and a P+ gate(110a'') are formed in the PMOS formation part. A silicide layer is formed on the N+ gate and the P+ gate.

Description

Method for fabricating dual gate MOS transistors {Method for fabricating dual gate type MOS transistor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a highly reliable dual gate type MOS transistor applicable to a high performance low-power product.

Conventional low power MOS transistors have been manufactured using a single gate method in which W-polycide is applied to a gate without using self-aligned silicide. This is because when Co or Ti-silicide is applied to the active, it is likely to be a leakage pass if the N + or P + junction is not deep.

When manufacturing a MOS transistor using a single gate method, the PMOS should be brought into a buried-channel structure, in order to set the threshold voltage (hereinafter referred to as Vth) of the PMOS to a level similar to the Vth of the NMOS. to be. However, in case of the buried-channel PMOS, the short-channel characteristic is worse than that of the surface-channel PMOS using the P + gate. Therefore, when the design rule of the semiconductor device is reduced to 0.18 μm or less, the buried channel PMOS is no longer suitable, and a dual gate type MOS transistor design is required.

Also important for low-power transistor designs is that they must be as deep as possible to the depth of the N + or P + junction. This is to secure a sufficient overetch margin of the contact when forming the contact and to suppress the occurrence of a short at the junction during barrier metal deposition. The problem here is that deepening the junction depth and boron penetration in the PMOS gate are in a trade-off relationship.

In conclusion, as the design rules shrink, low-power products require dual-gate MOS transistor designs, but low-power products must not only use silicide for active but also be as deep as junction depth, and at the P + gate. There are some preliminary challenges, such as the need to prevent boron from penetrating, which makes it impossible to implement high-performance, low-power products using the current dual gate process. Furthermore, given that high-performance transistors are required for low-power products in the future, it is necessary to completely eliminate gate depletion for both N + and P +.

This will be described in detail below with reference to a process flowchart showing a conventional method of manufacturing a dual gate type MOS transistor shown in FIGS. 1A to 1C. For convenience, the process is divided into three stages.

As a first step, as shown in FIG. 1A, the P well 14 is formed in the NMOS forming portion A and the N well is formed in the PMOS forming portion B in the semiconductor substrate 10 having the shallow trench isolation (STI) 12. After the formation of the 16, the gate 20 made of an intrinsic polysilicon material is formed on the P well 14 and the N well 16 via the gate insulating layer 18. Thereafter, a lightly doped drain (N-LDD) region 22a is formed in the substrate 10 on both edges of the gate 20 located in the NMOS forming portion A, and the gate 20 located in the PMOS forming portion B. P-LDD regions 22b are formed in the substrate 10 on both edges. After forming spacers 24 of insulating material on both sidewalls of the gate 20, and forming the first photoresist layer pattern 26 on the resultant so that the NMOS forming portion A is opened, the gate ( 20) and ion implantation of high concentration N-type (N + -type) impurities such as As onto the substrate 10 using the first photosensitive film pattern 26 as a mask to form the N + type and the active (the portion where the source / drain will be formed). do. In FIG. 1A, a portion indicated by ⓐ indicates an N + type impurity implantation region in the P well 14.

As a second step, as shown in FIG. 1B, the first photoresist pattern 26 is removed, and a second photoresist pattern 28 is formed on the resultant to open the PMOS forming portion B, and then the gate ( 20) and a high concentration P-type (P + -type) impurity such as B or BF ₂ on the substrate 10 using the second photosensitive film pattern 26 as a mask to make the active and the active (part where the source / drain is to be formed) into P + type. Ion implantation. In FIG. 1B, a portion indicated by ⓑ represents a P + type impurity implantation region in the N well 16.

As a third step, as shown in FIG. 1C, the second photoresist layer pattern 28 is removed, and heat treatment is performed to activate the NMOS forming portion A. An N + type source / drain region 30a having an LDD structure An N + type gate 20a is formed, and a P + type source / drain region 30b and a P + type gate 20b having an LDD structure are formed in the PMOS forming portion B. Subsequently, a high melting point metal of Co or Ti is formed on the resultant, and heat treatment is performed. At this time, on the gates 20a and 20b and the source / drain regions 30a and 30b, silicon and a high melting point metal react to form a silicide film 32, which is a low resistance metal, whereas an STI 12 is formed. In the portion where the portion or the spacer 24 is formed, silicon and the high melting point metal do not react, and the high melting point metal remains as the unreacted metal. Thereafter, the unreacted high melting point metal is removed to form an NMOS transistor on the P well 14 and a PMOS transistor on the N well 16, thereby completing the present process.

However, in the conventional dual gate MOS transistor manufacturing process, since both the NMOS and PMOS transistors are simultaneously doped with gate and active impurity doping, ie, ion implantation, a problem arises that they are not suitable for fabricating MOS transistors for high performance low power products. This is because the gate depth and boron penetration and the junction depth of the source and drain regions must be controlled by one ion implantation energy. In this case, the silicide film is also formed in the active source / drain regions at the time of salicidation.

Accordingly, an object of the present invention is to prevent ion implantation for forming active junctions (source / drain regions) and ion implantation for gate doping in the manufacture of a dual gate type transistor, and at the same time to prevent the salidate from being active. The present invention provides a method of manufacturing a dual gate type MOS transistor that solves the problems caused by applying the dual gate process to a high performance, high density and low power product.

1A to 1C are process flowcharts showing a conventional method of manufacturing a dual gate MOS transistor;

2A to 2H are process flowcharts illustrating a method of manufacturing a dual gate type MOS transistor proposed in the present invention.

In order to achieve the above object, in the present invention, a step of forming a P well and an N well in the NMOS forming portion in the semiconductor substrate with STI; Forming a gate having an "intrinsic polysilicon film / metal film" laminated structure by interposing a gate insulating film on the P well and the N well, respectively; Forming an N-LDD region in the substrate on both edges of the gate of the NMOS forming portion and a P-LDD region in the substrate on both edges of the gate of the PMOS forming portion; Forming insulating spacers on both sidewalls of the gate; Ion implanting N + -type impurities into the NMOS forming portion and ion implanting P + -type impurities into the PMOS forming portion for implanting impurities into the active; Forming an interlayer insulating film on the resultant product; Planarizing the interlayer insulating film until the metal film of the gate is exposed; Removing the metal layer on the gate, but leaving the interlayer insulating layer in an active region; Ion implanting N + -type impurities into the NMOS forming portion and ion implanting P + -type impurities into the PMOS forming portion for gate doping; Performing heat treatment to form an N + type source / drain region and an N + type gate in the NMOS forming portion, and a P + type source / drain region and a P + type gate in the PMOS forming portion; And forming a silicide layer on top of the N + gate and the P + gate.

When the dual gate type MOS transistor is manufactured based on the above process, ion implantation for forming an active junction and ion implantation for gate doping are performed separately, so that optimized ion implantation conditions and ions can be selected in each case. In addition, during the process, silicide is not naturally formed in the active process, and silicide is formed only in the gate.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2H illustrate a process flowchart showing the method of manufacturing the dual gate type MOS transistor proposed in the present invention. Referring to this, the manufacturing method is divided into eight steps.

As a first step, as shown in FIG. 2A, the P well 104 is formed in the NMOS forming portion A of the semiconductor substrate 100 provided with the STI 102, and the N well 106 is formed in the PMOS forming portion B, respectively. After the formation, the gate 112 is formed on the P well 104 and the N well 106 by interposing a gate insulating layer 108. In this case, the gate 112 is formed to have a structure in which a metal film 110b of W material is further deposited on the intrinsic polysilicon film 110a, and the metal film is formed to a thickness of 200 Å or less. Thereafter, an N-LDD region 114a is formed in the substrate 100 on both edges of the gate 112 located in the NMOS forming portion A, and both edges of the gate 112 located in the PMOS forming portion B are formed. The P-LDD region 114b is formed in the substrate 100. Spacers 116 of insulating material are formed on both sidewalls of the gate 112, and the first photoresist layer pattern 118 is formed on the resultant so that the NMOS forming portion A is opened. High concentration N-type (N + -type) impurities such as As are ion-implanted onto the substrate. At this time, since the metal film 112 on the gate 112 sufficiently serves as an implant stopper when implanting N + -type impurity ions, almost no dose is injected into the gate region. In FIG. 2A, a portion indicated by ⓐ indicates an N + type impurity implantation region in the P well 104.

As a second step, as shown in FIG. 2B, the first photoresist pattern 118 is removed, and the second photoresist pattern 120 is formed on the resultant so that the PMOS forming portion B is opened. High concentration P-type (P + type) impurities such as B or BF ₂ are ion-implanted onto the substrate. In this case as well, since the metal film 110b serves as an ion implantation stopper, almost no dose is implanted into the gate region. In FIG. 2B, a portion indicated by ⓑ represents a P + type impurity implantation region in the N well 106. Therefore, the junction depth can be adjusted by performing ion implantation of sufficient energy as desired without worrying about boron infiltration.

As a third step, as shown in FIG. 2C, the second photoresist layer pattern 120 is removed, and the interlayer insulating layer 122 made of P-TEOS material is sufficiently thickly formed on the resultant product. This is an interlayer insulating film for chemical mechanical polishing (CMP) to the gate metal film 110b, and if necessary, a CMP stopper before deposition of the interlayer insulating film 122, or a contact stopper at the time of forming a contact in a subsequent process. It is a matter of course that a film quality (for example, a SiON film or a SiN film) to serve as a contact stopper can be deposited first with a thickness of about 500 GPa.

As a fourth step, the interlayer insulating film 122 is subjected to CMP treatment until the surface of the metal film 110b constituting the gate 112 is exposed as shown in FIG. 2D.

As a fifth step, as illustrated in FIG. 2E, the metal film 110b on the upper end of the gate 112 is removed by an etch back process. In this case, since the interlayer insulating film 122 has a poor selectivity (2: 1) with respect to the oxide film when the metal film 110b is etched back, it may be understood that the interlayer insulating film 122 must be applied to protect the STI and the active region.

As a sixth step, after forming the third photoresist pattern 124 on the resultant to open the NMOS forming portion (A) as shown in Figure 2f, doping the gate intrinsic polysilicon film (110a) with N + type impurities For this purpose, a high concentration of N-type (N + type) impurities such as As is ion-implanted onto the substrate using the third photoresist pattern 124 as a mask.

As a seventh step, as shown in FIG. 2G, the third photoresist pattern 124 is removed, and a fourth photoresist pattern 126 is formed on the resultant product so that the PMOS forming portion B is opened. Next, in order to dope the gate intrinsic polysilicon film 110a with P + type impurities, a high concentration P type (P + type) impurity such as B or BF ₂ is ionized onto the substrate using the fourth photoresist pattern 126 as a mask. Inject.

As a result, N + type and P + type impurities are selectively implanted only in the intrinsic polysilicon film 110a, and the ion implantation energy at this time does not need to consider the junction depth and depletion and boron of the gate polysilicon film 110a. Energy can be used to minimize the penetration. In addition, the interlayer insulating film 122 serving as a stopper when the gate metal film 110b is etched back also serves as an ion implantation stopper for the active, thereby minimizing the dose injection in the active.

As an eighth step, as shown in FIG. 2H, the fourth photoresist pattern 126 is removed and a heat treatment for activation is performed to form the NMOS forming portion A with an N + type source / drain region 128a having an LDD structure and an N + type gate. 110a 'is formed, and a P + type source / drain region 128b and a P + type gate 110a' 'having an LDD structure are formed in the PMOS forming portion B. Subsequently, a high melting point metal of Co or Ti is formed on the resultant, and heat treatment is performed. At this time, on the N + type gate 110a 'and the P + type gate 110a' ', silicon and a high melting point metal are reacted to form a silicide film 128, which is a low resistance metal, whereas the interlayer insulating film 122 is covered. In the region where the spacer 116 is formed, silicon and the high melting point metal do not react, and the high melting point metal remains as the unreacted metal. Thereafter, the unreacted high melting point metal is removed to form an NMOS transistor on the P well 104 and a PMOS transistor on the N well 106 to complete the present process.

In this case, since ion implantation for forming an active junction (source and drain region) and ion implantation for gate doping are performed separately, optimized ion implantation conditions and ions can be selected in each case. In addition, during the process, silicide is not naturally formed in the active process, and silicide is formed only in the gate.

Therefore, in the conventional case, when the depth of the active junction is deeply inevitable, boron penetration naturally increases, whereas in the case of the present invention, the boron penetration into the gate can be minimized separately even when the active junction is deeply brought to a desired level. Will be. In addition, since it is not necessary to consider the junction depth of the active when doping N + or P + type impurities into the gate, it is possible to minimize (or eliminate) the depletion of the gate polysilicon layer 110a through energy control during ion implantation. In addition, since the silicide film is not formed in the active state, it is possible to fundamentally prevent the formation of the liquidity pass. As a result, device manufacturing can be achieved by applying a dual gate type MOS transistor manufacturing process to high-performance, high-density low-power products.

As described above, according to the present invention, the ion implantation for forming the active junction and the ion implantation for the gate doping are divided into separate processes, and the silicide layer is not formed in the active. As a result, the problems caused when the existing dual gate process is applied to a low power product can be eliminated, thereby enabling the dual gate process to be applied to a high performance and high density low power product.

Claims (5)

Forming a P well in the NMOS forming portion and a N well in the PMOS forming portion in the semiconductor substrate provided with the STI; Forming a gate having an "intrinsic polysilicon film / metal film" laminated structure by interposing a gate insulating film on the P well and the N well, respectively; Forming an N-LDD region in the substrate on both edges of the gate of the NMOS forming portion and a P-LDD region in the substrate on both edges of the gate of the PMOS forming portion; Forming insulating spacers on both sidewalls of the gate; Ion implanting N + -type impurities into the NMOS forming portion and ion implanting P + -type impurities into the PMOS forming portion for implanting impurities into the active; Forming an interlayer insulating film on the resultant product; Planarizing the interlayer insulating film until the metal film of the gate is exposed; Removing the metal layer on the gate, but leaving the interlayer insulating layer in an active region; Ion implanting N + -type impurities into the NMOS forming portion and ion implanting P + -type impurities into the PMOS forming portion for gate doping; Heat treatment to form an N + type source / drain region and an N + type gate in the NMOS forming portion, and a P + type source / drain region and a P + type gate in the PMOS forming portion; And And forming a silicide layer on top of the N + gate and the P + gate. 2. The method of claim 1, further comprising forming a CMP stopper or a contact etch stopper made of SiON or SiN prior to forming the interlayer insulating film. The method of claim 1, wherein the metal film forming the gate is formed of W. 7. The method of claim 3, wherein the metal film forming the gate is formed to a thickness of 200 μm or less. The method of claim 1, wherein the metal layer forming the gate is removed by an etch back process.