經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 發明領域： 本發明係與一種電晶體之製程有關，特別是有關於一 種形成具有提昇之源汲極區（elevated source/drain)及固相 擴散（solid phase diffused)的金氧半場效電晶體（metal oxide semiconductor field effect transistor; MOSFET)之方法 發明背景： 自從第一個積體電路於西元1 96 0年首先發明以來，半 導體製程中單一晶片上的元件數目，即以爆炸性的速度快 速成長，隨著半導體工業近四十年的發展，現階段的半導 體製程技術已邁入超大型積體電路（ultra large scale integration; ULSI)、以及更高密度的時代，單一晶片上的元 件數目也由以往的數千個元件，增加至數百萬個元件，甚 至可達到單一晶片上製作數千萬個或是更多個元件的密 度。 因此，半導體晶片上如電晶體、電容器、及連線等皆 必須進一步縮減其所使用面積，以提高元件積集度（packing density)，此一要求形成對半導體製程技術的一大挑戰，每 一個半導體元件皆必須在不影響其功能的前提下，進一步 縮減其尺寸或占用的面積。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公;t ) (請先閱讀r面之注意事項再填寫本頁) --------訂·-------- 經濟部智慧財產局員Η消費合作社印製 A7 _B7_ 五、發明說明（） 而在更高的積集度之下，整體元件或電路之功能仍須 維持不變、甚至必須具有更好的可靠度、工作壽命、並同 時加入低功率消耗及低發熱率的特性。因此半導體製程中 的五大製程技術，也就是包含微影、蚀刻、沈積、離子佈 植、及熱製程的四大製程技術，也就是包含微影、蝕刻、 薄膜、及擴散的製程技術，必須同時的研究與發展，以達 成下一代積體電路的發展目標。 在一般的積體電路中，最常被應用的元件之一即是具 有控制特性的電晶體，尤其是所謂的金氧半場效電晶體 (MOSFET)，隨著元件尺寸的日益縮減，次微米尺寸的金氧 半場效電晶體同時面臨更多的挑戰。當積體電路中每一個 金氧半場效電晶體所占的長度與寬度縮小時，電晶體的通 道長度亦隨之縮減，而引發的墜穿效應，將造成元件漏電 流增大及崩潰電壓減小等問題，因而降低了半導體製程的 良率及元件的可靠度。 為了發展未來次微米（sub-micrometer)尺寸、甚至是更 小尺寸的金氧半場效電晶體，必須使用極淺通道的技術， 以抑制元件尺寸縮減所造成的短通道效應。但在極小的元 件尺寸及極高的積集度下，要製造極淺通道的金氧半場效 電晶體，技術上有相當的困難，傳統的離子植入製程，很 難形成具有較高離子濃度的極淺通道。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------ * I I 1----訂·-------» (請先閱讀¥面之註意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1^43928 9 A7 __B7_ 五、發明說明（） 在K. Takeuchi 等人所發表的著作（“High performance sub-tenth micron CMOS using advanced boron doping and W S12 dual gate process”， in 1 9 9 5 Symposium on VLSI Technology Digest of Technical Papers)中，即提出此一問 題，並表示以離子植入製程的特性，要形成具有高離子濃 度的淺通道*有相當的困難性，且基材缺陷所導致的通道 區棚離子擴散造成許多問題’基村中靠近源>及極區的區域 性硼空乏現象，會更增加短通道效應。 此外，閘極結構中多晶矽中的硼離子，經常會由於侵 入閘極氧化層或穿透進入基材，而造成元件效能的退化* S.L.Wu(本發明之發明人）、C.L.Lee、及T.F. Lai即於所發 表的論文中提出上述現象（“Suppression of Boron Penetration into an Ultra-Thin Gate Oxide ( ^ 7nm) by Using a Stacked-Amorphous-Silicon (SAS) Film’’，IEDM 93-329 1993 IEEE)。 此外，在他們的論文中亦提到，p型摻雜的多晶矽己廣 泛的使用作為P型金氧半場效電晶體的閘極材質，以避免 短通道效應。一般而言’大多是使用含蝴及氣的離子（BF2) 植入以形成閘極及源汲極區’然而氟的影響會使硼離子很 容易侵入閘極氧化層或？透進入基材内’而導致元件臨界 電壓的變化，他們並提出堆疊非晶矽（stacked-amorphous silicon; SAS)層的結構，以抑制氟引發的硼離子穿透效應。 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公爱） (請先閱讀r面之法意事項再填寫本頁) i 裝--------訂--------線 1643 928 9 A7 _B7五、發明說明（） 經濟部智慧財產局員工消費合作社印製 發明目的及概述： 本發明的目的為提供一種電晶體的形成方法。 本發明的另一目的為提供一種具有提昇之源汲·極區的 金氧半場效電晶體（MOSFET)的形成方法。 本發明的再一目的為提供一種金氡半場效電晶體的形 成方法，利用電漿擴散或低能量離子植入的製程’形成極淺 的源汲極區，以進一步提昇半導體元件的特性及製程的積集 度。 本發明中形成電晶體之方法可包含以下步驟：首先形成 問極絕緣層於基材上；並形成一第一石夕層於閘極絕緣層 上；再形成一第一介電層於第一矽層上；接著去除部分之 第一介電層、第一矽層、及閘極絕緣層以定義一閘極區域； 之後摻雜基材未被閘極區域覆蓋之部分’以形成延伸源汲極 接面於基材之内；並形成未摻雜之側壁結構於閘極區域之侧 壁上；再去除第一介電層：然後形成一第二矽層於基材上 及第一矽層上；再對基材進行離子植入以摻雜第二矽層、提 供用以形成源汲極接面所需之離子。 在本發明的較佳實施例中，並可進一步加入一系列的 ----- t 1 i --------- (請先閱讀r面之泫咅〗事項再填寫本頁) 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 1143 9 2 3 9 A7 _B7 五、發明說明（） 步驟，以形成矽化金屬層於第二矽層上，其步驟可包含：首 先形成一金屬層於基材上；並進行一熱製程，以擴散並活化 延伸源汲極接面之離子，並擴散第二矽層内之離子以形成源 汲極接面於未被閘極區域及側壁結構覆蓋之基材内，並形成 矽化金屬層於第二矽層之上；最後再去除未反應之金屬層。 在另一較佳實施例之中，可於上述之形成延伸源汲區 域之摻雜步驟完成後，由基材及第一矽層加熱成長一第二介 電層於基材上，以修補蝕刻對基材表面的破壞，並避免閘極 絕缘層受到其他區域所摻雜離子的污染。 圖式簡單說明： 第一圖 顯示本發明中形成閘極絕緣層、第一矽層、 及第一介電層於基材上之裁面示意圖。 第二圖 顯示本發明中去除部分之第一介電層、第一 矽層、及閘極絕緣層以定義一閘極區域之裁 面示意圖。 第三圖 顯示本發明中摻雜基材未被閘極區域覆蓋 之部分，以形成延伸源汲極接面於基材之内 的截面示意圖。 第四圖 顯示本發明中形成未摻雜之側壁結構於閘 極區域之側壁上的截面示意圖。 第五圖 顯示本發明中去除第一介電層、並形成第二 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公蔆） (請先閱讀背面之^意事項再填寫本頁) 裝·-------訂·--------線 經濟部智慧財產局員工消費合作杜印製 A7 B7_ 五、發明說明（） 妙層於基材上之載面示意圖。 第六圖 顯示本發明中對基材進行離子植入以摻雜 第二矽層、提供用以形成源汲極接面所需之 離子的截面示意圖。 第七圖 顯示本發明中形成矽化金屬層於第二矽層 上的截面示意圖。 發明詳細說明： 本發明中提供一種具有提昇之源汲極區及固相擴散之 延伸源汲極區的金氧半場效電晶體（Μ 0 S F E T)之形成方法， 藉由提昇之源汲極區，可消除短通道效應，並藉由電漿擴 散或低能量離子植入形成極淺的延伸源汲極區，藉以抑制 隨著元件尺寸縮小所造成的短通道效應。 在不限制本發明的精神及應用範圍下，以下以一半導 體製程中，Ν型之金氧半場效電晶體（NMOS)之形成方法及 結構為例，介紹本發明之實施，而熟悉此領域技藝者’可利 用相同之精神，應用於其他不同類型電晶體之製造’其變化 之細節即不做贅述。 參見第一圖所示*首先提供一基材10，基材10 —般可 使用一矽材質 '晶向為<100>之半導體基材，亦可視不同需 要使用其他材質或是不同晶向的基材’基材〗〇上已形成隔 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） {請先閱讀背面之泷意事項再填寫本頁) --------訂·-------- 經濟部智慧財產局貝工消費合作社印製 A7 _ B7___ 五、發明說明（） 離區12，隔離區12可為如圖中所示的場氧化區或是使用其 他的隔離製程，如溝渠隔離等。 如第一圖所示’形成一閘極絕緣層14於基材1 〇上， 閘極絕緣層1 4可為一氧化矽層’此氧化矽層1 4係於一含氧 環境中，由基材1〇加熱氧化成長而成，氡化矽層〗4之厚度 可約為1 5埃（angstroms)至3 00埃之間；此外，在較佳實施 例之中，閘極絕緣層丨4亦可使用氮氧化矽層，此氮氧化矽 層14可於含氧及氮的環境中、例如含有NO或N〇2的環境 中，由基村10加熱氧化成長而成，氮氡化碎層14之厚度同 樣可約為15埃（angstroms)至300埃之間 之後形成一第一矽層16於閘極絕緣層14上，以本實 施例而言，第一矽層1 6可使用未摻雜之多晶矽層、或是僅 具有輕微摻雜之多晶矽層，其形成可使用沈積方式達成，例 如使用化學氣相沈積法等，未掺雜之多晶矽層1 6沈積之厚 度約為3 00埃至4000埃之間，若以輕微摻雜之多晶矽層而 言，則可應用沈積時同步摻雜（in-situ doped)的方式’形成 所需的輕微摻雜。 接著形成一第一介電層18於第一矽層16上’ 一般而 言，第一介電層18可使用一沈積而成之氮化矽層，第一介 電層1 8可於後續的製程做為蝕刻的中止層’以本例而言’ 此氮化矽層可使用化學氣相沈積（chemical vapor depositions 8 本紙張尺度適用令圈國家標準（CNS)A4規格（210 X 297公笈）Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention () Field of the Invention: The present invention relates to the process of a transistor, in particular to the formation of an elevated source / drain ) And solid phase diffused (metal oxide semiconductor field effect transistor; MOSFET) method. BACKGROUND OF THE INVENTION: Since the first integrated circuit was first invented in 1960, semiconductors The number of components on a single wafer in the process is growing rapidly at an explosive rate. With the development of the semiconductor industry for nearly 40 years, the current stage of semiconductor process technology has entered ultra large scale integration (ULSI). In the era of higher density, the number of components on a single wafer has also increased from thousands of components in the past to millions of components, and even the density of tens of millions or more components on a single wafer can be reached. . Therefore, semiconductor wafers such as transistors, capacitors, and connections must be further reduced in area to increase the packing density of components. This requirement poses a major challenge to semiconductor process technology. All semiconductor components must be further reduced in size or area without affecting their functions. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 male; t) (Please read the precautions on r side before filling out this page) -------- Order · ------ -Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A7 _B7_ V. Description of the Invention () Under the higher accumulation level, the function of the overall component or circuit must still remain unchanged, and it must even have better reliability Degree, working life, and low power consumption and low heating rate characteristics. Therefore, the five major process technologies in the semiconductor process, that is, the four major process technologies including lithography, etching, deposition, ion implantation, and thermal processes, that is, the process technologies including lithography, etching, thin film, and diffusion must be simultaneously Research and development to achieve the development goals of the next generation of integrated circuits. In general integrated circuits, one of the most commonly used components is a transistor with control characteristics, especially the so-called metal-oxide-semiconductor field-effect transistor (MOSFET). As the size of components decreases, submicron sizes Metal-oxygen half-field-effect transistors face more challenges at the same time. When the length and width of each metal-oxide-semiconductor half-effect transistor in the integrated circuit is reduced, the channel length of the transistor is also reduced, and the fall-through effect caused will increase the component leakage current and collapse voltage Minor issues, thus reducing the yield of semiconductor processes and the reliability of components. In order to develop future sub-micrometer size and even smaller sizes of gold-oxygen half field effect transistors, it is necessary to use extremely shallow channel technology to suppress the short channel effect caused by the reduction in component size. However, under the extremely small component size and high integration degree, it is technically difficult to manufacture gold-oxygen half field-effect transistors with very shallow channels. Traditional ion implantation processes are difficult to form with high ion concentration. Very shallow channel. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------ * II 1 ---- Order · ------- »(Please Please read the notes on ¥ face before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 ^ 43928 9 A7 __B7_ V. Description of Invention () Works published by K. Takeuchi et al. ("High performance sub- tenth micron CMOS using advanced boron doping and W S12 dual gate process ”, in 1 9 9 5 Symposium on VLSI Technology Digest of Technical Papers), this problem is raised, and the characteristics of the ion implantation process are to be formed with Shallow channels with high ion concentration have considerable difficulties, and many problems caused by ion diffusion in the channel area due to substrate defects. The phenomenon of regional boron depletion near the source in the base village and the polar region will increase even more. Channel effect. In addition, the boron ions in the polycrystalline silicon in the gate structure often cause degradation of device performance due to intrusion into the gate oxide layer or penetration into the substrate * SLWu (the inventor of the present invention), CLLee, and TF Lai That is, the above phenomenon was proposed in the published paper ("Suppression of Boron Penetration into an Ultra-Thin Gate Oxide (^ 7nm) by Using a Stacked-Amorphous-Silicon (SAS) Film", IEDM 93-329 1993 IEEE). In addition, they also mentioned in their paper that p-type doped polycrystalline silicon has been widely used as the gate material of P-type metal-oxide-semiconductor field-effect transistors to avoid short-channel effects. Generally speaking, most of them use Breathing ions (BF2) are implanted to form the gate and source drain regions. 'However, the effect of fluorine will cause boron ions to easily penetrate the gate oxide layer or penetrate into the substrate', resulting in changes in the critical voltage of the device. They also proposed a structure of stacked-amorphous silicon (SAS) layers to suppress the effect of boron ion penetration caused by fluorine. This paper size is applicable to China National Standard (CNS) A4 (210x297 public love) (Please Read the legal and matters on the r side, and then fill out this page.) I Install -------- Order -------- line 1643 928 9 A7 _B7 V. Invention Description () Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs The purpose and summary of the invention printed by a consumer cooperative: The purpose of the present invention is to provide a method for forming a transistor. Another object of the present invention is to provide a metal-oxide-semiconductor field-effect transistor (MOSFET) having a boosted source and drain region. Forming method. Another object of the present invention is to provide a method for forming a gold field half-effect transistor, which uses a process of plasma diffusion or low-energy ion implantation to form a very shallow source-drain region to further improve the semiconductor device. Characteristics and the degree of integration of the process. The method for forming a transistor in the present invention may include the following steps: first forming an interlayer insulating layer on a substrate; and forming a first stone layer on the gate insulating layer; The first dielectric layer is on the first silicon layer; then a portion of the first dielectric layer, the first silicon layer, and the gate insulating layer are removed to define a gate region; and then the doped substrate is not covered by the gate region. Part 'to form an extended source-drain connection Inside the substrate; and forming an undoped sidewall structure on the sidewall of the gate region; removing the first dielectric layer: then forming a second silicon layer on the substrate and the first silicon layer; and The substrate is ion-implanted to dope the second silicon layer to provide the ions needed to form the source-drain junction. In the preferred embodiment of the present invention, a series of- -t 1 i --------- (Please read the items on the r side first and then fill out this page) This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm). Economy Printed by the Ministry of Intellectual Property Bureau Consumer Cooperatives 1143 9 2 3 9 A7 _B7 V. Description of the invention () Step to form a silicided metal layer on the second silicon layer, the steps may include: first forming a metal layer on the substrate ; And perform a thermal process to diffuse and activate the ions that extend the source-drain junction and diffuse the ions in the second silicon layer to form the source-drain junction in a substrate that is not covered by the gate region and sidewall structure And forming a silicided metal layer on the second silicon layer; and finally removing the unreacted metal layer. In another preferred embodiment, after the doping step of forming the extended source region is completed, the substrate and the first silicon layer can be heated to grow a second dielectric layer on the substrate to repair the etching. Damage to the surface of the substrate and avoid contamination of the gate insulation layer by doped ions in other areas. Brief description of the drawings: The first figure shows a schematic cross-sectional view of a gate insulating layer, a first silicon layer, and a first dielectric layer formed on a substrate in the present invention. The second figure shows a cut-away view of the first dielectric layer, the first silicon layer, and the gate insulating layer removed to define a gate region in the present invention. The third figure shows a schematic cross-sectional view of a portion of the doped substrate in the present invention that is not covered by the gate region to form an extended source drain junction within the substrate. The fourth figure shows a schematic cross-sectional view of an undoped sidewall structure formed on the sidewall of the gate region in the present invention. The fifth figure shows that the first dielectric layer is removed in the present invention, and the second paper size is formed to apply the Chinese National Standard (CNS) A4 specification (210 X 297 male diamond) (please read the notice on the back before filling this page) ) Assembly · ------- Order · -------- Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs and Du A7 B7_ V. Description of the invention () Schematic diagram of the surface of the wonderful layer on the substrate . FIG. 6 is a schematic cross-sectional view of the present invention in which a substrate is ion-implanted to dope a second silicon layer to provide ions required to form a source-drain junction. Fig. 7 is a schematic cross-sectional view showing the formation of a silicide metal layer on the second silicon layer in the present invention. Detailed description of the invention: The present invention provides a method for forming a metal-oxide-semiconductor field-effect transistor (M 0 SFET) having a raised source-drain region and a solid-phase diffusion extended source-drain region. , Can eliminate the short-channel effect, and form a very shallow extended source drain region by plasma diffusion or low-energy ion implantation, thereby suppressing the short-channel effect caused by the shrinking of the component size. Without limiting the spirit and scope of the present invention, the following takes the formation method and structure of N-type metal-oxide-semiconductor field-effect transistor (NMOS) in a semiconductor process as an example to introduce the implementation of the present invention, and is familiar with the art in this field Those who can use the same spirit for the manufacture of other different types of transistors will not go into details. See the first picture * First, a substrate 10 is provided. Generally, a silicon material can be used. A semiconductor substrate with a crystal orientation of < 100 > can also be made of other materials or different crystal orientations. Substrate 'Substrate' 〇 has been formed on the paper size applicable to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) {Please read the intention on the back before filling this page) ------ --Order · -------- Printed by the Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7___ V. Description of the invention () Departure zone 12 and isolation zone 12 can be field oxidation zones as shown in the figure Or use other isolation processes, such as trench isolation. As shown in the first figure, 'a gate insulating layer 14 is formed on the substrate 10, and the gate insulating layer 14 may be a silicon oxide layer.' This silicon oxide layer 14 is in an oxygen-containing environment. It can be grown by heating and oxidizing the material 10, and the thickness of the silicon oxide layer 4 can be between about 15 angstroms and 300 angstroms. In addition, in the preferred embodiment, the gate insulation layer 4 also A silicon oxynitride layer can be used. The silicon oxynitride layer 14 can be grown by heating and oxidizing the base 10 in an environment containing oxygen and nitrogen, such as an environment containing NO or No2, and the nitrogen trioxide layer 14 A thickness of about 15 angstroms (angstroms) to about 300 angstroms can be formed, and then a first silicon layer 16 is formed on the gate insulating layer 14. In this embodiment, the first silicon layer 16 can be undoped. The polycrystalline silicon layer, or a polycrystalline silicon layer with only slight doping, can be formed using a deposition method, for example, using chemical vapor deposition. The thickness of the undoped polycrystalline silicon layer 16 is about 300 angstroms to 4,000. Between Angstroms, in the case of a lightly doped polycrystalline silicon layer, an in-situ doped method can be applied. Into the required slight doping. Next, a first dielectric layer 18 is formed on the first silicon layer 16. Generally speaking, the first dielectric layer 18 can be a deposited silicon nitride layer, and the first dielectric layer 18 can be used in a subsequent step. The process is used as the stop layer for etching 'for this example'. This silicon nitride layer can be chemical vapor depositions (chemical vapor depositions 8) This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 cm)
It I I ί * ----I I--— — — — — — — It I i請先閱請資面之法意事項再填寫本頁) ^43928 9 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（) CVD)或是電敷增強式化學氣相沈積（p丨asma_enhanced chemical vapor deposition; PECVD)的方式加以形成，其厚 度約在300埃至1500埃之間。 參見第二圖所示’去除部分之第一介電層〖8、第一石夕 層1 6、及閘極絕緣層1 4 ’以定義一閘極區域。閘極區域之 形成’可使用一般的圖案化製程，也就是包含微影製程及钱 刻製程的一連串步驟。一般定義閘極區域的過程可包含以下 步驟：首先形成一光阻層20於第一介電層上；再利用微影 製程令的曝光及顯影’以定義一閘極圖案於光阻層2〇上； 並以光阻層20為罩幕’蝕刻第一介電層18、第—妙層16、 及閘極絕緣層14，例如本例中可使用具有較佳非等向性的 電漿蝕刻方式，即可完成閘極區域之定義。 接著參見第三圖，之後摻雜基材10中、未被閉極區域 覆蓋之部分，以形成延伸源汲極接面30於基材之内，為 形成極淺的延伸源汲極接面3 0，在較佳實施例之办 1〜τ，可利 用電漿擴散（或稱電漿浸入， plasma immersion)、或是低处 9 離子植入的方式直接形成延伸源汲極接面30於基材1〇之 内。以形成nMOSFET而言，電漿擴散的製程，可使基材^ 曝露於具有磷離子或砷離子的電漿環境之中，而使所需的離 入進入基材10未被覆蓋的表面處。 而若使用低能量離子植入的製程，可直接楂入碟離子 本紙張尺度適用中國國家標準（CNS)A4規格（210 297公釐） {請先閱讀.背面之-意事項再填寫本頁>It II ί * ---- I I --— — — — — — — It I i Please read the legal matters before filling out this page) ^ 43928 9 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. Description of the invention () CVD) or electro-enhanced chemical vapor deposition (PECVD), the thickness of which is between 300 angstroms and 1500 angstroms. Refer to the 'removed portion of the first dielectric layer [8, the first stone layer 16, and the gate insulating layer 1 4]' shown in the second figure to define a gate region. The formation of the gate region can use a general patterning process, that is, a series of steps including a lithography process and a engraving process. Generally, the process of defining the gate region may include the following steps: firstly forming a photoresist layer 20 on the first dielectric layer; then using exposure and development of a photolithographic process order to define a gate pattern on the photoresist layer 2 And using the photoresist layer 20 as a mask to etch the first dielectric layer 18, the first-middle layer 16, and the gate insulating layer 14, for example, a plasma etching having a better anisotropy may be used in this example. Method to complete the definition of the gate area. Next, referring to the third figure, the portion of the substrate 10 that is not covered by the closed electrode region is then doped to form an extended source drain junction 30 within the substrate to form a very shallow extended source drain junction 3 0, in the preferred embodiment, 1 to τ, the plasma source immersion (or plasma immersion), or low-level 9 ion implantation can be used to directly form the extended source drain junction 30 on the base.材 1〇 Within. For the formation of nMOSFETs, the plasma diffusion process can expose the substrate ^ to a plasma environment with phosphorus ions or arsenic ions, so that the required ion can enter the uncovered surface of the substrate 10. If you use a low-energy ion implantation process, you can directly insert the ions into the dish. The paper size applies the Chinese National Standard (CNS) A4 specification (210 297 mm) {Please read first. Please note on the back-please fill out this page >
- *---—I — I ^ I I 丨 I I I I HI43 A7 B7 五、發明説明（ 或砷離子，以本例而言，其植入之能量約為0 .丨至5 K e V， 所形成之#雜濃度約為 1E13至 lE15ions/cm2。，以形成 pMOSFETs的應用而言，上述中電漿擴散的製程及低能量離 子植入的製程令的磷離子或砷離子，則可使用硼離子加以取 代之》 在延伸源汲極接面30形成之後，可選擇性的加入一形 成第二介電層22於基材10上之步驟，利用熱製程的方式、 由基材1 0及閘極區域之側壁上成長第二介電層22 ;本例令 之介電層2 2可使用氮氧化矽層或是氧化矽層，氧化矽層係 於含氧（形成氮氧化矽時，可進一步加入含氮氣體）之環境 辛，由基材丨0及第一 夕層16加熱成長而成*並形成於基材 10上、以及第一矽層16與閘極絕緣層1 4的側壁上，此第 二介電層22之厚度約為5埃至100埃。藉由熱成長方式所 形成之第二介電層 22*可修補蝕刻對基材表面的破壞，並 避免閘極絕緣層受到其他區域所摻雜離子的污染。 請 先 閱 讀 背 ιέ 之 注 '意 事 項 再 填 % 本 頁 訂 經濟部智慧財產局員工消費合作社印製 在此一形成氧化矽層或氬氧化矽層的較佳實施例之 ψ，第二介電層22的形成，可用以改善基材10之表面，利 用消耗部分表面的矽材質來修復基材I 〇於閘極區域定義時 因蝕刻所產生的缺陷。 參見第四圖所示，之後並形成未摻雜之侧壁結構24於 閘極區域之側壁上，本例中未摻雜之側壁結構24可為未摻 Ϊ0 本紙浪尺度適用中國國家標隼（CNS ) Α4規格（210Χ297公釐） A7 B7 五、發明説明（） 雜之氡化矽間隙壁，並可利用沈積並回蝕氧化矽層的方式加 以形成，在氧化矽層回蝕的過程之中，氮化矽的第一介電層 1 8即可做為一良好的蝕刻_止層，防止其他的閘極區域因 鞋刻而受到破壞。 參見第五圖所示，然後去除第一介電層18，並形成第 二矽層26於基材10曝露的表面上及第一矽層16上；本例 中第二<5夕層26可為一未搀雜的多晶5夕層，此一未摻雜的石夕 層可利用一化學氣相沈積法形成，以最佳實施例而言，可使 用一選擇性的屋晶沈積（selective epitaxial deposition)方式 形成第二矽層2 6，例如應用一高真空度的化學氣相沈積法 (ultra-high vacuum chemical vapor deposition; UHVCVD)， 而可選擇性的僅形成矽層於具有矽材質的表面上，也就是第 二矽層26的表面上，而不需使用額外的微影製程及蝕刻製 程。 參見第五圖所示，在第二矽層26形成之後，即接著對 基材10進行離子植入的製程，以摻雜所需的離子至第二矽 層26内，以做為後續製程中擴散進入基材10之離子來源 經濟部智慧財產局員工消費合作社印製 2 8，而形成源汲極接面於未被閘極區域及側壁結構24覆蓋 之基材10内，並同時摻雜藉由後續熱製程中第二矽層26 内摻雜離子的向下擴散，使原本未具摻雜或是僅具低摻雜的 第一矽層1 8的摻雜濃度增加，提昇其做為閘極的導電性。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 Μ _Β7 五、發明説明（） 本例中的離子摻雜製程可應用離子植入的製程，以 nMOSFETs的應用而言，可植入較高劑量的砷或磷離子進入 第二矽層2 6 ’以藉由後續之熱擴散製程形成源汲極接面， 在較佳實施例裡，離子佈植的能量約i 〇 _丨5 〇 k e V，以形成 劑量約5E14至5E16 i〇ns/cm2之間的源汲極接面；以形成 pMOSFETs的應用而言’則可使用蝴離子來取代上述的珅或 磷離子。 在未進行矽化金屬製程的實施例之中，可於上述步驟完 成後進行後續的熱製程’以藉由摻雜離子的擴散形成延伸源 汲極接面30及源汲極接面28，如第六圖所示。 參考第七圖所示’在電晶體的主要架構完成之後，可 進行一系列的製程，以進行矽化金屬於閘極及源./汲極區域 之上。矽化金屬製程一般可包含數個步驟，首先形成金屬層 於基材10上’一般可應用於形成矽化金屬化合物之金屬材 質可包括鈦、站、錄、鎮、及始等；並接著進行熱製程，於 高溫下使金眉層與其下方的矽材料反應，以形成矽化金屬層 32於第二石夕層26上，也就是閘極及接面區所在的區域。 以較隹實施例而言’熱製程可使用快速熱處理製程 (rapid therma丨 processing; RTP)，其溫度約為 600°C 至 11〇〇 ΐ之間’在熱製程的作用之下，會同時擴散並活化延伸源汲 極接面30内之離子，並擴散第二矽層26内之離子、以形成 本紙张尺度適用中國固家樣率（CNS) A4規格U10X297公釐） ^^^1- ^^^1 <|^1 m m —i z/ ^^^1 ^^^1 ml 1^1 nn m ，^-* {請先閲讀f面之注't事項再填寫本頁) 陷43 92 8 A7 B7 五、發明説明（ 源汲極接面2 8於未被閘極區域及惻壁結構2 4復蓋之基材 10内、並使摻雜離子向下擴散至第—矽層16。最後龙去除 未反應成矽化金屬層之殘餘金屬，以一般矽化金屬製程的應 用而言’可使用溼蝕刻的方式，利用如包含氨水、水及過氧 化氫等的蝕刻溶液，去除如鈦等的殘餘金屬，而留下如第七 圖中之矽化金屬層32。 藉由以上之方法，即可完成本發明中具有提昇之源汲 極區的金氧半場效電晶體（MOSFET)的結構。並可進一步對 半導體基材10進行金屬連線製程，以形成對閘極及接面區 的電性連接，一般可包含一層或多層的連線層。金屬化導線 連接製程可包含一連串如形成接觸窗、填入導體層、以及平 坦化等的製程。 I n^i - - - - - B II — ^^^1 —-^-- —ι^ϋ ^^1 m (锖先閱讀e面之注意事項再填寫本f ) 經濟部智慧財產局員工消費合作杜印製 右以形成較佳電性的要求而言，本發明可進一步利用 上述自行對準的矽化金屬製程（se丨f-aHgned sihcide)形成矽 化金屬層；利用矽化金屬的製程’可降低接觸阻值，提昇連 線的導電性，且由於本發明中之矽化金屬層係形成於第二矽 層20上，其形成或是矽化時不會消耗泺汲極區2 8處的基材 10，因此可避免源汲極區28的通道受到影響。£夕化金屬製 程之細節步驟為此領域中所熟知之技術，在此即不多做介 紹。 本發明中之電晶體’可藉由電漿擴散或是低能量離子 本紙佚尺度適用中國國家標準（CNS > A4規格（210 X 297公釐y ,) A7 B7 ^请#員明示^年>月^日所-^之 經濟部智蒽財產局員工消资合作社印製 #立本有無變更實質内容是否准予修正。 五、發明説明（）-* ---— I — I ^ II 丨 IIII HI43 A7 B7 V. Description of the invention (or arsenic ion, in this case, the implanted energy is about 0. 丨 5 K e V, #Miscellaneous concentration is about 1E13 to 1E15ions / cm2. For the application of forming pMOSFETs, the above-mentioned plasma diffusion process and low-energy ion implantation process can be used to replace phosphorus or arsenic ions with boron ions. After the extension source-drain junction 30 is formed, a step of forming a second dielectric layer 22 on the substrate 10 can be optionally added, and the substrate 10 and the gate region can be formed by a thermal process. A second dielectric layer 22 is grown on the sidewall; the dielectric layer 22 used in this example can be a silicon oxynitride layer or a silicon oxide layer. The silicon oxide layer is based on oxygen (to form silicon oxynitride, nitrogen can be further added). Gas) environment, formed by heating and growing from the substrate 丨 0 and the first night layer 16 * and formed on the substrate 10, and on the side walls of the first silicon layer 16 and the gate insulating layer 14, this second The thickness of the dielectric layer 22 is about 5 Angstroms to 100 Angstroms. The second dielectric layer 22 formed by thermal growth can repair the etch Carve damage to the surface of the substrate, and avoid contamination of the gate insulation layer with doped ions in other areas. Please read the note below and then fill in% This page is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In this preferred embodiment of forming a silicon oxide layer or an argon silicon oxide layer, the formation of the second dielectric layer 22 can be used to improve the surface of the substrate 10, and the silicon material that consumes part of the surface is used to repair the substrate I. 〇 Defects due to etching during the definition of the gate region. See the fourth figure, and then an undoped sidewall structure 24 is formed on the sidewall of the gate region. In this example, the undoped sidewall structure 24 is formed. Can be non-doped. This paper scale is applicable to Chinese National Standards (CNS) A4 specifications (210 × 297 mm) A7 B7 5. Description of the invention () Hybrid silicon oxide spacers, and can be used to deposit and etch back the silicon oxide layer. In the process of etch-back of the silicon oxide layer, the first dielectric layer 18 of silicon nitride can be used as a good etching stop layer to prevent other gate regions from being damaged due to shoe engraving. See figure 5 The first dielectric layer 18 is then removed, and a second silicon layer 26 is formed on the exposed surface of the substrate 10 and the first silicon layer 16; in this example, the second < 5x layer 26 may be unfinished A heterogeneous polycrystalline silicon layer. This undoped stone layer can be formed by a chemical vapor deposition method. In a preferred embodiment, a selective epitaxial deposition method can be used. To form the second silicon layer 26, for example, an ultra-high vacuum chemical vapor deposition (UHVCVD) method is applied, and only a silicon layer can be selectively formed on a surface having a silicon material, and It is on the surface of the second silicon layer 26 without using an additional lithography process and an etching process. As shown in FIG. 5, after the second silicon layer 26 is formed, the substrate 10 is then subjected to an ion implantation process to dope the required ions into the second silicon layer 26 as a subsequent process. Diffusion into the source of the ions of the substrate 10 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics and printed 2 8 to form a source-drain junction in the substrate 10 that is not covered by the gate region and the sidewall structure 24, and simultaneously doped The subsequent diffusion of doped ions in the second silicon layer 26 in the subsequent thermal process increases the doping concentration of the first silicon layer 18, which is not doped or only lowly doped, and enhances it as a gate Extremely conductive. This paper size applies Chinese National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _B7 V. Description of the invention () The ion doping process in this example can be applied to the ion implantation process For the application of nMOSFETs, a higher dose of arsenic or phosphorus ions can be implanted into the second silicon layer 26 'to form a source-drain junction through a subsequent thermal diffusion process. In a preferred embodiment, the ions The implanted energy is about i 〇_ 丨 50 ke V to form a source-drain junction between about 5E14 to 5E16 ions / cm2; for applications that form pMOSFETs, butterfly ions can be used instead The aforementioned rhenium or phosphorus ions. In the embodiment where the metal silicide process is not performed, the subsequent thermal process can be performed after the above steps are completed to form the extended source-drain junction 30 and the source-drain junction 28 by diffusion of doped ions, as described in the first paragraph. Figure six. Referring to the seventh figure, after the main structure of the transistor is completed, a series of processes can be performed to perform silicided metal on the gate and source / drain regions. The silicided metal process may generally include several steps. First, a metal layer is formed on the substrate 10. The metal materials generally applicable to the formation of silicided metal compounds may include titanium, metal, silicon, metal, and silicon; and then a thermal process is performed. The gold eyebrow layer is reacted with the silicon material below it at a high temperature to form a silicided metal layer 32 on the second stone layer 26, which is the area where the gate electrode and the junction area are located. In a comparative example, 'the thermal process can use rapid therma processing (RTP), the temperature of which is between about 600 ° C and 1100 ° C', under the effect of the thermal process, it will diffuse at the same time And activate the ions in the drain source junction 30 of the extended source, and diffuse the ions in the second silicon layer 26 to form the paper size applicable to the Chinese solid sample rate (CNS) A4 specification U10X297 mm) ^^^ 1- ^ ^^ 1 < | ^ 1 mm —iz / ^^^ 1 ^^^ 1 ml 1 ^ 1 nn m, ^-* {Please read the note on the f side before filling in this page) trap 43 92 8 A7 B7 V. Description of the invention (source-drain junction 2 8 is in the substrate 10 not covered by the gate region and the wall structure 2 4, and the doped ions are diffused downward to the first silicon layer 16. Finally Long removes the remaining metal that has not reacted to the silicided metal layer. In the application of the general silicidation process, 'wet etching can be used to remove residues such as titanium using an etching solution containing ammonia, water, hydrogen peroxide, etc. Metal, leaving the silicided metal layer 32 as shown in the seventh figure. By the above method, the source-drain region having the improvement in the present invention can be completed Metal oxide half field effect transistor (MOSFET) structure. Further, a metal connection process can be performed on the semiconductor substrate 10 to form an electrical connection to the gate electrode and the junction area, which generally includes one or more layers of connection The metallization wire connection process may include a series of processes such as forming a contact window, filling a conductor layer, and planarizing, etc. I n ^ i-----B II — ^^^ 1 —- ^-—ι ^ ϋ ^^ 1 m (锖 Please read the precautions on the e side before filling in this f) The consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed the right to form a better electrical requirement. The present invention can further use the above The aligned silicided metal process (se 丨 f-aHgned sihcide) forms the silicided metal layer; the use of the silicided metal process can reduce the contact resistance value and improve the conductivity of the connection, and because the silicided metal layer in the present invention is formed on On the second silicon layer 20, the substrate 10 at the 泺 -drain regions 28 is not consumed during formation or silicidation, so that the channel of the source-drain region 28 can be prevented from being affected. The detailed steps of the metallization process are as follows: Not many technologies are well known in this field Introduction. The transistor in the present invention can be applied to the national standard (CNS > A4 specification (210 X 297 mm y,) A7 B7 ^ Please # 员 明示 ^ by plasma diffusion or low energy ion paper size) Year > Month ^ Date-^ Printed by the staff of the Ministry of Economic Affairs, Zhithuan Property Bureau, Consumer Capital Cooperatives # 立 本 Whether the substance of the change is allowed to be amended. V. Description of the invention ()
植入形成極淺且宽度均一的源汲極區1並藉由上述製程提 供提昇的源汲極區，可消除傳統結構及製程中的短通道效 應，並利用一複合層之堆疊閘極結構，可避免離子入侵閘 極氧化矽層或氮氧化矽所造成的元件退化問題。因此可消 除傳統製程應用於小尺寸元件中，因通道縮減所面臨的諸 多問題，減少因通道及閘極寬度縮短的負面效果，提供更 好的元件操作特性及可靠度。 本發明以一較佳實施例說明如上，僅用於藉以幫助了 解本發明之實施，非用以限定本發明之精神，而熟悉此領 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 範圍内，當可作些許更動潤飾及等同之變化替換，其專利 保護範圍當視後附之申請專利^範圍及其等同領域而定。 圖號標示說明： 10 基 材 12 隔 離 區 14 閘 極 絕 緣 層 16 苐 一 矽 層 18 第 一 介 電 層 20 光 阻 層 22 第 二 介 電 層 24 侧 壁 結 構 26 苐 二 矽 層 28 離 子 來 源 30 汲 極 接 面 32 矽 化 金 屬層 14 本紙張尺度通用中國因家橾準（CNS ) A4見格（2!0X297公釐） (請先閲讀背.面之注意事項再填寫本育)Implanting to form a very shallow and uniform source-drain region 1 and providing an enhanced source-drain region through the above process can eliminate the traditional structure and short channel effect in the process, and use a composite layer stacked gate structure, Prevents device degradation caused by ions invading the gate silicon oxide layer or silicon oxynitride. Therefore, the traditional process applied to small-sized components can be eliminated, many problems faced by channel reduction, the negative effects of shortening the channel and gate width can be reduced, and better component operation characteristics and reliability can be provided. The present invention is described above with a preferred embodiment, and is only used to help understand the implementation of the present invention, and is not intended to limit the spirit of the present invention. Those skilled in the art will not depart from the present invention after understanding the spirit of the present invention. Within the scope of the spirit, when it can be slightly modified and replaced with equivalent changes, the scope of patent protection depends on the scope of the attached patent application and its equivalent fields. The drawing indicates: 10 substrate 12 isolation area 14 gate insulating layer 16 silicon layer 18 first dielectric layer 20 photoresist layer 22 second dielectric layer 24 sidewall structure 26 silicon layer 28 ion source 30 Drain junction 32 Silicided metal layer 14 The paper size is in accordance with China Standards (CNS) A4 (2! 0X297 mm) (Please read the notes on the back and fill in this education first)
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