TW488031B - A tunable sidewall spacer process for cmos integrated circuits - Google Patents
A tunable sidewall spacer process for cmos integrated circuits Download PDFInfo
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- TW488031B TW488031B TW089107690A TW89107690A TW488031B TW 488031 B TW488031 B TW 488031B TW 089107690 A TW089107690 A TW 089107690A TW 89107690 A TW89107690 A TW 89107690A TW 488031 B TW488031 B TW 488031B
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 20
- 238000002513 implantation Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 230000000873 masking effect Effects 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 239000007943 implant Substances 0.000 abstract description 8
- 239000010408 film Substances 0.000 description 11
- 239000002019 doping agent Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910001922 gold oxide Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
488031 五、發明說明（1) 一·〜— - 發明領域 本發明大體i有關金氧化半導體場效電 其有關於互補式金氧化半導體積體電路中形^ :顆方法，以使該_及聰電晶體兩者 發明背景 隨著互補式金氡化半導體積體電路之臨界 串聯電阻對於電晶體性能之限制曰漸重要。串要 係來自該電晶體中以下三種來源：經輕 9 ^ ，、接觸及線路電阻、及通道電阻。降低雜二極= 必而之LDD結構係為該電晶體中整體串聯電阻之. :太i聯：：對於電晶體驅動電流(離子)之影響係為該電 机本身之函放:NM0S電晶體之較高電導係數使其對於串聯 電阻效應之感党強於Ρ Μ 〇 S電晶體。 目則，該LDD結構係使用侧壁間隔物及自動對正離子植 入形成。形成該閘極結構之後，一般係進行自動對正植 入，以於與該電晶體閘極相鄰之區域中形成該ldd結構。 N-型摻雜劑物質植入NM〇s電晶體中，而p—型摻雜劑物質係 植入PM0S電晶體中。於此ldd植入之後，形成厚氮化矽 層’經各向異性蝕刻，以於與該NM〇s &PM〇s電晶體之閘極 =鄰處形成側壁結構。之後進行源極及汲極植入，以於兩 電晶體類型中形成經高度摻雜之源極及汲極區域。於該經 植入物質之退火期間，擴散將使該LDD區域於該閘極區域 底下位移。因為該LDD及源極及汲極區域_使用硼，故該488031 V. Description of the invention (1) I. ~~-Field of the invention The present invention generally relates to field-effect electricity of gold oxide semiconductors, which relates to the shape of a complementary gold oxide semiconductor integrated circuit ^: a method to make the _ and Cong BACKGROUND OF THE INVENTION Both transistors are becoming increasingly important as the critical series resistance of complementary metallized semiconductor integrated circuits limits the performance of transistors. The string is derived from the following three sources in the transistor: the light source, the contact and line resistance, and the channel resistance. Reducing heterodipole = The necessary LDD structure is the overall series resistance in the transistor.: Tai-lian :: The effect on the transistor drive current (ion) is the function of the motor itself: NM0S transistor The higher conductivity makes it more sensitive to series resistance effects than PMOS transistors. For this purpose, the LDD structure was formed using sidewall spacers and automatic counterion implantation. After the gate structure is formed, automatic alignment is generally performed to form the ldd structure in a region adjacent to the transistor gate. The N-type dopant substance is implanted in the NMOS transistor, and the p-type dopant substance is implanted in the PMOS transistor. After the ldd implantation, a thick silicon nitride layer is formed anisotropically etched to form a sidewall structure adjacent to the gate of the NMOS and PMOS transistors. Source and drain implants are then performed to form highly doped source and drain regions in the two transistor types. During the annealing of the implanted material, diffusion will displace the LDD region under the gate region. Because the LDD and source and drain regions _ use boron, so the
488031 五、發明說明（2) PMOS電晶體之擴散較大。 該電晶體之串聯電阻的降低可 午儆J糟者降低該側壁厚度而達 成，以縮短該LDD區域。麸而，a你μ ▲ A a门乂士 ^…、而此種縮短使得該PMOS電晶 肚中因為來自該源極汲極區域之擴散而致該ldd區域越 界。導致電晶體漏流增加，而使得該電路無法操作。因此 需要-種調整供該NM0S及PM0S電晶體使用之側壁間隔物之 方法，而不增加該程序之成本及複雜性。 發明概逢 本發明係為一種於互補式金氧牝半導體積體電路中形成 側壁結構之方法，用以使該NM〇s &pM〇s電晶體之性能最佳 化。該方法包括步驟：於一半導體基材之n—型區域上形成 二PM0S電晶體閘極結構；於該半導體基材之p—型區域上形 成一NM0S電晶體閘極結構；於緊鄰於該NM〇s電晶體閘極結 構及该PM0S電晶體閘極結構處形成側壁結構；及蝕刻與該 NM0S電晶體閘極結構相鄰之側壁結構，使得與該NM〇s電晶 體問極結構相鄰之側壁結構寬度小於與該pMQS電晶體閘極 結構相鄰之側壁結構寬度。該側壁之蝕刻係使用一各向異 性姓刻進行，而該側壁結構係選自氮化矽、二氧化矽、及 氮氧化碎之材料。 單說明 圖中： 圖1 A - 1 C係為本發明具體實例之剖面圖。 圖中使用共同之參考編號以表示相同或相似特徵。該特 徵未依比例繪製，而僅供說明。488031 V. Description of the invention (2) The diffusion of PMOS transistor is large. The reduction of the series resistance of the transistor can be achieved by reducing the thickness of the sidewall to shorten the LDD region. In addition, a u μ ▲ A a gatekeeper ^ ..., and this shortening causes the PMOS transistor to cross the boundary of the ldd region due to diffusion from the source drain region. This results in an increase in transistor leakage, making the circuit inoperable. Therefore, a method of adjusting the sidewall spacers for the NMOS and PMOS transistors is needed without increasing the cost and complexity of the procedure. Summary of the Invention The present invention is a method for forming a sidewall structure in a complementary metal-oxide semiconductor integrated circuit to optimize the performance of the NMOS and pMos transistors. The method includes the steps of: forming a two PMOS transistor gate structure on an n-type region of a semiconductor substrate; forming a NMOS transistor gate structure on a p-type region of the semiconductor substrate; 〇s transistor gate structure and a sidewall structure formed at the PM0S transistor gate structure; and etching the sidewall structure adjacent to the NM0S transistor gate structure to make it adjacent to the NM0s transistor gate structure The width of the sidewall structure is smaller than the width of the sidewall structure adjacent to the pMQS transistor gate structure. The sidewall etching is performed using an anisotropic engraving, and the sidewall structure is selected from the group consisting of silicon nitride, silicon dioxide, and oxynitride. In the drawings: Figures 1A-1C are sectional views of specific examples of the present invention. Common reference numbers are used in the drawings to indicate the same or similar features. This feature is not drawn to scale and is for illustration only.
五、發明說明（3) 發明詳述 雖然本發明以下描诚你& ’、十對圖1 A - 1 C進行考岸，>f曰本略 明可使用於任何半導艚奘罢仏 ]可恩仏尽署 ΜΜ〇ς » PMOQ ^ 、置、…構。本發明之方法針對於 Ν Μ 0 S及Ρ Μ 0 S电晶γ目,丨jg^曰曰 $ # 4 β & ^ 側壁間隔物寬度之調整提供解答，而 不增加私序複雜性。 叩 麥=圖1 A，提供第—電導係數類型之基材1 〇，含有第二 電導係數類型20區域。本發明具體實例中，該第一電導； 數類型係為P-型，而第二電導係數類型係為卜型。閘極： 電質30係形成於該基材1〇及2〇兩者之部分區域上。該 介電其30可包括氧化物、&長晶以〇2、氣化物、氛氧化 物、或其任何組合物，較佳係為}至丨〇毫微米大小之厚 度。含矽材料層（經圖型化及蝕刻以形成閘極結構4 〇 )係形 成於閘極介電質3 0上。此種含矽材料較佳係包括多晶矽 (’’多晶”或π多晶矽”），但可包括磊晶矽或任何其他半導體 材料。該基材中含有絕緣結構50。此等絕緣結構可包括氧 化物或部分其他絕緣體。絕緣結構5 0之目的係使該基材上 之主動型裝置彼此隔離。 就圖1 Α至1 C所示之本發明具體實例而言，該基材丨〇係為 p-型，而井洞20係為η-型。NMOS電晶體係於1 〇中製造，而 PMOS電晶體係於區域20中。界定該閘極結構4〇，於該基材 1 0上形成一光阻劑層。使用微影術，將該抗焊劑圖型化並 蝕刻，產生抗焊劑覆蓋該PMOS電晶體之區域。進行毯覆槽 式Ρ-型植入，之後毯覆槽式η-型LDD植入，產生ρ-型摻雜 曲線60及η -型摻雜曲線70。於目前積體電路技術中，槽式V. Description of the invention (3) Detailed description of the invention Although the following description of the present invention & ', ten pairs of Figures 1 A-1 C test, > f said slightly can be used for any semi-conductor. ] 可 恩 仏 定 署 ＭＭ〇ς »PMOQ ^, set, ... structure. The method of the present invention provides a solution for the adjustment of the NM 0 S and PM 0 S crystals, and the adjustment of the width of the sidewall spacers without increasing the complexity of the private sequence.叩 Mic = Figure 1 A, providing the first conductivity type substrate 10, containing the second conductivity type 20 area. In a specific example of the present invention, the first conductivity type is P-type, and the second conductivity coefficient type is Bu type. Gate: The capacitor 30 is formed on a part of both the substrates 10 and 20. The dielectric 30 may include oxides, < crystals < 2 >, gaseous compounds, atmospheric oxides, or any combination thereof, preferably having a thickness in the range of} to 0 nm. A silicon-containing material layer (patterned and etched to form the gate structure 40) is formed on the gate dielectric 30. Such silicon-containing materials preferably include polycrystalline silicon ('' polycrystalline 'or π polycrystalline silicon'), but may include epitaxial silicon or any other semiconductor material. The substrate contains an insulating structure 50. These insulating structures may include oxides or some other insulators. The purpose of the insulating structure 50 is to isolate the active devices on the substrate from each other. For the specific example of the present invention shown in FIGS. 1A to 1C, the substrate is p-type, and the well 20 is η-type. The NMOS transistor system is manufactured in 10, and the PMOS transistor system is in region 20. The gate structure 40 is defined, and a photoresist layer is formed on the substrate 10. Using lithography, the solder resist is patterned and etched to produce areas where the solder resist covers the PMOS transistor. A blanket-covered slot-type P-type implantation was performed, and then a blanket-covered slot-type η-type LDD was implanted to produce a p-type doping curve 60 and an η-type doping curve 70. In the current integrated circuit technology, the slot type
丄 五、發明說明（4) :ί體：ί :如ί入物’用以降低電晶體閘極短長度對於電 於臨限電壓。特定電曰雕 ^槽式植入物之衫響不限 電晶體汲極延伸之摻^ ^ ί生之槽式植入物通常產生超過 ΛΒ . BF? Γ 七雜曲線。該卜型槽式植入物之種類可 植入物之大小部分：任何其他適當之n-型摻雜劑。 植入之前進行。士成、兮心1 而該LDD植入係於該槽式 任何所需之後續：i二 式植入、該n-型⑽植入及 劑。去除該光阻劑之後，了上：標準處理技術去除光阻 诜夕—隹—k 曼可於形成該PM0S電晶體之LDD區 域之刖進灯任何數量之程序。 $形成PMOS LDD區域，光阻劑層形成於該基材1()上經 圖至化及蝕」以覆盍或罩蓋該NM0S電晶體。進行毯覆槽 式η-型植人及後續之毯覆p_mDD植人，以產生型捧曰 雜：線80，及該p-型摻雜曲線9〇。該^型槽式植入之種類 可為As、P、Sb或任付i杨、备Λ1 ΙΑ 〇 ^P"^DD Ga、In或任何其他適當之ρ —型摻 雜劑二植=之次序部分任意，而該LDD植入係於該槽式植 入之4進行凡成植入及任何其他必要程序之後，於該基 材上形成一側壁膜10G。去除該光阻劑，於該閘極結構4〇 及基材10表面上形成一側壁膜1〇〇，以形成供該閘極結構 40使用，側壁結構。此種側壁膜可包括氮化矽、氮氧化 石夕、一氧化石夕、或任何具有相同性質之薄膜。 圖1B出示在各向異性側壁蝕刻程序之後的圖iA結構。該丄 V. Description of the invention (4): ί body: ί: such as ί 入 物 ’is used to reduce the short length of the transistor gate to the threshold voltage. The specific sound of the grooved implants is not limited. The doped extension of the transistor drain ^ ^ The grooved implants usually produce more than ΛB. BF? Γ seven miscellaneous curves. The type of Bu-groove implant can be the size of the implant: any other suitable n-type dopant. Perform before implantation. Shicheng, Xixin1, and the LDD implantation is in any required follow-up of the trough: i-type implantation, the n-type iliac implantation and agent. After removing the photoresist, the following is done: standard processing technology to remove the photoresistance 诜 诜 — 隹 —k mann can enter any number of procedures during the formation of the LDD region of the PMOS transistor. A PMOS LDD region is formed, and a photoresist layer is formed on the substrate 1 () to be etched and etched to cover or cover the NMOS transistor. Carpet-covered trough-type η-type implantation and subsequent blanket-covered p_mDD implantation were performed to produce a pattern impurity: line 80, and the p-type doping curve 90. The type of the ^ -type groove implant may be As, P, Sb, or any of Yang, Bei Λ1 ΙΑ 〇 ^ P " ^ DD Ga, In, or any other appropriate ρ-type dopant II plant = order Partially arbitrary, and the LDD implantation is performed after the trough implantation 4 and all other necessary procedures to form a sidewall film 10G on the substrate. After removing the photoresist, a side wall film 100 is formed on the gate structure 40 and the surface of the substrate 10 to form a side wall structure for the gate structure 40. Such a sidewall film may include silicon nitride, oxynitride, oxide, or any thin film having the same properties. FIG. 1B shows the structure of FIG. IA after the anisotropic sidewall etching process. The
488031 五、發明說明（5) -一' - NM0S電晶體1 1Q及該pM〇s電晶體丨2()之側壁結構係使用相同 餘刻方法同時地形成。此等原始側壁結構具有第一寬度 1 〇 1 ’如圖1 B所示。於其中該側壁膜係為氮化矽之具體實 ，:’使用二階蝕刻方法以形成該側壁。第一個步驟係為 疋^之氮化矽電漿蝕刻，基本壓力係為丨〇 〇 — 3 〇 〇 mT、能量 位準1 0 0 -30 0瓦、間隙l 5厘米、S{?6係為12〇 —2〇〇 sccm、488031 V. Description of the invention (5) -One '-The NM0S transistor 1 1Q and the pM0s transistor 2 () side wall structure are formed simultaneously using the same method. These original sidewall structures have a first width 1 0 1 ′ as shown in FIG. 1B. In the embodiment where the sidewall film is silicon nitride, a second-order etching method is used to form the sidewall. The first step is the silicon nitride plasma etching of 疋 ^, the basic pressure is 丨 00—300mT, the energy level is 100-30 watts, the gap is 15cm, and the S {? 6 series 12-200 sccm,
He為5 0 -80 sccm、及6托耳之He反壓。此種蝕刻方法之氮 化矽、矽、二氧化矽選擇性係約1比1。此方法係用以蝕刻、 大部分之側壁膜。該側壁蝕刻方法之第二個步唧係為高選 擇性氮化物姓刻方法。此方法包括基本壓力係為4 〇 〇 _ 8 〇 〇 111丁、能量位準1〇〇- 30 0瓦、間隙1〇厘米、31?6係為12〇-2〇() seem、HBr為5-3 0 seem、及6托耳之He反壓。此蝕刻方法 之氮化夕、矽、二氧化矽選擇性係約4比1。側壁形成及任 何其他必要程序步驟之後，形成該源極汲極區域。此方法 一般係包括兩個罩蓋步驟，使用光阻劑作為罩蓋材料。於 該第一罩蓋步驟中，形成光阻劑並圖型化丨3 〇，以覆蓋該 NMOS電晶體及該PMOS電晶體中由離子植入所形成之源極汲 極區域。產生圖1B所示之p-型摻雜曲線14〇。該？_型源極 沒極植入之種類有β、Ga、In或任何其他適當之p -型 掺雜劑。 於第二個罩蓋步驟中，去除光阻劑膜1 3 〇，形成新的光 阻劑膜，經圖型化150以覆蓋該pm〇s電晶體，如圖ic所 示。進行附加之側壁蝕刻，存在該抗焊劑膜丨5 〇以縮小該 NMOS側壁110之宽度，同時不影響該PM〇N側壁12〇。該題⑽He is a He back pressure of 5 0 -80 sccm and 6 Torr. The silicon nitride, silicon, and silicon dioxide selectivity of this etching method is about 1: 1. This method is used to etch most of the sidewall film. The second step of the sidewall etching method is a highly selective nitride lasting method. This method includes a basic pressure system of 400-800 mm, an energy level of 100-300 watts, a gap of 10 cm, a 31-6 series of 12-20-2 () seem, and HBr of 5 -3 0 seem, and He back pressure of 6 Torr. In this etching method, the selectivity of nitride, silicon, and silicon dioxide is about 4 to 1. After sidewall formation and any other necessary process steps, the source-drain region is formed. This method generally involves two cover steps, using a photoresist as the cover material. In the first capping step, a photoresist is formed and patterned to cover the source and drain regions of the NMOS transistor and the PMOS transistor formed by ion implantation. A p-type doping curve 14 shown in FIG. 1B is generated. What? Types of _-type implants are β, Ga, In or any other suitable p-type dopants. In the second capping step, the photoresist film 130 is removed to form a new photoresist film, and patterned 150 to cover the pMOS transistor, as shown in FIG. Additional sidewall etching is performed, and the solder resist film is present to reduce the width of the NMOS sidewall 110 without affecting the PMON sidewall 120. The title
O:\63\63583.ptd 第9頁 488031 五、發明說明（6) _ 電晶體102之新寬度係小於該PM〇s電晶體之側 此種蝕刻應相對地各向同性，對於該晶圓上一 ^度ιοί。 二氧化矽表面具有高度選擇性。其中該側辟、路之矽及 體實例中，適當之蝕刻方法係為電漿蝕刻：：矽，具 係為 1 2 0 -2 0 0 sccPHBrW-30 sccm、及6 托耳之 ^反 壓H虫刻方法之氮化石夕、石夕、二氧化石夕選擇性係約4比 1。於該選擇性NMOS側壁蝕刻之後，使用離子植入形成該 NM〇f電晶體之源極汲極區域。形成—型摻雜曲線16〇係 出不於圖1C中。該η-型源極汲極植入之種類可為As、p、 Sb或任何其他適當之n—型摻雜劑。該CM〇s積體電路可使用 必要之處理步驟完成。藉著使該NM〇 s電晶體之側壁結構 102寬度較該PM0S電晶體1〇1側壁結構縮小，NM〇s LDD所產 生之串聯電阻可在不影影該PM〇s電晶體之電晶體漏流的情 況下降低。 雖然已參照例示具體實例描述本發明，但此描述不構成 限制。熟習此技藝者可在參照本發明描述之後明暸例示具 體實例及本發明其他具體實例之各種修飾及組合。因此， 所附之申請專利範圍係涵蓋任何該種修飾及具體實例。O: \ 63 \ 63583.ptd Page 9 488031 V. Description of the invention (6) _ The new width of transistor 102 is smaller than the side of the PM0s transistor. This etching should be relatively isotropic. For the wafer Previous ^ 度 ιοί. The surface of silicon dioxide is highly selective. Among the examples of the side and road silicon and body, the appropriate etching method is plasma etching: silicon, with 1 2 0-2 0 0 sccPHBrW-30 sccm, and 6 Torr back pressure H The selectivity of the worm-carved method is about 4 to 1. After the selective NMOS sidewall etching, ion source implantation is used to form the source-drain region of the NMOf transistor. The formation of a -type doping curve 160 is not shown in Fig. 1C. The type of the n-type source-drain implantation may be As, p, Sb, or any other suitable n-type dopant. The CMOS integrated circuit can be completed using necessary processing steps. By making the width of the sidewall structure 102 of the NMOS transistor smaller than that of the PM0S transistor 101, the series resistance generated by the NMOS transistor can not affect the transistor leakage of the PMMOS transistor. In case of streaming. Although the present invention has been described with reference to specific examples, this description does not constitute a limitation. Those skilled in the art can clearly illustrate various modifications and combinations of specific examples and other specific examples of the present invention after referring to the description of the present invention. Therefore, the scope of the attached patent application covers any such modifications and specific examples.
488031 案號 89107690 年夕月 》月，曰修正/吏正/禰疙 修正_ 圖式簡單說明 圖式元件符號簡單說明 10 p型矽區域 20 η型矽區域 3 0 閘極介電質 40 閘極結構 50 絕緣結構 6 0,9 0,1 4 0 ρ 型摻雜 7 0，8 0，1 6 0 η 型摻雜 100 側壁膜 101 PMOS電晶體的側壁寬度 102 NMOS電晶體的側壁寬度 110 NMOS 側壁 120 PMOS 側壁 13 0 光阻膜 1 50 光阻膜488031 Case No. 89107690 Month and Month, Revised / Revised / Revised _ Brief Description of Drawings Simple Description of Symbols of Drawing Elements 10 p-type silicon region 20 η-type silicon region 3 0 gate dielectric 40 gate Structure 50 Insulation structure 6 0,9 0,1 4 0 ρ-type doping 7 0,8 0,1 6 0 η-type doping 100 sidewall film 101 sidewall width of PMOS transistor 102 sidewall width of NMOS transistor 110 NMOS sidewall 120 PMOS sidewall 13 0 photoresist film 1 50 photoresist film
0:\63)63583-910329.ptc 第11頁0: \ 63) 63583-910329.ptc Page 11
Claims (1)
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