經濟部智慧財產局Η工消費合作社印緊 Γ ·4325 4 2 ΙΓ 五、發明说明（） 發明領域= 本發明係與一種電晶體之製程有關，特別是有關於— 種形成具有提昇之源 >及極區（elevated source/drain)及固相 擴散（solid phase diffused)的金氧半場效電晶體（meta丨oxide semiconductor field effect transistor; MOSFET)之方法。 發明背景： 自從第一個積體電路於西元1 9 6 0年首先發明以來，半 導體製程中單一晶片上的元件數目，即以爆炸性的速度快 速成長，隨著半導體工業近四十年的發展，現階段的半導 體製程技術已邁入超大型積體電路（ultra large scale integration; ULSI)、以及更高密度的時代，單一晶片上的元 件數目也由以往的數干個元件，增加至數吉萬個元件，甚： 辱可達到單一晶片上製作數千萬個或是更多個元件的密 度< 因此，半導體晶片上如電晶體、電容器、及連線等皆， 必須進一步縮減其所使用面積，以提高元件積集度（packing density)，此一要求形成對半導體製程技術的一大挑戰，每 —個半導體元件皆必須在不影響其功能的前提下，進一步 縮減其尺寸或占用的面積，而在更高的積集度之下，整'體 元件或電路之功能仍須維持不變、甚至必須具有更好的可 靠度、工作壽命、並同時加入低功率消耗及fe發熱率的特 本紙恨尺度通用中國國家標隼（CNS ) Α4规格（2丨) ΪΜII 訂 n JIM I i 1 (請先K讀背16之注意事項再填寫本頁) 經濟部智慧財產局吕：工消"合作社印製 Γ 臞4325 4 k _____ir五、發明説明（ ） ~~ 性。因此丰導體製程中的五大製程技術，也就是包含微影、 蝕刻、沈積、離子佈植、及熱製程的四大製程技術，也就 是包含微影、軸刻、薄膜、及擴散的製程技術，必須同時 的研究與發展，以達成下一代積體電路的發展目標。 在一般的積體電路中，最常被應用的元件之一即是具 有控制特性的電體1尤其是所謂的金氧半場效電晶體 (MOSFET)’隨著元件尺寸的曰益縮減，次微米尺寸的金氧 半場效電晶體同時面臨更多的挑戰。當積體電路中每一個 金氧半場效電晶想所占的長度與寬度縮小時，電晶體的通 道長度亦隨之縮減’而引發的墜穿效應，將造成元件漏電 流增大及崩潰電壓減小等問題，因而降低了半導禮製程的 良率及元件的可靠度。 為了發展未來次微米（sub-micrometer)尺寸 '甚至是更 小尺寸的金氧半場效電晶體，必須使用極淺通道的技術， 以抑制元件尺寸縮.減所造.成·的、短通道效應。....但在.極小的元 ... 件尺寸及極高的積集度下，：要製造極淺通道的金氧半場效 電晶體’技術上有相當的ϋ難:，傳統的離子i人製程，很 難形成具有較高離子濃度的極淺通道。 在K. Takeuchi等人所發表的著作（“High performance sub-tenth micron CMOS using advanced boron doping and WSi2 dual gate process”，in.' 1 995 Symposium on VLSI Technology Digest of . Technical.:.Papers)中.，，即·提出此广問 題，.並表示.以離子植入製程的特性，要形戒真，有高離子濃 ,；. '；- - 度的淺通道，有相當的困難性，且基材缺陷斛導致的通道 (請先"讀背而-注意事項再填寫本頁) 本纸掁义度遢川中闽國家標準（C.NS )六4现格（2!〇x297公;t ) 經濟部智1財走局負工消費合作社印^ 醪432542 ， 八 _____五、發明説明（） 區硼離子擴散造成許多問題，基材中靠近源汲極區的區域 性硼空乏現象，會更增加短通道效應。 此外，閘極結構中多晶矽中的硼離子，經常會由於侵 入閘極氡化層或穿透進入基材，而造成元件效能的退化， S.L.Wu(本發明之發明人）、C.L.Lee、及T_F. Lai即於所發 表的論文中提出上述現象（“Suppression of Boron Penetration into an Ultra-Thin Gate Oxide 7nm) by UsingaStacked-Amorphous-Silicon(SAS)Film”，IEDM93-3 29 1 993 IEEE)，其中即提到，p型掺雜的多晶矽己廣泛的 使用作為P型金氧半場效電晶體的閘極材質，以避免短通 道效應。一般而言，大多是使用含硼及氟的離子（BF2)植入 以形成閘極及源汲極區，然而氟的影響會使硼離子很容易 侵入問極氧化層或穿透進入基材内，而導致元件臨界電壓 的變化，他們並提出堆疊非晶石夕（stacked-amorphous silicon; .， SAS)層的結構，以抑制氟引發碎硼離子穿透:效應。.+ - : 發明目的及概述： 本發明的目的為提供一種電晶體的形成方法。 本發明的另一目的為提供一種具有提昇之源汲極區的 金氧半場效電晶體（MOSFET)的形成方法。 本發明的再一目的為提供一種金氧半場效電晶體的形 , - 成方法，利用電漿擴散或低能量離子植入的製程，形成極淺 的源汲極區，以進一步提昇半導;體元件的特性及製程的積集 (請先料讀背面之注意事項再填寫本頁) 裝 訂 本紙張尺度適用中圃國家標準（CNS ) Λ4规格（210X 297公簌） 經濟部智£財產局肖工消"合作社印製 「靨4 325 ‘坌 Η"五、發明説明（）度。 本發明中形成電晶體之方法可包含以下步驟：首先形成 閘極絕緣層於基材上：並形成一第一矽層於閘極絕緣層 上；再形成一抗反射層於第—矽層上；接著去除部分之抗 反射層、第一矽層、及閘極絕緣層以定義一閘極區域；之後 摻雜基材未被閘極區域覆蓋之部分，以形成延伸源汲極接面 於基材之内；並形成未摻雜之側壁結構於閘極區域之侧壁 上；再去除抗反射層：然後形成—第二矽層於基..材上汲*第 一矽層上方；再對基材進行離子植入以摻雜第二矽層、及形 成源汲·極接面於未被閘極區域及側壁結構覆蓋之基材内；最 後進行一熱製程，以擴散並活化延伸源汲極接面及源汲極接 面之離子。 圖式簡單說明： ·. ' . I 第一圖 顯示本發明中形成閘極絕緣層、第一矽層、 及抗反射層於基材上之戴面杗意圖。‘ 第二圖 顯示本發明中去除部分之抗反射層、第一矽 層、及閘極絕緣層以定義一閘極區域之截面 示意圖° 第三圖 顯示本發明中摻雜基材未被閘極區域覆蓋 之部分，以形成延伸源汲極接面於基材之内 、的〜截面示意圖。. 第四圖’顯示本發明中形成側壁結構於閘極區域、並 (讀先"讀背而-注意事項再填芎本頁)Intellectual Property Cooperative Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Γ · 4325 4 2 ΙΓ 5. Description of the Invention () Field of the Invention = The present invention is related to the process of a transistor, and particularly related to-the formation of a source of improvement > And polarized (elevated source / drain) and solid phase diffused (meta 丨 oxide semiconductor field effect transistor (MOSFET)) methods. Background of the Invention: Since the first integrated circuit was first invented in 1960, the number of components on a single wafer in the semiconductor process has grown rapidly at an explosive rate. With the development of the semiconductor industry in the past four decades, The current stage of semiconductor process technology has entered the era of ultra large scale integration (ULSI) and higher density. The number of components on a single chip has also increased from several dry components to tens of thousands. Components, even: the density can reach tens of millions or more components on a single chip < therefore, semiconductor chips such as transistors, capacitors, and wiring must be further reduced in area In order to improve the packing density of components, this requirement poses a major challenge to semiconductor process technology. Each semiconductor component must further reduce its size or occupied area without affecting its function. With a higher degree of integration, the function of the entire body component or circuit must remain unchanged, and it must even have better reliability. Special paper with low power consumption and fe heating rate at the same time of working life, common standard of Chinese National Standards (CNS) Α4 specifications (2 丨) ΪΜII order n JIM I i 1 (please read the precautions of K 16 first) (Fill in this page) Lu, Bureau of Intellectual Property, Ministry of Economic Affairs: Printed by the Consumers' Cooperative Γ 臞 4325 4 k _____ir V. Description of the Invention () ~~. Therefore, the five major process technologies in the Fengcong process are the four major process technologies including lithography, etching, deposition, ion implantation, and thermal processes, which are the process technologies including lithography, axial etching, thin film, and diffusion. Research and development must be conducted simultaneously to achieve the development goals of the next generation of integrated circuits. In general integrated circuits, one of the most commonly used components is the electric body 1 with control characteristics, especially the so-called metal-oxide-semiconductor field-effect transistor (MOSFET). At the same time, the size of the metal oxide half field effect transistor is facing more challenges. When the length and width of each metal-oxide-semiconductor half-effect transistor in the integrated circuit is reduced, the channel length of the transistor is also reduced accordingly, and the fall-through effect caused by the transistor will increase the component leakage current and the breakdown voltage. Reduction and other issues, thus reducing the yield and reliability of the semi-conductor process. In order to develop future sub-micrometer size or even smaller size metal-oxygen half field-effect transistors, it is necessary to use extremely shallow channel technology to prevent component size shrinkage, reduction, and short-channel effects. . .... But at a very small element size and a high degree of integration, it is technically quite difficult to manufacture a very shallow channel metal-oxygen half field effect transistor: traditional ions It is difficult to form a very shallow channel with a high ion concentration during the manufacturing process. In the work published by K. Takeuchi et al. ("High performance sub-tenth micron CMOS using advanced boron doping and WSi2 dual gate process", in. '1 995 Symposium on VLSI Technology Digest of. Technical.:.Papers). That is, to raise this broad question, and express that the characteristics of the ion implantation process must be true or absent, with a high ion concentration, and the shallow channel of the degree of ';--has considerable difficulty, and the basic Channels caused by wood defects (please read " read-before-notice before filling out this page) This paper is about the 4th standard (C.NS) of Sichuan and Fujian National Standards (2.〇x297 公; t) Printed by the Ministry of Economic Affairs and the Consumer Affairs Cooperative of the Finance Bureau 印 542432542, eight _____ V. Description of the Invention () The diffusion of boron ions in the area causes many problems. The regional boron vacancy phenomenon near the source drain region in the substrate will Increase the short channel effect. In addition, the boron ions in the polycrystalline silicon in the gate structure often cause degradation of element performance due to intrusion into the gate halide layer or penetration into the substrate. SLWu (the inventor of the present invention), CLLee, and T_F Lai proposed the above phenomenon in his published paper ("Suppression of Boron Penetration into an Ultra-Thin Gate Oxide 7nm) by UsingaStacked-Amorphous-Silicon (SAS) Film", IEDM93-3 29 1 993 IEEE), among which It is mentioned that p-type doped polycrystalline silicon has been widely used as the gate material of P-type metal-oxide-semiconductor half field effect transistors to avoid short channel effects. Generally speaking, most of the ions containing boron and fluorine (BF2) are implanted to form the gate and source drain regions. However, the effect of fluorine will make boron ions easily penetrate the interrogation oxide layer or penetrate into the substrate. As a result of the change in the critical voltage of the device, they proposed a structure of stacked-amorphous silicon (SAS) layers to suppress the penetration of broken boron ions caused by fluorine: the effect. . +-: Object and Summary of the Invention: The object of the present invention is to provide a method for forming a transistor. Another object of the present invention is to provide a method for forming a metal-oxide-semiconductor field-effect transistor (MOSFET) having a raised source drain region. Still another object of the present invention is to provide a shape of a metal oxide half field effect transistor, a method for forming a very shallow source-drain region using a plasma diffusion or low energy ion implantation process to further enhance the semiconductor; The characteristics of the body components and the accumulation of the manufacturing process (please read the precautions on the back before filling in this page) The size of this paper is applicable to the China National Standard (CNS) Λ4 specification (210X 297 gong). Industrial Consumers & Co., Ltd. printed "靥 4 325 '坌 Η" 5. Description of the invention (). The method for forming a transistor in the present invention may include the following steps: first forming a gate insulating layer on a substrate: and forming a The first silicon layer is on the gate insulation layer; an anti-reflection layer is formed on the first silicon layer; then a part of the anti-reflection layer, the first silicon layer, and the gate insulation layer are removed to define a gate region; The portion of the doped substrate that is not covered by the gate region forms an extended source-drain junction within the substrate; and forms an undoped sidewall structure on the sidewall of the gate region; and then removes the anti-reflection layer: Then formed-a second silicon layer on .. on the material * above the first silicon layer; then the substrate is ion-implanted to dope the second silicon layer, and a source-drain electrode interface is formed in the substrate not covered by the gate region and sidewall structure Finally, a thermal process is performed to diffuse and activate the ions that extend the source-drain junction and the source-drain junction. The diagram briefly explains: ·. 'I The first diagram shows the formation of the gate insulation layer, the first A silicon layer and an anti-reflection layer on the substrate are intended to be worn. 'The second figure shows the anti-reflection layer, the first silicon layer, and the gate insulation layer removed in the present invention to define a gate region. Sectional diagram ° The third diagram shows a section of the doped substrate in the present invention that is not covered by the gate region to form an extended source drain junction within the substrate. The fourth diagram shows the present invention. Side wall structure is formed in the gate area, and (read first " read back-note before filling out this page)
本紙張尺度適用中國國家標準（CNS )六4規格（210X297公淹） ΓΒ43254 2 ' Η五、發明説明（） 圖 五 第 層冲 射明上 反發材 抗本基 除示於 去顯層 意 除 第 層 圖 射層 示反矽 面抗 方 上 發意 二示 第面 成載 形之 並 圖 六 第 匕 活 並 散 擴 以 程 製 熱 一 行 進 中 明 發 本 。示 圖顯 的 子 fc· 0 之 内 面 接 極 汲 源 及 面 接。 極圖 汲意 源示 伸面 延截 請先閲請背面之注意事項再填寫本頁) •裝. 訂 經濟部智慧財產局貨工消骨合作社印^ 本紙张尺度適用中國國家標準（Λ4ί1格（210/297公漦） * i : : ______ ______________________________________________ i: . __________________________________ ______________________________________________________ 虼"·部智^!1ί^/ήΜ工4合作社卬製 43254 2 發明詳細說明 本發明中提供一種具有提昇之源汲極區及固相擴散之 延伸源汲極區的金氧丰場效電晶體（Μ 0 S F E T )之形成方法， 藉由提昇之源汲極區 '可消除短通道效應，並藉由電漿擴 散或低能量離子植入形成極淺的延伸源汲極區，藉以抑制 隨著元件尺寸縮小所造成的短通道效應。 在不限制本發明的精神及應用範圍下，以下以一半導 體製程中，Ν型之金氧半場效電晶體（Ν Μ 0 S )之形成方法及 結構為例1介紹本發明之實施，而熟悉此領域技藝者，可利 用相同之精神，應用於其他不同類型電晶體之製造，其變化 之.細節即不做贅述， ' '參見第一圖所示’首先提供一基材10，基材10 —般可 使用一矽材質 '晶向為< 1 0 0 > Α半導體基材’基材1 0_上已 形成隔離區1 2，隔離區1 2可為如圖中所示的埽氧化..區或是 使用其他的隔離製程’如溝渠隔離等。 如第一圖所示，形成一閉極:絕緣層1 4於‘基封1 〇上' 閘極絕緣層1 4可為一氧化層，此氧化層1 4係於一含氧環境 中，由基材10加熱氧化成長而成，氧化層12之厚度可約為 1 5 埃（a 11 g s t r 〇 m s)至 3 0 0 埃之間。 之後形成一第一矽層]6於閘極絕緣層14上’以本實 施例而言，第一矽層丨6可使用未摻雜之多晶矽層' 或是僅 具有輕微摻雜之多晶矽層1其形成可使用沈積方式達成，例 iW I ί . J!- 填 裝 Ί >'Jl 1¾ !H t N W t if： if ( f.NS ) A4)m ί 2；!].- ) 經濟部智慈財產妫：肖工"费合作社印製 r 贗43254 2 五、發明説明（） 如使用化學氣相沈積法等，未摻雜之多晶矽層1 6沈積之厚 度約為3 00埃至2000埃之間。 接著形成一抗反射層18於第一矽層16上，一般而言， 抗反射層18可使用一沈積而成之氮化矽層’抗反射層18 可於後續的微影製程中減少底層反射對曝光精確度的影 響，而增加圖案定義的準確性。 參見第二圖所示，去除部分之抗反射層 18、第一矽層 1 6、及閘極絕緣層 1 4，以定義一閘極區域。閘極區域之形 成，可使用一般的圖案化製程，也就是包含微影製程及蝕刻 製程的一連串步驟。一般定義閘極區域的過程可包含以下步 騾：首先形成一光阻層於抗反射層上；再利用微影製程中的 曝光及顯影，以定義一閘極圖案於光阻層上；並以光阻層為 罩幕，#刻抗反射層丨8，第一石夕層1 6、及閘極絕緣層1 4， 即可完成閘極區域之定義。 接著參見第三圖，之後掺‘雜基材1 〇中、未被閑極區域 覆蓋之部分，以形成延伸源汲極接面3 0於基材1 0之内，為 形成極淺的延伸源汲極接面，在較佳實施例之中’可利 用電漿擴散（或稱電漿浸入，piasmaimmersion)、或是低能量 離子植入的方式直接形成延伸源汲極接面3 0於基材1 0之 内。以形成nMOSFET而言，電漿擴散的製程，可使基材10 曝露於具有磷離子或砷離子的電漿環境之中’而使所需的離 入進入基材1〇未被覆蓋的表面處；而若使用低能量離子植 入的製程，可直接植入磷離子或砷離子’以本例而言’其植 本紙ί|ί尺度適用中國國家標準（CNS ) Λ4規格（2丨0〆297公益） 裝--*---„--訂-----^—線 ("先巧讀背而V/注意事項再填寫本'S ) . 歷43254 2 入之能量约為 〇 . 1至 ί K e V，所形成之摻雜濃度約岛丨l·' 1 3 至1 E 1 5 i ο n s / c m 2。.以形成ρ Μ ◦ S F E 丫 s的應用而言，上述 中電漿擴散的t程及低能量離子植入的製程中的雄離子或 砷離子’則可使用硼離子加以取代之。The size of this paper applies to China National Standards (CNS) six 4 specifications (210X297 male flood) ΓΒ43254 2 'Η 5. Description of the invention () The first layer shot layer shows the anti-silicon surface, and the second surface is shown in the shape of the load, and the sixth figure is active and scattered, and the process is heating. The inner surface of the sub-fc · 0 shown in the figure is connected to the source and the surface. The pole figure draws the source to show the extension of the surface, please read the notes on the back before filling in this page) • Packing. Ordered by the Goods and Consumers Bone Reduction Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ This paper size applies Chinese national standards (Λ4ί1 grid ( 210/297 public money) * i:: ______ ______________________________________________ i:. __________________________________ ______________________________________________________ 虼 " · 部 智 ^! 1ί ^ / ήΜ 工 4 卬 社 卬 制 43254 2 Detailed Description of the Invention The present invention provides a source drain with an improvement source Region and solid-phase diffusion extended source-drain MOS field-effect transistor (M 0 SFET) formation method, by elevating the source-drain region, the short-channel effect can be eliminated, and by plasma diffusion or Low-energy ion implantation forms a very shallow extended source drain region, thereby suppressing the short channel effect caused by the shrinking of the element size. Without limiting the spirit and application scope of the present invention, in the following, a semiconductor process, type N The formation method and structure of a metal-oxygen half field-effect transistor (N M 0 S) is taken as an example 1 to introduce the implementation of the present invention, and Those skilled in this field can use the same spirit to apply to the manufacture of other different types of transistors, and the changes will not be described in detail. 'See the first figure' First provide a substrate 10, substrate 10—Generally, a silicon material can be used. 'Crystal orientation is < 1 0 0 > Α semiconductor substrate'. An isolation region 12 has been formed on the substrate 1 0_, and the isolation region 12 can be as shown in the figure. Oxidation .. area or use other isolation processes such as trench isolation, etc. As shown in the first figure, a closed electrode is formed: the insulating layer 14 on the 'base seal 10 and the gate insulating layer 14 may be a An oxide layer 14 is formed in an oxygen-containing environment and is grown by heating and oxidizing the substrate 10. The thickness of the oxide layer 12 may be about 15 angstroms (a 11 gstr oms) to 300 angstroms. A first silicon layer is then formed] 6 on the gate insulating layer 14 'For the purpose of this embodiment, the first silicon layer 6 can be an undoped polycrystalline silicon layer' or a polycrystalline silicon with only slight doping. The formation of layer 1 can be achieved using a deposition method, for example iW I ί. J!-Filling Ί > 'Jl 1¾! H t NW t if: if (f.NS) A4) m ί 2 ;!]. -) Intellectual Property of the Ministry of Economic Affairs: Printed by Xiao Gong & Co., Ltd. r43254 2 V. Description of the Invention () If chemical vapor deposition is used, the undoped polycrystalline silicon layer 16 is deposited to a thickness of about 3 00 Angstroms to 2000 Angstroms. Next, an anti-reflection layer 18 is formed on the first silicon layer 16. Generally, the anti-reflection layer 18 can be a silicon nitride layer deposited. The anti-reflection layer 18 can reduce the underlying reflection in the subsequent lithography process. Impact on the accuracy of the exposure while increasing the accuracy of the pattern definition. Referring to the second figure, a part of the anti-reflection layer 18, the first silicon layer 16 and the gate insulating layer 14 are removed to define a gate region. The gate region can be formed using a general patterning process, that is, a series of steps including a lithography process and an etching process. The process of generally defining the gate region can include the following steps: first forming a photoresist layer on the anti-reflection layer; then using exposure and development in the lithography process to define a gate pattern on the photoresist layer; and The photoresist layer is a mask, #etched anti-reflection layer 丨 8, the first stone layer 16 and the gate insulation layer 14 can complete the definition of the gate area. Next, referring to the third figure, a portion of the 'hetero substrate 10' which is not covered by the free electrode region is formed to form an extension source drain junction 30 within the substrate 10 to form a very shallow extension source. Drain junction, in a preferred embodiment, 'plasma diffusion (or plasma immersion, piasmaimmersion), or low-energy ion implantation can be used to directly form an extended source drain junction 30 on the substrate Within 10. For the formation of nMOSFETs, the plasma diffusion process can expose the substrate 10 to a plasma environment with phosphorus ions or arsenic ions, so that the required ionization enters the uncovered surface of the substrate 10 However, if a low-energy ion implantation process is used, phosphorous or arsenic ions can be implanted directly. “In this case,” its plant paper is used. The Chinese national standard (CNS) Λ4 specification (2 丨 0〆297) Commonweal) installed-* --- „-subscribed ----- ^ — line (" read it first and then V / Notes before filling in this' S). Calendar 43254 2 The energy of entering is about 0.1 To ί K e V, the doping concentration formed is about 丨 l · '1 3 to 1 E 1 5 i ο ns / cm 2. To form ρ Μ ◦ For the application of SFE γs, the above plasma The male ion or arsenic ion in the diffusion process and low-energy ion implantation process can be replaced by boron ion.
裝 I 在延伸源汲極接面3 0形成之後，可選擇性的加人一形 成介電層22於基材10上之步驟，利用熱製程的方式、由基 材1 0及閘極區域之側壁上成長一介電層；本例中之介電層 2 2可使用一氮氡化矽層或是氧化矽層，氧化矽層係於含氧 (形成氮氧化矽時，可進—步加入含氮氣體）之環境中’由基 材1 0及第一矽層1 6加熱成長而成，並形成於基材1 0上、 以及第一矽層16與間極絕緣層1 4的側壁上，此一介電層 2 2之厚度約為5埃至1 0 0埃。 介電層 2 2的形成，可用以改善基材1 0之表面，利用 消耗部分表面的矽材質來修復基材1 〇於閘極區域定義時因 蝕刻所產生的缺陷。 線 參見第四圖所示，之後並形成未摻雜之側壁結構2 4於 閘極區域之側壁上，本例中未#雜之側壁結構1 2'4可為氧化 矽間隙壁，並可利用沈積並回蝕氧化矽層的方式加以形成° 在氧化矽間隙壁形成之後，即去除抗反射層1 8。在抗反射 經^部智总时^1:?;^工;7!贽合作社印緊 後 之 除 去 步 JI .處 熱 的 後 入 植 SV 1 ..子 層離 入' 加 的 fi 擇 選 可 .進 以' 進 性驟 特步 電入 導植 其 一 昇 提 .步 ·ώ 而 驟 步 的 入 植 子 β 0 第 # 步 層 矽 及使α卜， 此離 略將 省程 可製 亦入· /1 .植 中子 k離 例及 施層 實矽 的一. 同另 不的 在成 ;形 經濟部智慧財產局0(工消^合作社印製 「朦4325 4 2 vAfter the formation of the extended source-drain junction 30, a step of selectively forming a dielectric layer 22 on the substrate 10 can be added, using a thermal process, from the substrate 10 and the gate region. A dielectric layer is grown on the sidewall; the dielectric layer 22 in this example can be a silicon nitride layer or a silicon oxide layer. The silicon oxide layer is based on oxygen (to form silicon oxynitride, it can be further added.) In the environment containing nitrogen gas), the substrate 10 and the first silicon layer 16 are heated and grown, and are formed on the substrate 10 and the sidewalls of the first silicon layer 16 and the interlayer insulating layer 14 The thickness of this dielectric layer 22 is about 5 Angstroms to 100 Angstroms. The formation of the dielectric layer 22 can be used to improve the surface of the substrate 10, and the silicon material that consumes part of the surface is used to repair the defects of the substrate 10 caused by etching when the gate region is defined. The line is shown in the fourth figure, and then an undoped sidewall structure 24 is formed on the sidewall of the gate region. In this example, the non-doped sidewall structure 1 2'4 can be a silicon oxide spacer and can be used. The silicon oxide layer is deposited and etched back to form it. After the silicon oxide spacer is formed, the anti-reflection layer 18 is removed. In the anti-reflection zone, the total time of the Ministry of ^ 1:?; ^ Work; 7! 贽 Cooperative cooperatives to remove the step JI. After the heat into the planting SV 1. Sub-layer separation into the optional fi can be added. Progressive step-by-step electric step-by-step guide to plant one liter of promotion. Step · Selling and stepping into the plant β 0 ## Step layer of silicon and α α, this step will save the process can also be entered / 1 The first example of planting neutrons and the application of solid silicon. The same as the others; the Intellectual Property Bureau of the Ministry of Economic Affairs 0 (printed by Industrial Consumer Cooperative, "Ha 4325 4 2 v
_______FT 五、發明説明（） 子擴散至第一矽層16内。 參見第五圖所示，然後即形成第二矽層26於基材10 曝露的表面上、以及第一矽層16之上，由於抗反射層18 的去除’會留下一凹口於第一矽層16的上方及側壁結構24 内，而第二石夕層26的形成即會填入此凹口内，如第五圖所 示，而形成一複合層的堆疊閘極結構。本例中第二矽層26 可為一未摻雜的多晶矽層，硼摻雜矽層可利用一化學氣相沈 .積法形成’以最佳實施而言’可使用一選擇性的磊晶沈積方 式形成第二矽廣26 ’例如應用一高真空度的化學氣相沈積 法（ultra-high vacuum chemical vapor deposition; UHVCVD)。 在第二碎層26形成後’即對基材進行離子植入的 製程，以摻雜所需的離子至苐二矽層26内，以做為後續製 程中擴散進入基材丨0之離子來源2 8，而形成禪汲極接面於 未被問極區域及側壁結構24覆蓋之基材丨〇內0本例.中可應 用離子植入的製程’以nMOSFETs的應用而言，可植入較 高劑量的砷或磷離子進入第二矽層26，以藉由後續之熱擴 散製程形成源汲極接面，在較佳實施例裡，離子佈植的能量 約10-〗50 keV’以形成劑量約5£14至5E16 ions/cm2之間 的源汲極接面；以形成pMOSFETs的應用而言，則可使用 硼離子來取代上述的砷或磷離子。 、： 、參見第六圖所示’最後即進行一熱製程’以使第二矽 層26内的離子向下擴散形成源沒極接面28、並活化延伸源 10 適用中國囡家標华Ycns) A4%# ( ---^丨丨，—---裝--.--”—訂-----：丨線. (1ΐ"κι讀背荀之注意事項再填寫本頁) 14 325 4 2 五、發明説明（ ） ;及極接面3 0内之離子，形成如圖中所示的延伸源沒極接面 3 0及源汲極接面2 8。本例中之熱製程可使用一快速加熱製 程（rapid thermal process; RTP)，其溫度約為 700 °C 至 1150 。(：之間，並可得到接面極淺，且具有高濃度的源汲極區 28 及延伸源汲極區3 0，解決傳統離子製程較難形成的淺接面 區。 藉由以上之方法，即可完成本發明中具有提昇之源汲 極區的金氧半場效電晶體（M0SFET)的結構。並可進一步對 半導體基材10進行金屬連線製程1以形成對閘極及接面區 的電性連接，一般可包含一層或多層的連線層。金屬化導線 連接製程可包含一連_如形成接觸窗、填入導體層、以及平 坦化等的製程，若以形成較佳電性的要求而言’本發明可進 一步利用自行對準的石夕化金屬製程（self-aligned si丨icide)形 成一矽化金屬層於第二矽層··丈:上.；利用矽化.金屬.的f裎，可 降低接觸阻值，提昇連線的導電性’且由於本發明中之矽化 金屬層係形成於第二矽層2 6上，其形成或是矽化時不會消 ： .. · .· ....· .! . 1 . ' : 耗源汲極區2 8處的基材1 0，因此可避免源汲極區2 8的通 道受到影響。砍化金屬製程之細節步驟為此領域中所熟知之 技術，在此即不多做介紹。 本發明中之電晶體，可藉由電漿擴散或是低能量離子 植入形成極淺且寬度均—的源展極區，並藉由上述製程提 供提昇的源汲福區，.可消除傳统結構及製程中的短通道效 應，並利用一複合層之堆疊間_極..結構，可避.免硼離子入侵 本紙張尺度適用中阐國家標準（CNS ) Λ4規格（210/ 297公及） {請先間讀背兩之注意事項再填寫木.頁 -裝 訂 經濟部智慧財產局轉工消費合作社印製 Γ謬4325 4 2 閘極氧化層所造成的元件退化問題"因此可消除濞統製程 ‘ 應用於小尺寸元件中’因通道縮減所面臨的諸多問題 '減 丨. 少因通道及閘極寬度縮短的負面效果，提供更好的元件操 丨< 作特性及可靠度。 4 π 本發明以一較佳實施例說明如上’僅用於藉以幫助了 解本發明之實施，非用以限定本發明之精神，而熟悉此頜 1 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 Ρ·- 範圍內，當可作些許更動潤飾及等同之變化替換，其專利 署 保護範圍當視後附之申請專利範圍及其等同領域而定。 I $_______FT V. Description of the invention () The ions diffuse into the first silicon layer 16. Referring to the fifth figure, a second silicon layer 26 is then formed on the exposed surface of the substrate 10 and on the first silicon layer 16. Due to the removal of the anti-reflection layer 18, a notch will be left in the first Above the silicon layer 16 and in the sidewall structure 24, the formation of the second stone layer 26 will fill the notch, as shown in the fifth figure, to form a stacked gate structure with a composite layer. In this example, the second silicon layer 26 may be an undoped polycrystalline silicon layer, and the boron-doped silicon layer may be formed using a chemical vapor deposition. The formation method is 'for the best implementation' an optional epitaxy The deposition method forms the second silicon substrate 26 ′, for example, an ultra-high vacuum chemical vapor deposition (UHVCVD) method is used. After the second fragmentation layer 26 is formed, the process of ion implantation of the substrate is used to dope the required ions into the silicon layer 26 as a source of ions that diffuse into the substrate in the subsequent process. 28, and the Zen-drain junction is formed on the substrate that is not covered by the interrogation region and the side wall structure 24. In this example, the process of ion implantation can be applied. In the application of nMOSFETs, implantable Higher doses of arsenic or phosphorus ions enter the second silicon layer 26 to form a source-drain junction by a subsequent thermal diffusion process. In a preferred embodiment, the energy of the ion implantation is about 10- 〖50 keV 'to The source-drain junction is formed at a dose of about 5 £ 14 to 5E16 ions / cm2; for the application of forming pMOSFETs, boron ions can be used instead of the arsenic or phosphorus ions mentioned above. ： ， See Figure 6, 'Finally, a thermal process is performed' to make the ions in the second silicon layer 26 diffuse downward to form the source-electrode interface 28 and activate the extension source 10. Applicable to China's standard Chinese Ycns ) A4% # (--- ^ 丨 丨, ----- install --.-- ”— order -----: 丨 line. (1ΐ " κι read the notes on the back, then fill out this page) 14 325 4 2 V. Description of the invention (); and the ions in the pole junction 30, forming the extended source pole junction 30 and source drain junction 28 as shown in the figure. The thermal process in this example A rapid thermal process (RTP) can be used, and its temperature is about 700 ° C to 1150 °. (:, And can obtain a very shallow junction with a high concentration of the source-drain region 28 and the extended source The drain region 30 solves the shallow junction region that is difficult to form in the traditional ion manufacturing process. By the above method, the structure of the metal-oxide-semiconductor field-effect transistor (MOSFET) with an improved source drain region in the present invention can be completed. And can further perform a metal connection process 1 on the semiconductor substrate 10 to form an electrical connection to the gate electrode and the junction area, which generally includes one or more connection layers The metallization wire connection process may include a series of processes, such as forming a contact window, filling a conductor layer, and planarizing. If the requirements for better electrical properties are formed, the present invention can further utilize self-aligned Shi Xi The metallization process (self-aligned si 丨 icide) forms a silicided metal layer on the second silicon layer. ···: On the use of silicide. Metal. F 裎 can reduce the contact resistance and improve the conductivity of the connection. And because the silicided metal layer in the present invention is formed on the second silicon layer 26, it will not disappear when it is formed or silicided: .......... The substrate 10 at the polar region 28 can prevent the channel of the source-drain region 28 from being affected. The detailed steps of the metal-cutting process are well-known techniques in this field, and will not be described here. The transistor in the invention can form a very shallow and uniform width source-exhibitor region by plasma diffusion or low-energy ion implantation, and provide an enhanced source-blessing region through the above process, which can eliminate traditional structures. And the short channel effect in the manufacturing process, and the use of a composite layer stacking structure .Free from boron ions intrusion. Applicable National Standards (CNS) Λ4 specifications (210/297 and) in this paper. {Please read the two notes before filling in the wood. Page-Binding, Consumption of Intellectual Property, Ministry of Economic Affairs Cooperative printed Γ 43 4325 4 2 Element degradation caused by gate oxide " so it can eliminate the system process' application in small size components' reduced many problems due to channel shrinkage '. The negative effect of the shortened gate width provides better component operation < operation characteristics and reliability. 4 π The present invention is described above with a preferred embodiment. 'It is only used to help understand the implementation of the present invention, not to limit the spirit of the present invention. After understanding the spirit of the present invention, those skilled in this field will Without departing from the spirit of the present invention, the scope of protection of the Patent Office will depend on the scope of the patent application and its equivalent fields when it can be modified and replaced equivalently. I $