JP2005228906A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2005228906A
JP2005228906A JP2004036040A JP2004036040A JP2005228906A JP 2005228906 A JP2005228906 A JP 2005228906A JP 2004036040 A JP2004036040 A JP 2004036040A JP 2004036040 A JP2004036040 A JP 2004036040A JP 2005228906 A JP2005228906 A JP 2005228906A
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film
gate electrode
polycrystalline silicon
insulating film
semiconductor substrate
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JP4801323B2 (en
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Tsunenori Yamauchi
経則 山内
Shunji Nakamura
俊二 中村
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Fujitsu Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To realize a high-performance LDMOS transistor which is capable of highly efficient high-frequency operation as a basic element of a high-frequency power amplifier, typified by a cellular phone or wireless LAN by improving both f<SB>max</SB>and the power gain. <P>SOLUTION: Substitutional reaction between polycrystalline silicon and Al is utilized. Namely, a polycrystalline silicon film 4 is first patterned similar to a conventional device, an Al film is formed on a layer insulating film 9 in contact with the polycrystalline silicon film, and heat treatment is then conducted to substitute a polycrystalline silicon film 4 in the layer insulating film 9 with Al. By patterning this, a gate electrode 23 comprising Al of low gate parasitic resistance and high mobility is formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、高周波デバイスとして用いられる半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device used as a high-frequency device and a manufacturing method thereof.

従来より、携帯電話や無線ＬＡＮの基地局などを対象とした高周波用途の出力トランジスタが開発されている。例えば、５００ＭＨｚから５ＧＨｚのマイクロ波帯の高周波出力トランジスタとしては、ＧａＡｓＦＥＴが多く使われているが、最近のシリコンＬＳＩ技術の進歩に伴い、ＧａＡｓＦＥＴよりも安価で高品質ないわゆるシリコンＬＤＭＯＳ（Laterally Diffused MOS）トランジスタに替わりつつある。   Conventionally, output transistors for high-frequency applications for mobile phones and wireless LAN base stations have been developed. For example, GaAsFET is often used as a high-frequency output transistor in the microwave band from 500 MHz to 5 GHz. With recent advances in silicon LSI technology, so-called silicon LDMOS (Laterally Diffused MOS), which is cheaper and higher quality than GaAsFET. ) Transistors are being replaced.

従来のＬＤＭＯＳトランジスタの概略構成を図６に示す。
図示のように、ｐ-／ｐ+／ｐ-型のシリコン半導体基板１０１上にゲート絶縁膜１０２を介して電極形状の多結晶シリコン膜１１１及びその上層にＷシリサイド膜１１２がパターン形成されており、これらを覆うように層間絶縁膜１０３が形成されている。半導体基板１の表層には、ｎ型不純物が導入されてなるソース拡散層１０３及びｎ+ドレイン拡散層１０４が形成されており、ｎ+ソース拡散層１０４及びｎ+ドレインコンタクト層１０５の間にｎ+ドレインコンタクト層１０５と接続されてなる高周波耐性を確保するためのｎードリフト層１０６が形成されている。更にこの表層には、ソース拡散層１０４を覆うようにｐ-チャネル拡散層１０７及びこれと接続される基板コンタクト拡散層１０８が形成されている。 A schematic configuration of a conventional LDMOS transistor is shown in FIG.
As shown in the figure, an electrode-shaped polycrystalline silicon film 111 and a W silicide film 112 are patterned on a p − / p + / p − type silicon semiconductor substrate 101 via a gate insulating film 102. An interlayer insulating film 103 is formed so as to cover them. A source diffusion layer 103 and an n + drain diffusion layer 104 into which an n-type impurity is introduced are formed on the surface layer of the semiconductor substrate 1, and n n between the n + source diffusion layer 104 and the n + drain contact layer 105 are formed. An n-drift layer 106 for ensuring high-frequency resistance connected to the + drain contact layer 105 is formed. Further, on the surface layer, a p − channel diffusion layer 107 and a substrate contact diffusion layer 108 connected thereto are formed so as to cover the source diffusion layer 104.

層間絶縁膜１０３には、開孔１０９，１１０が形成されている。開孔１０９はｎ+ドレインコンタクト層１０５の表面の一部を露出するように形成されており、開孔１１０はソース拡散層１０４の表面の一部及び基板コンタクト拡散層１０８の表面の一部を露出するように形成されている。そして、層間絶縁膜１０３上で開孔１０９を下地膜１１３を介して埋め込みｎ+ドレインコンタクト層１０５と電気的に接続されてなるドレイン電極１２１と、層間絶縁膜１０３上で開孔１１０を下地膜１１３を介して埋め込みソース拡散層１０４と電気的に接続されてなるソース電極１２２と、層間絶縁膜１０３上で下地膜１１３を介してＷシリサイド膜１１２及び多結晶シリコン膜１１１と電気的に接続されてなる上部電極１２３が設けられ、ＬＤＭＯＳトランジスタが構成される。ここで、ドレイン電極１２１、ソース電極１２２、及び上部電極１２３はアルミニウムまたはその合金を材料としており、多結晶シリコン膜１１１、Ｗシリサイド膜１１２、及び上部電極１２３からゲート電極１２４が構成されている。 Openings 109 and 110 are formed in the interlayer insulating film 103. The opening 109 is formed so as to expose a part of the surface of the n + drain contact layer 105, and the opening 110 covers a part of the surface of the source diffusion layer 104 and a part of the surface of the substrate contact diffusion layer 108. It is formed to be exposed. Then, the opening 109 is embedded in the interlayer insulating film 103 through the base film 113 and the drain electrode 121 is electrically connected to the n + drain contact layer 105, and the opening 110 is formed in the base film on the interlayer insulating film 103. A source electrode 122 that is electrically connected to the buried source diffusion layer 104 through 113, and a W silicide film 112 and a polycrystalline silicon film 111 through the base film 113 on the interlayer insulating film 103. The upper electrode 123 is provided to constitute an LDMOS transistor. Here, the drain electrode 121, the source electrode 122, and the upper electrode 123 are made of aluminum or an alloy thereof, and the gate electrode 124 is composed of the polycrystalline silicon film 111, the W silicide film 112, and the upper electrode 123.

特開２００２−９４０５４号公報JP 2002-94054 A Hiroshi Horie, Masahiko, Imai, Akio Ito, and Yoshihiro Arimoto: Novel High Aspect Ratio Aluminum Plug for Logic/DRAm LSIs Using Polysilicon-Aluminum Substitute(PAS)", IEDM96,p.946，（１９９６）Hiroshi Horie, Masahiko, Imai, Akio Ito, and Yoshihiro Arimoto: Novel High Aspect Ratio Aluminum Plug for Logic / DRAm LSIs Using Polysilicon-Aluminum Substitute (PAS) ", IEDM96, p.946, (1996) 堀江博・今井雅彦・伊藤昭雄・有本由弘、「多結晶シリコンとアルミ置換による微細配線技技術」、電子情報通信学会 信学技報 ＳＤＭ９６−２０８（１９９７）Hiroshi Horie, Masahiko Imai, Akio Ito, Yoshihiro Arimoto, "Micro-wiring technology using polycrystalline silicon and aluminum substitution", IEICE Technical Report SDM96-208 (1997) 電気学会技術報告第６６６号「２１世紀に向けたパワーデバイスの重点課題」、p.36 （１９９８）IEEJ Technical Report 666, “Priority Issues of Power Devices for the 21st Century”, p.36 (1998) M.Shindo,M.Morikawa,T.Fujioka,K.Nagura,K.Kurotani,K.Odaira,T.Uchiyama,and I. Yoshida: "High Power LDMOS for Cellular Base Station Applications", ISPSD 2001, p.107(2001)M. Shindo, M. Morikawa, T. Fujioka, K. Nagura, K. Kurotani, K. Odaira, T. Uchiyama, and I. Yoshida: "High Power LDMOS for Cellular Base Station Applications", ISPSD 2001, p.107 (2001)

高周波用途の出力トランジスタの性能指標は、高周波動作限界を占う最大発信周波数ｆmaxと電力利得である。ｆmax向上のためにはゲート寄生抵抗を低減する必要があり、電力利得を向上させるためにはゲート電極とドレイン電極間の寄生容量Ｃgdを低減しなくてはならない。 The performance index of an output transistor for high frequency applications is the maximum transmission frequency f max and the power gain that occupy the high frequency operation limit. In order to improve f max , it is necessary to reduce the gate parasitic resistance, and in order to improve the power gain, the parasitic capacitance C gd between the gate electrode and the drain electrode must be reduced.

高周波電力増幅器では、より効果的な電波を発するため、当該増幅器に加えられた電力に対して出力される電波の電力を向上させる必要がある。特に電池を電源とする携帯電話では極めて重要な課題である。高効率で高周波動作を可能にするには、寄生抵抗、寄生容量を徹底的に削減する必要がある。性能指標である遮断周波数ｆTは、（１）式で示すように寄生容量に強く依存している。また最大発信周波数ｆmaxは、（２）式に示すようにゲート寄生抵抗に依存している。 In a high frequency power amplifier, in order to emit a more effective radio wave, it is necessary to improve the power of the radio wave output relative to the power applied to the amplifier. This is a particularly important issue for mobile phones that use batteries as a power source. In order to enable high-frequency operation with high efficiency, it is necessary to thoroughly reduce parasitic resistance and parasitic capacitance. The cut-off frequency f T that is a performance index strongly depends on the parasitic capacitance as shown by the equation (1). Further, the maximum transmission frequency f max depends on the gate parasitic resistance as shown in the equation (2).

ｆT＝ｇm／｛２π（Ｃgs＋Ｃds）｝ ・・・（１）
（ｇm：相互コンダクタンス、Ｃgs：ゲートーソース間寄生容量、Ｃds:ドレインーソース間寄生容量）
ｆmax＝ｆT／｛２（Ｒｇ・Ｇｄ）1/2｝ ・・・（２）
（Ｒｇ:ゲート寄生抵抗、Ｇｄ：ドレインコンダクタンス） f T = g m / {2π (C gs + C ds )} (1)
(G m : mutual conductance, C gs : gate-source parasitic capacitance, C ds : drain-source parasitic capacitance)
f max = f T / {2 (Rg · Gd) 1/2 } (2)
(Rg: gate parasitic resistance, Gd: drain conductance)

寄生容量Ｃgs，Ｃdsは遮断周波数ｆTを阻害し、ゲート寄生抵抗Ｒｇは最大発信周波数ｆmaxを阻害する。
従来では図６に示すように、多結晶シリコン膜１１１とＷシリサイド膜１１２とを積層したゲート構造を採るため、ゲート寄生抵抗Ｒｇは約１０Ω/□となり、このゲート寄生抵抗Ｒｇの低減には制限があった。そしてこのゲート寄生抵抗Ｒｇは、ゲート長を短くするほど顕著となり、その低減が高周波動作に対する課題であった。また、ゲート電極の多結晶シリコン側に空乏層が広がり相互コンダクタンスｇｍが低下することも高周波動作を阻害していた。 The parasitic capacitances C gs and C ds inhibit the cutoff frequency f T , and the gate parasitic resistance Rg inhibits the maximum transmission frequency f max .
Conventionally, as shown in FIG. 6, since a gate structure in which a polycrystalline silicon film 111 and a W silicide film 112 are stacked is adopted, the gate parasitic resistance Rg is about 10Ω / □, and the reduction of the gate parasitic resistance Rg is limited. was there. The gate parasitic resistance Rg becomes more prominent as the gate length is shortened, and the reduction thereof is a problem for high-frequency operation. In addition, the depletion layer spreading on the polycrystalline silicon side of the gate electrode and the mutual conductance gm being lowered also hindered the high frequency operation.

高周波用途の出力トランジスタでは、その高性能化のためには、ゲート寄生抵抗を極限まで低くすることが求められているものの、これを実現すべく開発されたＬＤＭＯＳトランジスタでも、上記の如き問題がある。   Output transistors for high-frequency applications require gate parasitic resistance to be as low as possible in order to improve performance, but LDMOS transistors developed to achieve this have the above-mentioned problems. .

本発明は、上記の課題を解決すべくなされたものであり、ｆmaxと電力利得の双方を向上させ、携帯電話や無線ＬＡＮに代表される高周波電力増幅器の基本素子として、高効率で高周波動作を可能とする高性能のＬＤＭＯＳトランジスタ及びその製造方法を提供することを目的とする。 The present invention has been made to solve the above-described problems, improves both f max and power gain, and is a high-efficiency, high-frequency operation as a basic element of a high-frequency power amplifier typified by a mobile phone or a wireless LAN. It is an object of the present invention to provide a high-performance LDMOS transistor and a method for manufacturing the same.

本発明の半導体装置は、半導体基板と、前記半導体基板の上方に形成されたゲート電極と、前記ゲート電極の両側における前記半導体基板の表層に形成されてなる一対の不純物拡散層と、前記ゲート電極と一方の前記不純物拡散層との間における前記半導体基板の表層に、前記不純物拡散層と同一の導電型として形成されてなるドリフト層と、を含み、前記ゲート電極は、アルミニウムを含む金属を材料としてオーバーハング形状に形成されてなる。   The semiconductor device of the present invention includes a semiconductor substrate, a gate electrode formed above the semiconductor substrate, a pair of impurity diffusion layers formed on a surface layer of the semiconductor substrate on both sides of the gate electrode, and the gate electrode And a drift layer formed as the same conductivity type as the impurity diffusion layer in a surface layer of the semiconductor substrate between the impurity diffusion layer and one of the impurity diffusion layers, and the gate electrode is made of a metal containing aluminum. It is formed in an overhang shape.

本発明の半導体装置の製造方法は、半導体基板上にゲート絶縁膜を介して電極形状の多結晶シリコン膜を形成する工程と、前記半導体基板に表層に不純物を導入して、一対の不純物拡散層及びドリフト層をそれぞれ形成する工程と、前記多結晶シリコン膜を覆うように、前記半導体基板上に層間絶縁膜を形成する工程と、前記層間絶縁膜の表層を除去して前記多結晶シリコン膜の上面を露出させる工程と、前記各不純物拡散層の表面の一部をそれぞれ露出させるように、前記層間絶縁膜に開孔を形成する工程と、前記各開孔を埋め込むように、前記層間絶縁膜上にアルミニウムを含む金属膜を形成する工程と、多結晶シリコンとアルミニウムとを選択的に置換反応させ、前記層間絶縁膜内の前記多結晶シリコン膜の形成部位を前記金属膜の材料で充填する工程と、前記金属膜を加工して、前記各不純物拡散層とそれぞれ接続されてなる一対の電極と、前記金属膜の材料で一体形成されてなるゲート電極とをそれぞれ形成する工程とを含む。   A method of manufacturing a semiconductor device according to the present invention includes: a step of forming an electrode-shaped polycrystalline silicon film on a semiconductor substrate through a gate insulating film; And a step of forming a drift layer, a step of forming an interlayer insulating film on the semiconductor substrate so as to cover the polycrystalline silicon film, and removing a surface layer of the interlayer insulating film to form the polycrystalline silicon film Exposing the upper surface; forming an opening in the interlayer insulating film so as to expose a part of the surface of each impurity diffusion layer; and filling the interlayer insulating film so as to embed each opening. A step of forming a metal film containing aluminum thereon, and a selective substitution reaction between polycrystalline silicon and aluminum, and the formation site of the polycrystalline silicon film in the interlayer insulating film is a material of the metal film And a step of processing the metal film to form a pair of electrodes respectively connected to the impurity diffusion layers and a gate electrode formed integrally with the material of the metal film. including.

本発明によれば、ｆmaxと電力利得の双方を向上させ、携帯電話や無線ＬＡＮに代表される高周波電力増幅器の基本素子として、高効率で高周波動作を可能とする高性能のＬＤＭＯＳトランジスタが実現する。 According to the present invention, a high-performance LDMOS transistor capable of high-frequency operation with high efficiency is realized as a basic element of a high-frequency power amplifier typified by a mobile phone or a wireless LAN by improving both f max and power gain. To do.

−本発明の基本骨子−
本発明者は、ＬＤＭＯＳトランジスタにおいてｆmaxと電力利得の双方の向上を実現すべく、ＬＤＭＯＳトランジスタのゲート電極材料の改良に考察した。従来のＬＤＭＯＳトランジスタのゲート電極では、その構成上、ゲート電極の下部層を多結晶シリコンを用いてパターン形成していたため、その寄生抵抗及び寄生容量の低減には限界があった。本発明者は、ゲート電極を全てアルミニウム（Ａｌ）（またはその合金：以下、同様の意味でＡｌと記す。）から構成することに想到した。ゲート材料を全てＡｌとすることにより、ゲート寄生抵抗が約１／５０となり大きな改良が可能となる。また同時に、空乏層のゲート電極部位への広がりが全く無くなり、チャネル移動度が約１．２倍に向上する。 -Basic outline of the present invention-
The present inventor has considered the improvement of the gate electrode material of the LDMOS transistor in order to realize both the f max and the power gain in the LDMOS transistor. In the conventional gate electrode of an LDMOS transistor, the lower layer of the gate electrode is patterned by using polycrystalline silicon because of its configuration, and thus there is a limit to the reduction of parasitic resistance and parasitic capacitance. The present inventor has conceived that the gate electrode is entirely made of aluminum (Al) (or an alloy thereof: hereinafter referred to as Al in the same meaning). By making all the gate material Al, the gate parasitic resistance becomes about 1/50 and a great improvement is possible. At the same time, the depletion layer does not spread to the gate electrode portion, and the channel mobility is improved by about 1.2 times.

そして、上記のゲート電極を実現すべく、多結晶シリコンとＡｌ間における置換反応を利用する。即ち、先ず従来と同様に多結晶シリコン膜をパターン形成し、層間絶縁膜上に多結晶シリコン膜と接触するようにＡｌ膜を形成した後、熱処理することにより、層間絶縁膜内の多結晶シリコン膜をＡｌで置換する。これをパターニングすることにより、ゲート寄生抵抗の低く移動度の高いＡｌからなるゲート電極が形成される。   In order to realize the gate electrode, a substitution reaction between polycrystalline silicon and Al is used. That is, first, a polycrystalline silicon film is patterned in the same manner as in the prior art, an Al film is formed on the interlayer insulating film so as to be in contact with the polycrystalline silicon film, and then heat treatment is performed, so that the polycrystalline silicon in the interlayer insulating film is formed. Replace the film with Al. By patterning this, a gate electrode made of Al with low gate parasitic resistance and high mobility is formed.

また、ゲート電極の形成と同じプロセスにより、ゲート電極と一方の電極（ドレイン電極）との間に、Ａｌからなるシールド層を形成する。このシールド層は、更なる高周波性能の向上を図るためのものであり、ゲート電極のパターンの他にゲート電極とドレイン電極の間にもう１つ当該シールド電極のパターンをマスク内に設けることで全く工程を追加せずに形成することができ、非常に精度良くゲート電極とシールド層との間隔を規定できると共に、シールド層形成のための導電膜のスパッタ、フォトエッチング、絶縁膜成長などの製造工程の簡略化が可能とする。   In addition, a shield layer made of Al is formed between the gate electrode and one electrode (drain electrode) by the same process as the formation of the gate electrode. This shield layer is intended to further improve the high-frequency performance, and in addition to the gate electrode pattern, another shield electrode pattern is provided in the mask between the gate electrode and the drain electrode. It can be formed without additional processes, and the gap between the gate electrode and the shield layer can be defined with very high accuracy, and the manufacturing process such as sputtering of the conductive film, photoetching, and growth of the insulating film for forming the shield layer Can be simplified.

−本発明の具体的な諸実施形態−
以下、本発明を適用する好適な諸実施形態について説明する。本実施形態では、ＬＤＭＯＳトランジスタの構成をその製造方法と共に述べる。 -Specific embodiments of the present invention-
Hereinafter, preferred embodiments to which the present invention is applied will be described. In the present embodiment, the configuration of the LDMOS transistor will be described together with its manufacturing method.

（第１の実施形態）
図１及び図２は、第１の実施形態によるＬＤＭＯＳトランジスタの製造方法を工程順に示す概略断面図である。
先ず、図１（ａ）に示すように、ｐ-／ｐ+／ｐ-型のシリコン半導体基板１上に所定のフォトマスク（不図示）を形成し、これをマスクとして半導体基板１の表層にｐ型不純物、ここではホウ素（Ｂ）を加速エネルギー６０ｋｅＶ、ドーズ量２×１０15／ｃｍ2の条件でイオン注入し、前記フォトマスクを灰化処理等により除去した後、半導体基板１に１１００℃で３０分間の熱処理を加えることにより、基板コンタクト層２を形成する。 (First embodiment)
1 and 2 are schematic cross-sectional views showing the method of manufacturing the LDMOS transistor according to the first embodiment in the order of steps.
First, as shown in FIG. 1A, a predetermined photomask (not shown) is formed on a p − / p + / p − type silicon semiconductor substrate 1 and used as a mask on the surface layer of the semiconductor substrate 1. A p-type impurity, here boron (B), is ion-implanted under the conditions of an acceleration energy of 60 keV and a dose of 2 × 10 15 / cm 2 , and the photomask is removed by ashing or the like. The substrate contact layer 2 is formed by applying a heat treatment for 30 minutes.

続いて、図１（ｂ）に示すように、熱酸化法により半導体基板１の表面に膜厚１０ｎｍ程度のゲート絶縁膜３を形成する。引き続き、ＣＶＤ法により多結晶シリコン膜４を堆積し、フォトリソグラフィー及びそれに続くドライエッチングにより多結晶シリコン膜４を電極形状に加工する。   Subsequently, as shown in FIG. 1B, a gate insulating film 3 having a thickness of about 10 nm is formed on the surface of the semiconductor substrate 1 by a thermal oxidation method. Subsequently, the polycrystalline silicon film 4 is deposited by the CVD method, and the polycrystalline silicon film 4 is processed into an electrode shape by photolithography and subsequent dry etching.

続いて、図１（ｃ）に示すように、シリコン半導体基板１上に所定のフォトマスク（不図示）を形成し、多結晶シリコン膜４の片側のみにおける半導体基板１の表層にｐ型不純物、ここではホウ素（Ｂ）を加速エネルギー３０ｋｅＶ、ドーズ量２×１０13／ｃｍ2の条件でイオン注入し、前記フォトマスクを灰化処理等により除去した後、半導体基板１に１０００℃で３０分間の熱処理を加えることにより、ｐ-チャネル拡散層６を形成する。 Subsequently, as shown in FIG. 1C, a predetermined photomask (not shown) is formed on the silicon semiconductor substrate 1, and p-type impurities are formed on the surface layer of the semiconductor substrate 1 only on one side of the polycrystalline silicon film 4. Here, boron (B) is ion-implanted under the conditions of an acceleration energy of 30 keV and a dose of 2 × 10 13 / cm 2 , the photomask is removed by ashing or the like, and then the semiconductor substrate 1 is subjected to 1000 ° C. for 30 minutes. By applying heat treatment, the p − channel diffusion layer 6 is formed.

引き続き、シリコン半導体基板１上に所定のフォトマスク（不図示）を形成し、半導体基板１の表層にｎ型不純物、ここではリン（Ｐ）を加速エネルギー１２０ｋｅＶ、ドーズ量２×１０15／ｃｍ2の条件でイオン注入し、前記フォトマスクを灰化処理等により除去した後、１０００℃で３０分間の熱処理を半導体基板１に加えることにより、ｎ+ドレインコンタクト層５を形成する。 Subsequently, a predetermined photomask (not shown) is formed on the silicon semiconductor substrate 1, and an n-type impurity, here phosphorus (P), is applied to the surface layer of the semiconductor substrate 1 with an acceleration energy of 120 keV and a dose of 2 × 10 15 / cm 2. After the ion implantation is performed under the above conditions and the photomask is removed by ashing or the like, a heat treatment at 1000 ° C. for 30 minutes is applied to the semiconductor substrate 1 to form the n + drain contact layer 5.

続いて、図１（ｄ）に示すように、シリコン半導体基板１上に所定のフォトマスク（不図示）を形成し、半導体基板１の表層にｎ型不純物、ここではリン（Ｐ）を加速エネルギー６０ｋｅＶ、ドーズ量３×１０12／ｃｍ2の条件でイオン注入し、前記フォトマスクを灰化処理等により除去した後、９５０℃で３０分間の熱処理を半導体基板１に加えることにより、ｎードリフト層８を形成する。 Subsequently, as shown in FIG. 1D, a predetermined photomask (not shown) is formed on the silicon semiconductor substrate 1, and an n-type impurity, here phosphorus (P), is accelerated on the surface layer of the semiconductor substrate 1. Ions are implanted under the conditions of 60 keV and a dose of 3 × 10 12 / cm 2 , the photomask is removed by ashing or the like, and then a heat treatment at 950 ° C. for 30 minutes is applied to the semiconductor substrate 1 to thereby form an n-drift layer. 8 is formed.

引き続き、シリコン半導体基板１上に所定のフォトマスク（不図示）を形成し、半導体基板１の表層にｎ型不純物、ここでは砒素（Ａｓ）を加速エネルギー３０ｋｅＶ、ドーズ量３×１０15／ｃｍ2の条件でイオン注入し、前記フォトマスクを灰化処理等により除去した後、９００℃で３０分間の熱処理を半導体基板１に加えることにより、ｎ+ソース拡散層７を形成する。 Subsequently, a predetermined photomask (not shown) is formed on the silicon semiconductor substrate 1, and an n-type impurity, here arsenic (As), is applied to the surface layer of the semiconductor substrate 1 at an acceleration energy of 30 keV and a dose of 3 × 10 15 / cm 2. After the ion implantation is performed under the above conditions and the photomask is removed by ashing or the like, a heat treatment for 30 minutes at 900 ° C. is applied to the semiconductor substrate 1 to form the n + source diffusion layer 7.

続いて、図１（ｅ）に示すように、半導体基板１上に多結晶シリコン膜４を覆うように、ＣＶＤ法によりシリコン酸化膜を膜厚６００ｎｍ程度に堆積し、層間絶縁膜９を形成する。このとき、層間絶縁膜９の多結晶シリコン膜４の上部に相当する部分が他の部分より２００ｎｍ程度盛り上がる。   Subsequently, as shown in FIG. 1E, a silicon oxide film is deposited to a thickness of about 600 nm by the CVD method so as to cover the polycrystalline silicon film 4 on the semiconductor substrate 1 to form an interlayer insulating film 9. . At this time, the portion of the interlayer insulating film 9 corresponding to the upper portion of the polycrystalline silicon film 4 is raised by about 200 nm from the other portions.

続いて、図１（ｆ）に示すように、層間絶縁膜９の表面を多結晶シリコン膜４の上面が露出するまで化学機械研磨（ＣＭＰ）法により研磨する。通常、多結晶シリコン膜とアルミニウムとを反応させる部分の絶縁膜を取り除くときには、フォトエッチングを用いるのが一般的である。その場合、フォトリソグラフィーの位置合わせズレにより多結晶シリコン膜の上部以外の絶縁膜がエッチングされてしまい、良好なデバイス構造が得られない。本実施形態では、上述のようにＣＭＰ法を用いることにより、フォトエッチングを要することなく自己整合的に多結晶シリコン膜４の上面を露出させることができる。なお、ＣＭＰ法の替わりに、層間絶縁膜９の多結晶シリコン膜４の上部に相当する部位を一様にエッチングする方法を用いても良い。   Subsequently, as shown in FIG. 1F, the surface of the interlayer insulating film 9 is polished by a chemical mechanical polishing (CMP) method until the upper surface of the polycrystalline silicon film 4 is exposed. Usually, photoetching is generally used to remove the insulating film where the polycrystalline silicon film reacts with aluminum. In that case, an insulating film other than the upper part of the polycrystalline silicon film is etched due to misalignment of photolithography, and a good device structure cannot be obtained. In the present embodiment, by using the CMP method as described above, the upper surface of the polycrystalline silicon film 4 can be exposed in a self-aligned manner without requiring photoetching. Instead of the CMP method, a method of uniformly etching a portion corresponding to the upper portion of the polycrystalline silicon film 4 of the interlayer insulating film 9 may be used.

続いて、図２（ａ）に示すように、層間絶縁膜９にフォトリソグラフィー及びそれに続くドライエッチングを施し、ｎ+ドレインコンタクト層５の表面の一部を露出させるドレインコンタクト孔１０と、ｎ+ソース拡散層７の表面の一部及び基板コンタクト層２の表面の一部を露出させるソースコンタクト孔１１をそれぞれ形成する。 Subsequently, as shown in FIG. 2A, the interlayer insulating film 9 is subjected to photolithography and subsequent dry etching to expose a portion of the surface of the n + drain contact layer 5, and the n + Source contact holes 11 are formed to expose part of the surface of the source diffusion layer 7 and part of the surface of the substrate contact layer 2.

引き続き、ドレインコンタクト孔１０の内壁面及びソースコンタクト孔１１の内壁面を覆うように、層間絶縁膜９上にＴｉＮ膜を成膜し、下地膜（バリアメタル膜）１２を形成する。   Subsequently, a TiN film is formed on the interlayer insulating film 9 so as to cover the inner wall surface of the drain contact hole 10 and the inner wall surface of the source contact hole 11 to form a base film (barrier metal film) 12.

ここで従来より、バリアメタル膜はコンタクト孔の部分でアルミニウムとシリコンとの反応を防止するバリアメタルとして広く用いられている。しかしながら本実施形態では、後述するように多結晶シリコンをアルミニウムに置換する部分ではバリアメタル膜が障害となる。そこで、図２（ｂ）に示すように、バリアメタル膜１２にフォトリソグラフィー及びそれに続くドライエッチングを施し、バリアメタル膜１２の多結晶シリコン膜４の上面に相当する部位を除去し、当該上面のみを露出させる開孔１３を形成する。   Heretofore, the barrier metal film has been widely used as a barrier metal for preventing the reaction between aluminum and silicon at the contact hole. However, in this embodiment, as will be described later, the barrier metal film becomes an obstacle at the portion where polycrystalline silicon is replaced with aluminum. Therefore, as shown in FIG. 2B, the barrier metal film 12 is subjected to photolithography and subsequent dry etching to remove a portion of the barrier metal film 12 corresponding to the upper surface of the polycrystalline silicon film 4, and only the upper surface is removed. An opening 13 is formed to expose the.

続いて、図２（ｃ）に示すように、スパッタ法により全面にＡｌ膜１４を膜厚１０００ｎｍ程度に形成する。このとき、開孔１３のみにおいて多結晶シリコン膜４とＡｌ膜１４とが直接接触することになる。そして、４５０℃で６０分間の熱処理により、多結晶シリコン膜４とＡｌ膜１４とを置換反応させる。これにより、多結晶シリコン膜４が吸い出されると共に、層間絶縁膜９の多結晶シリコン膜４の形成部位にＡｌが侵入し、多結晶シリコン膜４がＡｌ膜２０に置き換わる。このように、多結晶シリコン膜４に相当する部分のみのバリアメタル膜１２を除去することにより、他の部分には置換反応が惹起されることなくゲート部分のみに多結晶シリコンとアルミニウムとの置換反応が惹起される。   Subsequently, as shown in FIG. 2C, an Al film 14 is formed to a thickness of about 1000 nm on the entire surface by sputtering. At this time, the polycrystalline silicon film 4 and the Al film 14 are in direct contact only in the opening 13. Then, the polycrystalline silicon film 4 and the Al film 14 are subjected to a substitution reaction by heat treatment at 450 ° C. for 60 minutes. As a result, the polycrystalline silicon film 4 is sucked out, Al enters the portion of the interlayer insulating film 9 where the polycrystalline silicon film 4 is formed, and the polycrystalline silicon film 4 is replaced with the Al film 20. In this way, by removing the barrier metal film 12 only in the portion corresponding to the polycrystalline silicon film 4, substitution of polycrystalline silicon and aluminum is performed only in the gate portion without causing a substitution reaction in the other portion. A reaction is triggered.

続いて、図２（ｄ）に示すように、Ａｌ膜１４及びバリアメタル膜１２をフォトリソグラフィー及びそれに続くドライエッチングによりパターニングし、バリアメタル膜１２を介してドレインコンタクト孔１０を埋め込むオーバーハング形状のドレイン電極２１と、バリアメタル膜１２を介してソースコンタクト孔１１を埋め込むオーバーハング形状のソース電極２２と、Ａｌ膜２０と上部電極１５とが接続された全てＡｌからなるオーバーハング形状のゲート電極２３とをそれぞれ同時形成する。ここで、トランジスタのレイアウト上、ゲート電極２３とドレイン電極２１との距離はゲート電極２３とソース電極２２との距離よりも大きいため、ゲート電極２３の上部電極１５を、図示のようにドレイン電極２１側に偏って延在する非対称形状に形成する。このように、上記の置換反応に用いたＡｌ膜１４をそのまま残して各種電極に用いるため、製造プロセスが極めて容易となり、製造コストの低減にもつながる。   Subsequently, as shown in FIG. 2D, the Al film 14 and the barrier metal film 12 are patterned by photolithography and subsequent dry etching to form an overhang shape in which the drain contact hole 10 is embedded through the barrier metal film 12. A drain electrode 21, an overhang-shaped source electrode 22 that fills the source contact hole 11 through the barrier metal film 12, and an overhang-shaped gate electrode 23 made of all Al, in which the Al film 20 and the upper electrode 15 are connected. Are simultaneously formed. Here, since the distance between the gate electrode 23 and the drain electrode 21 is larger than the distance between the gate electrode 23 and the source electrode 22 due to the layout of the transistor, the upper electrode 15 of the gate electrode 23 is connected to the drain electrode 21 as shown in the figure. It is formed in an asymmetrical shape that extends toward the side. Thus, since the Al film 14 used in the above substitution reaction is left as it is and used for various electrodes, the manufacturing process becomes extremely easy and the manufacturing cost is reduced.

しかる後、電極保護膜やボンディング部（共に不図示）等の形成を経て、本実施形態のＬＤＭＯＳトランジスタを完成させる。   Thereafter, an LDMOS transistor of this embodiment is completed through formation of an electrode protective film, a bonding portion (both not shown), and the like.

本実施形態のＬＤＭＯＳトランジスタにおいて、ゲート寄生抵抗が図６に示す従来構成に比して１／１０に激減する。また、チャネル移動度は約２０％向上する。これらの効果により、高周波動作の指標である最大発信周波数ｆmaxは、２０ＧＨｚから５０ＧＨｚへと約２．５倍に向上する。図３は、ゲート抵抗と最大発信周波数との関係を示す特性図である。なお、上述の（１）式及び（２）式にて期待される値より低い理由は、これらの近似式に含めたパラメータ以外の要素に制限されたためである。 In the LDMOS transistor of this embodiment, the gate parasitic resistance is drastically reduced to 1/10 compared to the conventional configuration shown in FIG. In addition, the channel mobility is improved by about 20%. With these effects, the maximum transmission frequency f max that is an index of high-frequency operation is improved by about 2.5 times from 20 GHz to 50 GHz. FIG. 3 is a characteristic diagram showing the relationship between the gate resistance and the maximum transmission frequency. The reason why the value is lower than the value expected in the above formulas (1) and (2) is that the elements are limited to elements other than the parameters included in these approximate formulas.

従来では、ゲート電極がポリサイドからなるため、ゲート寄生抵抗はシート抵抗にして１０Ω／□前後であり、特に最大発信周波数は２０ＧＨｚに留まっていた。本実施形態のアルミニウム置換技術により、ゲート寄生抵抗をシート抵抗にして０．２Ω／□と従来の１／５０に低減することができる。これにより、最大発信周波数は５０ＧＨｚと格段に向上する。従来の構造では、２ＧＨｚが使用周波数の限界であったが、本実施形態により５ＧＨｚ帯における各無線装置に適用することが可能となる。   Conventionally, since the gate electrode is made of polycide, the gate parasitic resistance is about 10Ω / □ as a sheet resistance, and the maximum transmission frequency is particularly limited to 20 GHz. With the aluminum replacement technique of this embodiment, the gate parasitic resistance can be reduced to 0.2Ω / □, which is a sheet resistance, to 1/50 of the conventional value. Thereby, the maximum transmission frequency is remarkably improved to 50 GHz. In the conventional structure, 2 GHz is the limit of the use frequency, but according to the present embodiment, it can be applied to each wireless device in the 5 GHz band.

以上説明したように、本実施形態によれば、ｆmaxと電力利得の双方を向上させ、携帯電話や無線ＬＡＮに代表される高周波電力増幅器の基本素子として、高効率で高周波動作を可能とするＬＤＭＯＳトランジスタが実現する。 As described above, according to the present embodiment, both f max and power gain are improved, and high-frequency operation is enabled with high efficiency as a basic element of a high-frequency power amplifier typified by a mobile phone or a wireless LAN. An LDMOS transistor is realized.

（第２の実施形態）
ここでは、第１の実施形態と同様にＬＤＭＯＳトランジスタの構成及びその製造方法を開示するが、更にシールド層を製造工程を増加することなく形成する点で相違する。 (Second Embodiment)
Here, the configuration of the LDMOS transistor and the manufacturing method thereof are disclosed in the same manner as in the first embodiment, but it is different in that the shield layer is further formed without increasing the manufacturing process.

図４及び図５は、第２の実施形態によるＬＤＭＯＳトランジスタの製造方法を工程順に示す概略断面図である。
先ず、図４（ａ）に示すように、ｐ-／ｐ+／ｐ-型のシリコン半導体基板１上に所定のフォトマスク（不図示）を形成し、これをマスクとして半導体基板１の表層にｐ型不純物、ここではホウ素（Ｂ）を加速エネルギー６０ｋｅＶ、ドーズ量２×１０15／ｃｍ2の条件でイオン注入し、前記フォトマスクを灰化処理等により除去した後、半導体基板１に１１００℃で３０分間の熱処理を加えることにより、基板コンタクト層２を形成する。 4 and 5 are schematic cross-sectional views illustrating the method of manufacturing the LDMOS transistor according to the second embodiment in the order of steps.
First, as shown in FIG. 4A, a predetermined photomask (not shown) is formed on a p − / p + / p − type silicon semiconductor substrate 1 and used as a mask on the surface layer of the semiconductor substrate 1. A p-type impurity, here boron (B), is ion-implanted under the conditions of an acceleration energy of 60 keV and a dose of 2 × 10 15 / cm 2 , and the photomask is removed by ashing or the like. The substrate contact layer 2 is formed by applying a heat treatment for 30 minutes.

続いて、図４（ｂ）に示すように、熱酸化法により半導体基板１の表面に膜厚１０ｎｍ程度のゲート絶縁膜３を形成する。引き続き、シリコン半導体基板１上に所定のフォトマスク（不図示）を形成し、半導体基板１の表層にｎ型不純物、ここではリン（Ｐ）を加速エネルギー１２０ｋｅＶ、ドーズ量２×１０15／ｃｍ2の条件でイオン注入し、前記フォトマスクを灰化処理等により除去した後、１０００℃で３０分間の熱処理を半導体基板１に加えることにより、ｎ+ドレインコンタクト層５を形成する。 Subsequently, as shown in FIG. 4B, a gate insulating film 3 having a thickness of about 10 nm is formed on the surface of the semiconductor substrate 1 by a thermal oxidation method. Subsequently, a predetermined photomask (not shown) is formed on the silicon semiconductor substrate 1, and an n-type impurity, here phosphorus (P), is applied to the surface layer of the semiconductor substrate 1 with an acceleration energy of 120 keV and a dose of 2 × 10 15 / cm 2. After the ion implantation is performed under the above conditions and the photomask is removed by ashing or the like, a heat treatment at 1000 ° C. for 30 minutes is applied to the semiconductor substrate 1 to form the n + drain contact layer 5.

続いて、シリコン半導体基板１上に所定のフォトマスク（不図示）を形成し、半導体基板１の表層にｎ型不純物、ここではリン（Ｐ）を加速エネルギー６０ｋｅＶ、ドーズ量３×１０12／ｃｍ2の条件でイオン注入し、前記フォトマスクを灰化処理等により除去した後、９５０℃で３０分間の熱処理を半導体基板１に加えることにより、ｎードリフト層８を形成する。 Subsequently, a predetermined photomask (not shown) is formed on the silicon semiconductor substrate 1, and an n-type impurity, here phosphorus (P), is applied to the surface layer of the semiconductor substrate 1 with an acceleration energy of 60 keV and a dose of 3 × 10 12 / cm. After ion implantation under the condition 2 and removing the photomask by ashing or the like, an n-drift layer 8 is formed by applying a heat treatment at 950 ° C. for 30 minutes to the semiconductor substrate 1.

続いて、図４（ｃ）に示すように、ＣＶＤ法により多結晶シリコン膜４を堆積し、フォトリソグラフィー及びそれに続くドライエッチングにより多結晶シリコン膜４及びこれと隣接する多結晶シリコン膜３１を同時形成する。   Subsequently, as shown in FIG. 4C, a polycrystalline silicon film 4 is deposited by a CVD method, and the polycrystalline silicon film 4 and the polycrystalline silicon film 31 adjacent thereto are simultaneously formed by photolithography and subsequent dry etching. Form.

引き続き、シリコン半導体基板１上に所定のフォトマスク（不図示）を形成し、多結晶シリコン膜４の片側のみにおける半導体基板１の表層にｐ型不純物、ここではホウ素（Ｂ）を加速エネルギー３０ｋｅＶ、ドーズ量２×１０13／ｃｍ2の条件でイオン注入し、前記フォトマスクを灰化処理等により除去した後、半導体基板１に１０００℃で３０分間の熱処理を加えることにより、ｐ-チャネル拡散層６を形成する。 Subsequently, a predetermined photomask (not shown) is formed on the silicon semiconductor substrate 1, and a p-type impurity, here boron (B), is applied to the surface layer of the semiconductor substrate 1 only on one side of the polycrystalline silicon film 4, with an acceleration energy of 30 keV, After ion implantation under the condition of a dose amount of 2 × 10 13 / cm 2 , the photomask is removed by ashing or the like, and then the semiconductor substrate 1 is subjected to a heat treatment at 1000 ° C. for 30 minutes, whereby a p − channel diffusion layer is obtained. 6 is formed.

続いて、図４（ｄ）に示すように、シリコン半導体基板１上に所定のフォトマスク（不図示）を形成し、半導体基板１の表層にｎ型不純物、ここでは砒素（Ａｓ）を加速エネルギー３０ｋｅＶ、ドーズ量３×１０15／ｃｍ2の条件でイオン注入し、前記フォトマスクを灰化処理等により除去した後、９００℃で３０分間の熱処理を半導体基板１に加えることにより、ｎ+ソース拡散層７を形成する。 Subsequently, as shown in FIG. 4D, a predetermined photomask (not shown) is formed on the silicon semiconductor substrate 1, and an n-type impurity, here arsenic (As), is accelerated on the surface layer of the semiconductor substrate 1. Ion implantation is performed under the conditions of 30 keV and a dose of 3 × 10 15 / cm 2 , the photomask is removed by ashing or the like, and then a heat treatment at 900 ° C. for 30 minutes is applied to the semiconductor substrate 1 so that n + source A diffusion layer 7 is formed.

続いて、図４（ｅ）に示すように、半導体基板１上に多結晶シリコン膜４，３１を覆うように、ＣＶＤ法によりシリコン酸化膜を膜厚６００ｎｍ程度に堆積し、層間絶縁膜９を形成する。このとき、層間絶縁膜９の多結晶シリコン膜４，３１の上部に相当する部分が他の部分より２００ｎｍ程度盛り上がる。   Subsequently, as shown in FIG. 4E, a silicon oxide film is deposited to a thickness of about 600 nm by the CVD method so as to cover the polycrystalline silicon films 4 and 31 on the semiconductor substrate 1, and the interlayer insulating film 9 is formed. Form. At this time, the portion corresponding to the upper portion of the polycrystalline silicon films 4 and 31 of the interlayer insulating film 9 is raised by about 200 nm from the other portions.

続いて、図４（ｆ）に示すように、層間絶縁膜９の表面を多結晶シリコン膜４，３１の上面が露出するまで化学機械研磨（ＣＭＰ）法により研磨する。通常、多結晶シリコン膜とアルミニウムとを反応させる部分の絶縁膜を取り除くときには、フォトエッチングを用いるのが一般的である。その場合、フォトリソグラフィーの位置合わせズレにより多結晶シリコン膜の上部以外の絶縁膜がエッチングされてしまい、良好なデバイス構造が得られない。本実施形態では、上述のようにＣＭＰ法を用いることにより、フォトエッチングを要することなく自己整合的に多結晶シリコン膜４，３１の上面を露出させることができる。なお、ＣＭＰ法の替わりに、層間絶縁膜９の多結晶シリコン膜４，３１の上部に相当する部位を一様にエッチングする方法を用いても良い。   Subsequently, as shown in FIG. 4F, the surface of the interlayer insulating film 9 is polished by a chemical mechanical polishing (CMP) method until the upper surfaces of the polycrystalline silicon films 4 and 31 are exposed. Usually, photo-etching is generally used to remove the insulating film where the polycrystalline silicon film reacts with aluminum. In that case, an insulating film other than the upper part of the polycrystalline silicon film is etched due to misalignment of photolithography, and a good device structure cannot be obtained. In the present embodiment, by using the CMP method as described above, the upper surfaces of the polycrystalline silicon films 4 and 31 can be exposed in a self-aligned manner without requiring photoetching. Instead of the CMP method, a method of uniformly etching portions corresponding to the upper portions of the polycrystalline silicon films 4 and 31 of the interlayer insulating film 9 may be used.

続いて、図５（ａ）に示すように、層間絶縁膜９にフォトリソグラフィー及びそれに続くドライエッチングを施し、ｎ+ドレインコンタクト層５の表面の一部を露出させるドレインコンタクト孔１０と、ｎ+ソース拡散層７の表面の一部及び基板コンタクト層２の表面の一部を露出させるソースコンタクト孔１１をそれぞれ形成する。 Subsequently, as shown in FIG. 5 (a), subjected to photolithography and the subsequent dry etching the interlayer insulating film 9, a drain contact hole 10 exposing a portion of the n + drain contact layer 5 of the surface, n + Source contact holes 11 are formed to expose part of the surface of the source diffusion layer 7 and part of the surface of the substrate contact layer 2.

引き続き、ドレインコンタクト孔１０の内壁面及びソースコンタクト孔１１の内壁面を覆うように、層間絶縁膜９上にＴｉＮ膜を成膜し、下地膜（バリアメタル膜）１２を形成する。   Subsequently, a TiN film is formed on the interlayer insulating film 9 so as to cover the inner wall surface of the drain contact hole 10 and the inner wall surface of the source contact hole 11, and a base film (barrier metal film) 12 is formed.

ここで従来より、バリアメタル膜はコンタクト孔の部分でアルミニウムとシリコンとの反応を防止するバリアメタルとして広く用いられている。しかしながら本実施形態では、後述するように多結晶シリコンをアルミニウムに置換する部分ではバリアメタル膜が障害となる。そこで、図５（ｂ）に示すように、バリアメタル膜１２にフォトリソグラフィー及びそれに続くドライエッチングを施し、バリアメタル膜１２の多結晶シリコン膜４，３１の上面に相当する部位を除去し、当該上面のみを露出させる開孔３４を形成する。   Heretofore, the barrier metal film has been widely used as a barrier metal for preventing the reaction between aluminum and silicon at the contact hole. However, in this embodiment, as will be described later, the barrier metal film becomes an obstacle at the portion where polycrystalline silicon is replaced with aluminum. Therefore, as shown in FIG. 5B, the barrier metal film 12 is subjected to photolithography and subsequent dry etching to remove a portion corresponding to the upper surface of the polycrystalline silicon films 4 and 31 of the barrier metal film 12. An opening 34 exposing only the upper surface is formed.

続いて、図５（ｃ）に示すように、スパッタ法により全面にＡｌ膜１４を膜厚１０００ｎｍ程度に形成する。このとき、開孔３４のみにおいて多結晶シリコン膜４，３１とＡｌ膜１４とがそれぞれ直接接触することになる。そして、４５０℃で６０分間の熱処理により、多結晶シリコン膜４，３１とＡｌ膜１４とを置換反応させる。これにより、多結晶シリコン膜４，３１が吸い出されると共に、層間絶縁膜９の多結晶シリコン膜４，３１の形成部位にＡｌが侵入し、多結晶シリコン膜４，３１がＡｌ膜２０にそれぞれ置き換わる。このように、多結晶シリコン膜４，３１に相当する部分のみのバリアメタル膜１２を除去することにより、他の部分には置換反応が惹起されることなくゲート部分のみに多結晶シリコンとアルミニウムとの置換反応が惹起される。   Subsequently, as shown in FIG. 5C, an Al film 14 is formed to a thickness of about 1000 nm on the entire surface by sputtering. At this time, the polycrystalline silicon films 4 and 31 and the Al film 14 are in direct contact with each other only in the opening 34. Then, the polycrystalline silicon films 4 and 31 and the Al film 14 are subjected to a substitution reaction by heat treatment at 450 ° C. for 60 minutes. As a result, the polycrystalline silicon films 4 and 31 are sucked out, and Al enters the formation site of the polycrystalline silicon films 4 and 31 of the interlayer insulating film 9, and the polycrystalline silicon films 4 and 31 enter the Al film 20, respectively. Replace. In this way, by removing the barrier metal film 12 only in the portion corresponding to the polycrystalline silicon films 4 and 31, no substitution reaction is induced in the other portions, and the polycrystalline silicon and aluminum are formed only in the gate portion. The substitution reaction is initiated.

続いて、図５（ｄ）に示すように、Ａｌ膜１４及びバリアメタル膜１２をフォトリソグラフィー及びそれに続くドライエッチングによりパターニングし、バリアメタル膜１２を介してドレインコンタクト孔１０を埋め込むオーバーハング形状のドレイン電極２１と、バリアメタル膜１２を介してソースコンタクト孔１１を埋め込むオーバーハング形状のソース電極２２と、Ａｌ膜２０と上部電極１５とが接続された全てＡｌからなるオーバーハング形状のゲート電極２３と、Ａｌ膜２０と上部層３２とが接続された全てＡｌからなるオーバーハング形状のシールド層３３とをそれぞれ同時形成する。ここで、トランジスタのレイアウト上、ゲート電極２３とドレイン電極２１との距離はゲート電極２３とソース電極２２との距離よりも大きいため、ゲート電極２３の上部電極１５を、図示のようにドレイン電極２１側に偏って延在する非対称形状に形成する。このように、上記の置換反応に用いたＡｌ膜１４をそのまま残して各種電極に用いるため、製造プロセスが極めて容易となり、製造コストの低減にもつながる。   Subsequently, as shown in FIG. 5D, the Al film 14 and the barrier metal film 12 are patterned by photolithography and subsequent dry etching to form an overhang shape in which the drain contact hole 10 is embedded through the barrier metal film 12. A drain electrode 21, an overhang-shaped source electrode 22 that fills the source contact hole 11 through the barrier metal film 12, and an overhang-shaped gate electrode 23 made of all Al, in which the Al film 20 and the upper electrode 15 are connected. Then, an overhang-shaped shield layer 33 made of all Al, in which the Al film 20 and the upper layer 32 are connected, is simultaneously formed. Here, since the distance between the gate electrode 23 and the drain electrode 21 is larger than the distance between the gate electrode 23 and the source electrode 22 due to the layout of the transistor, the upper electrode 15 of the gate electrode 23 is connected to the drain electrode 21 as shown in the figure. It is formed in an asymmetrical shape that extends toward the side. Thus, since the Al film 14 used in the above substitution reaction is left as it is and used for various electrodes, the manufacturing process becomes extremely easy and the manufacturing cost is reduced.

しかる後、電極保護膜やボンディング部（共に不図示）等の形成を経て、本実施形態のＬＤＭＯＳトランジスタを完成させる。   Thereafter, an LDMOS transistor of this embodiment is completed through formation of an electrode protective film, a bonding portion (both not shown), and the like.

このように、本実施形態では、ゲート電極のパターンのほかにゲート電極とドレイン電極の間に更にシールド電極のパターンをフォトマスク内に設けることにより、全く工程を追加せずにシールド層３３を形成することができる。   As described above, in this embodiment, in addition to the gate electrode pattern, the shield layer 33 is formed without any additional process by providing a shield electrode pattern in the photomask between the gate electrode and the drain electrode. can do.

以上説明したように、本実施形態によれば、ｆmaxと電力利得の双方を向上させ、携帯電話や無線ＬＡＮに代表される高周波電力増幅器の基本素子として、シールド層の配設により高効率で更なる高周波動作を可能とするＬＤＭＯＳトランジスタが実現する。 As described above, according to the present embodiment, both f max and power gain are improved, and as a basic element of a high-frequency power amplifier typified by a mobile phone or a wireless LAN, the shield layer is provided with high efficiency. An LDMOS transistor capable of further high-frequency operation is realized.

以下、本発明の諸態様を付記としてまとめて記載する。   Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

（付記１）半導体基板と、
前記半導体基板の上方に形成されたゲート電極と、
前記ゲート電極の両側における前記半導体基板の表層に形成されてなる一対の不純物拡散層と、
前記ゲート電極と一方の前記不純物拡散層との間における前記半導体基板の表層に、前記不純物拡散層と同一の導電型として形成されてなるドリフト層と、
を含み、
前記ゲート電極は、アルミニウムを含む金属を材料としてオーバーハング形状に形成されてなることを特徴とする半導体装置。 (Appendix 1) a semiconductor substrate;
A gate electrode formed above the semiconductor substrate;
A pair of impurity diffusion layers formed on the surface layer of the semiconductor substrate on both sides of the gate electrode;
A drift layer formed on the surface layer of the semiconductor substrate between the gate electrode and one of the impurity diffusion layers and having the same conductivity type as the impurity diffusion layer;
Including
The semiconductor device, wherein the gate electrode is formed in an overhang shape using a metal containing aluminum as a material.

（付記２）前記ゲート電極は、その上部が他方の前記一方の前記不純物拡散層側に偏って延在する非対称形状とされてなることを特徴とする付記１に記載の半導体装置。   (Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the gate electrode has an asymmetrical shape in which an upper portion thereof extends to be biased toward the other impurity diffusion layer.

（付記３）前記半導体基板の上方に、前記各不純物拡散層と接続されるように形成された一対の電極を含み、
前記各電極は、前記ゲート電極と同一材料からなることを特徴とする付記１又は２に記載の半導体装置。 (Appendix 3) A pair of electrodes formed so as to be connected to the respective impurity diffusion layers above the semiconductor substrate,
The semiconductor device according to appendix 1 or 2, wherein each of the electrodes is made of the same material as the gate electrode.

（付記４）
前記ゲート電極及び前記各電極は、前記半導体基板上に形成された層間絶縁膜にその下部を埋設するように形成されており、
前記各電極は、前記層間絶縁膜との間に金属下地膜を介して形成されるとともに、前記ゲート電極は、前記層間絶縁膜と直接に接するように形成されていることを特徴とする付記３に記載の半導体装置。 (Appendix 4)
The gate electrode and each electrode are formed so as to bury the lower part in an interlayer insulating film formed on the semiconductor substrate,
Each electrode is formed between the interlayer insulating film and a metal base film, and the gate electrode is formed so as to be in direct contact with the interlayer insulating film. A semiconductor device according to 1.

（付記５）前記ゲート電極と一方の前記電極との間に、両者を隔てるように前記ゲート電極と同一材料により形成されてなるシールド層を含むことを特徴とする付記３又は４に記載の半導体装置。   (Additional remark 5) The semiconductor of Additional remark 3 or 4 characterized by including the shield layer formed by the same material as the said gate electrode so that both may be separated between the said gate electrode and one said electrode apparatus.

（付記６）半導体基板上にゲート絶縁膜を介して電極形状の多結晶シリコン膜を形成する工程と、
前記半導体基板に表層に不純物を導入して、一対の不純物拡散層及びドリフト層をそれぞれ形成する工程と、
前記多結晶シリコン膜を覆うように、前記半導体基板上に層間絶縁膜を形成する工程と、
前記層間絶縁膜の表層を除去して前記多結晶シリコン膜の上面を露出させる工程と、
前記各不純物拡散層の表面の一部をそれぞれ露出させるように、前記層間絶縁膜に開孔を形成する工程と、
前記各開孔を埋め込むように、前記層間絶縁膜上にアルミニウムを含む金属膜を形成する工程と、
多結晶シリコンとアルミニウムとを選択的に置換反応させ、前記層間絶縁膜内の前記多結晶シリコン膜の形成部位を前記金属膜の材料で充填する工程と、
前記金属膜を加工して、前記各不純物拡散層とそれぞれ接続されてなる一対の電極と、前記金属膜の材料で一体形成されてなるゲート電極とをそれぞれ形成する工程と
を含むことを特徴とする半導体装置の製造方法。 (Appendix 6) A step of forming an electrode-shaped polycrystalline silicon film on a semiconductor substrate via a gate insulating film;
Introducing impurities into a surface layer of the semiconductor substrate to form a pair of impurity diffusion layers and a drift layer,
Forming an interlayer insulating film on the semiconductor substrate so as to cover the polycrystalline silicon film;
Removing the surface layer of the interlayer insulating film to expose the upper surface of the polycrystalline silicon film;
Forming an opening in the interlayer insulating film so as to expose a part of the surface of each impurity diffusion layer;
Forming a metal film containing aluminum on the interlayer insulating film so as to embed each opening;
A step of selectively substituting polycrystalline silicon and aluminum, and filling the formation site of the polycrystalline silicon film in the interlayer insulating film with the material of the metal film;
Processing the metal film to form a pair of electrodes respectively connected to the impurity diffusion layers and a gate electrode formed integrally with the material of the metal film. A method for manufacturing a semiconductor device.

（付記７）前記各開孔を形成した後、前記金属膜を形成する前に、前記各開孔の内壁面を覆うように前記層間絶縁膜上に下地膜を形成する工程と、
前記下地膜の前記多結晶シリコン膜上に相当する部位のみを除去し、前記多結晶シリコン膜の上面を露出させる工程と
を更に含むことを特徴とする付記６に記載の半導体装置の製造方法。 (Appendix 7) A step of forming a base film on the interlayer insulating film so as to cover an inner wall surface of each opening after forming each opening and before forming the metal film;
The method of manufacturing a semiconductor device according to appendix 6, further comprising: removing only a portion of the base film corresponding to the polycrystalline silicon film to expose an upper surface of the polycrystalline silicon film.

（付記８）前記金属膜を加工する際に、少なくとも前記ゲート電極をオーバーハング形状に形成することを特徴とする付記６又は７に記載の半導体装置の製造方法。   (Supplementary note 8) The method for manufacturing a semiconductor device according to supplementary note 6 or 7, wherein when processing the metal film, at least the gate electrode is formed in an overhang shape.

（付記９）前記金属膜を加工する際に、前記ゲート電極をその上部が他方の前記一方の前記不純物拡散層側に偏って延在する非対称形状に形成することを特徴とする付記８に記載の半導体装置の製造方法。   (Supplementary note 9) The supplementary note 8, wherein when the metal film is processed, the gate electrode is formed in an asymmetric shape in which an upper portion thereof is biased and extends toward the other impurity diffusion layer. Semiconductor device manufacturing method.

（付記１０）前記金属膜を加工する際に、前記ゲート電極となる部位と一方の前記電極となる部位との間に、両者を隔てるシールド層を前記ゲート電極及び前記各電極と共に形成することを特徴とする付記６〜９のいずれか１項に記載の半導体装置の製造方法。   (Additional remark 10) When processing the said metal film, forming between the site | part used as the said gate electrode and the site | part used as the one said electrode together with the said gate electrode and each said electrode which forms both 10. The method for manufacturing a semiconductor device according to any one of appendices 6 to 9, which is characterized by the following.

（付記１１）前記多結晶シリコン膜を形成する際に、前記多結晶シリコン膜とともに、半導体基板上で当該多結晶シリコン膜と隣接する他の多結晶シリコン膜を形成し、
前記置換反応の際に、前記層間絶縁膜内の前記多結晶シリコン膜の形成部位とともに前記他の多結晶シリコン膜の形成部位をそれぞれ前記金属膜の材料で置換し、
前記金属膜を加工する際に、前記一対の電極及び前記ゲート電極とともに、前記金属膜の材料で一体形成されてなる前記シールド層を形成することを特徴とする付記１０に記載の半導体装置の製造方法。 (Appendix 11) When forming the polycrystalline silicon film, together with the polycrystalline silicon film, another polycrystalline silicon film adjacent to the polycrystalline silicon film is formed on a semiconductor substrate,
In the substitution reaction, the formation part of the polycrystalline silicon film in the interlayer insulating film and the formation part of the other polycrystalline silicon film are respectively replaced with the material of the metal film,
11. The manufacturing method of a semiconductor device according to appendix 10, wherein when the metal film is processed, the shield layer formed integrally with the metal film material is formed together with the pair of electrodes and the gate electrode. Method.

第１の実施形態によるＬＤＭＯＳトランジスタの製造方法を工程順に示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing method of the LDMOS transistor by 1st Embodiment in order of a process. 図１に引き続き、第１の実施形態によるＬＤＭＯＳトランジスタの製造方法を工程順に示す概略断面図である。FIG. 2 is a schematic cross-sectional view illustrating the manufacturing method of the LDMOS transistor according to the first embodiment in order of processes following FIG. 1. ゲート抵抗と最大発信周波数との関係を示す特性図である。It is a characteristic view which shows the relationship between gate resistance and a maximum transmission frequency. 第２の実施形態によるＬＤＭＯＳトランジスタの製造方法を工程順に示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing method of the LDMOS transistor by 2nd Embodiment to process order. 図４に引き続き、第２の実施形態によるＬＤＭＯＳトランジスタの製造方法を工程順に示す概略断面図である。FIG. 5 is a schematic cross-sectional view illustrating the manufacturing method of the LDMOS transistor according to the second embodiment in order of processes subsequent to FIG. 4. 従来のＬＤＭＯＳトランジスタの構成を示す概略断面図である。It is a schematic sectional drawing which shows the structure of the conventional LDMOS transistor.

符号の説明Explanation of symbols

１ シリコン半導体基板
２ 基板コンタクト層
３ ゲート絶縁膜
４，３１ 多結晶シリコン膜
５ ｎ+ドレインコンタクト層
６ ｐ-チャネル拡散層
７ ｎ+ソース拡散層
８ ｎードリフト層
９ 層間絶縁膜
１０ ドレインコンタクト孔
１１ ソースコンタクト孔
１２ 下地膜（バリアメタル膜）
１３，３４ 開孔
１４，２０ Ａｌ膜
１５ 上部電極
２１ ドレイン電極
２２ ソース電極
２３ ゲート電極
３２ 上部層
３３ シールド層 1 silicon semiconductor substrate 2 substrate contact layer 3 gate insulating film 4, 31 polycrystalline silicon film 5 n + drain contact layer 6 p - channel diffusion layer 7 n + source diffusion layer 8 n over drift layer 9 interlayer insulating film 10 a drain contact hole 11 Source contact hole 12 Base film (barrier metal film)
13, 34 Opening 14, 20 Al film 15 Upper electrode 21 Drain electrode 22 Source electrode 23 Gate electrode 32 Upper layer 33 Shield layer

Claims (10)

半導体基板と、
前記半導体基板の上方に形成されたゲート電極と、
前記ゲート電極の両側における前記半導体基板の表層に形成されてなる一対の不純物拡散層と、
前記ゲート電極と一方の前記不純物拡散層との間における前記半導体基板の表層に、前記不純物拡散層と同一の導電型として形成されてなるドリフト層と、
を含み、
前記ゲート電極は、アルミニウムを含む金属を材料としてオーバーハング形状に形成されてなることを特徴とする半導体装置。 A semiconductor substrate;
A gate electrode formed above the semiconductor substrate;
A pair of impurity diffusion layers formed on the surface layer of the semiconductor substrate on both sides of the gate electrode;
A drift layer formed on the surface layer of the semiconductor substrate between the gate electrode and one of the impurity diffusion layers and having the same conductivity type as the impurity diffusion layer;
Including
The semiconductor device, wherein the gate electrode is formed in an overhang shape using a metal containing aluminum as a material. 前記ゲート電極は、その上部が他方の前記一方の前記不純物拡散層側に偏って延在する非対称形状とされてなることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the gate electrode has an asymmetrical shape in which an upper portion thereof extends to be biased toward the other impurity diffusion layer. 前記半導体基板の上方に、前記各不純物拡散層と接続されるように形成された一対の電極を含み、
前記各電極は、前記ゲート電極と同一材料からなることを特徴とする請求項１又は２に記載の半導体装置。 A pair of electrodes formed to be connected to each of the impurity diffusion layers above the semiconductor substrate;
The semiconductor device according to claim 1, wherein each of the electrodes is made of the same material as the gate electrode. 前記ゲート電極及び前記各電極は、前記半導体基板上に形成された層間絶縁膜にその下部を埋設するように形成されており、
前記各電極は、前記層間絶縁膜との間に金属下地膜を介して形成されるとともに、前記ゲート電極は、前記層間絶縁膜と直接に接するように形成されていることを特徴とする請求項３に記載の半導体装置。 The gate electrode and each electrode are formed so as to bury the lower part in an interlayer insulating film formed on the semiconductor substrate,
The electrode is formed between the interlayer insulating film and a metal base film, and the gate electrode is formed to be in direct contact with the interlayer insulating film. 3. The semiconductor device according to 3. 前記ゲート電極と一方の前記電極との間に、両者を隔てるように前記ゲート電極と同一材料により形成されてなるシールド層を含むことを特徴とする請求項３又は４に記載の半導体装置。   5. The semiconductor device according to claim 3, further comprising a shield layer formed of the same material as that of the gate electrode so as to separate the gate electrode and the one electrode. 半導体基板上にゲート絶縁膜を介して電極形状の多結晶シリコン膜を形成する工程と、
前記半導体基板に表層に不純物を導入して、一対の不純物拡散層及びドリフト層をそれぞれ形成する工程と、
前記多結晶シリコン膜を覆うように、前記半導体基板上に層間絶縁膜を形成する工程と、
前記層間絶縁膜の表層を除去して前記多結晶シリコン膜の上面を露出させる工程と、
前記各不純物拡散層の表面の一部をそれぞれ露出させるように、前記層間絶縁膜に開孔を形成する工程と、
前記各開孔を埋め込むように、前記層間絶縁膜上にアルミニウムを含む金属膜を形成する工程と、
多結晶シリコンとアルミニウムとを選択的に置換反応させ、前記層間絶縁膜内の前記多結晶シリコン膜の形成部位を前記金属膜の材料で充填する工程と、
前記金属膜を加工して、前記各不純物拡散層とそれぞれ接続されてなる一対の電極と、 前記金属膜の材料で一体形成されてなるゲート電極とをそれぞれ形成する工程と
を含むことを特徴とする半導体装置の製造方法。 Forming an electrode-shaped polycrystalline silicon film on a semiconductor substrate via a gate insulating film;
Introducing impurities into a surface layer of the semiconductor substrate to form a pair of impurity diffusion layers and a drift layer,
Forming an interlayer insulating film on the semiconductor substrate so as to cover the polycrystalline silicon film;
Removing the surface layer of the interlayer insulating film to expose the upper surface of the polycrystalline silicon film;
Forming an opening in the interlayer insulating film so as to expose a part of the surface of each impurity diffusion layer;
Forming a metal film containing aluminum on the interlayer insulating film so as to embed each opening;
A step of selectively substituting polycrystalline silicon and aluminum, and filling the formation site of the polycrystalline silicon film in the interlayer insulating film with the material of the metal film;
Processing the metal film to form a pair of electrodes respectively connected to the impurity diffusion layers and a gate electrode formed integrally with the material of the metal film. A method for manufacturing a semiconductor device. 前記各開孔を形成した後、前記金属膜を形成する前に、前記各開孔の内壁面を覆うように前記層間絶縁膜上に下地膜を形成する工程と、
前記下地膜の前記多結晶シリコン膜上に相当する部位のみを除去し、前記多結晶シリコン膜の上面を露出させる工程と
を更に含むことを特徴とする請求項６に記載の半導体装置の製造方法。 Forming a base film on the interlayer insulating film so as to cover an inner wall surface of each opening after forming each opening and before forming the metal film;
The method for manufacturing a semiconductor device according to claim 6, further comprising: removing only a portion of the base film corresponding to the polycrystalline silicon film to expose an upper surface of the polycrystalline silicon film. . 前記金属膜を加工する際に、少なくとも前記ゲート電極をオーバーハング形状に形成することを特徴とする請求項６又は７に記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 6, wherein at least the gate electrode is formed in an overhang shape when the metal film is processed. 前記金属膜を加工する際に、前記ゲート電極をその上部が他方の前記一方の前記不純物拡散層側に偏って延在する非対称形状に形成することを特徴とする請求項８に記載の半導体装置の製造方法。   9. The semiconductor device according to claim 8, wherein, when the metal film is processed, the gate electrode is formed in an asymmetric shape in which an upper portion of the gate electrode extends toward the one impurity diffusion layer side of the other. Manufacturing method. 前記金属膜を加工する際に、前記ゲート電極となる部位と一方の前記電極となる部位との間に、両者を隔てるシールド層を前記ゲート電極及び前記各電極と共に形成することを特徴とする請求項６〜９のいずれか１項に記載の半導体装置の製造方法。   When the metal film is processed, a shield layer is formed between the part to be the gate electrode and one part to be the electrode together with the gate electrode and each electrode. Item 10. The method for manufacturing a semiconductor device according to any one of Items 6 to 9.
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