CN103377899A - Metal grid electrode manufacturing method and CMOS manufacturing method - Google Patents
Metal grid electrode manufacturing method and CMOS manufacturing method Download PDFInfo
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Abstract
The invention discloses a metal grid electrode manufacturing method and a CMOS manufacturing method based on the metal grid electrode manufacturing method. The metal grid electrode manufacturing method includes the steps of providing a substrate which is provided with a pseudo grid structure, removing a pseudo polycrystalline silicon grid electrode to form a groove, sequentially depositing a metal work function layer and an isolating layer in the groove, depositing a polycrystalline silicon layer, filling the groove with the polycrystalline silicon layer, depositing an A1 metal layer on the polycrystalline silicon layer, conducting thermal annealing treatment so that the A1 metal layer and the polycrystalline silicon layer can be interchangeable and an A1 electrode can be formed, and removing the replaced polycrystalline silicon layer and A1 metal located outside the groove so that a metal grid electrode can be formed. According to the metal grid electrode manufacturing method and the CMOS manufacturing method, in the manufacturing process of smaller than 32nm, gaps in the A1 electrode can be prevented, and further the performance of semiconductor devices is prevented from being lowered.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly the manufacture method of a kind of manufacture method of metal gates of semiconductor device and CMOS (Complementary Metal-Oxide-Semiconductor, complementary metal oxide semiconductors (CMOS)).
Background technology
Along with the characteristic size (CD in the semiconductor fabrication process, constantly reducing Critical Dimension), the high-dielectric constant metal grid utmost point (HKMG) has been replaced original polysilicon gate, and is widely used in 45nm and 32nm and more in the process node of small-feature-size.The introducing of the high-dielectric constant metal grid utmost point, solved the technology barrier that traditional grid faces, as reduce EOT (Equivalent Oxide Thickness, the equivalence gate oxide thickness) and the reduction Vt (threshold voltage), reduce transistor drain current etc., and then improved the performance of semiconductor device.
Existing a kind of method of metal gates of making is referring to figs. 1 through Fig. 4.
As shown in Figure 1, substrate 1 is provided, such as N-type or P type substrate, be formed with pseudo-grid structure at this substrate 1, this puppet grid structure is included in boundary layer 2, high-k (High-K) gate dielectric layer 3 and the dummy poly grid 4 that forms successively on the described substrate 1, be formed with side wall 5 along described pseudo-grid structure both sides, on the substrate 1 in described side wall 5 outsides, also be formed with interlayer dielectric layer (ILD, Inter LayerDielectric) 6.
As shown in Figure 2, remove described dummy poly grid 4 and form grooves, and in groove successively plated metal work function layer 7 and separator 8.Metal work function layer 7 in this step and separator 8, that directly the body structure surface after forming groove deposits, therefore when in groove, forming metal work function layer 7 and separator 8, be in groove place in addition, such as top metal work function layer 7 and the separator 8 of also can forming of interlayer dielectric layer 6 among Fig. 2.In follow-up technique, being deposited on groove metal work function layer 7 and separator 8 in addition can be removed.
As shown in Figure 3, continue depositing Al (aluminium) metal level 9 and utilize Al metal level 9 that groove is filled up.Similar with separator 8 with metal work function layer 7 shown in Figure 2, Al metal level 9 is that directly the body structure surface after forming metal work function layer 7 and separator 8 deposits, and therefore is in groove place in addition and also can forms Al metal level 9.
As shown in Figure 4, remove Al metal level 9, the separator 8 beyond the groove and the metal work function layer 7 beyond the groove beyond the groove, thereby only keep Al metal level 9 in the groove to form the Al metal electrode.Adopt cmp (CMP) method in this step, in Al metal level 9, the separator 8 beyond the groove and the groove metal work function layer 7 in addition of the method beyond removing groove, also make the flattening surface of this structure.Through after this step, be in groove and jointly consisted of metal gate structure with interior Al metal level 9, separator 8 and metal work function layer 7.
In the prior art, as shown in Figure 3, after plated metal work function layer 7 and separator 8, just directly carry out the deposition of Al metal level 9.When semiconductor is made technique and is in 45nm and 32nm node, the groove opening width during the depositing Al metal more than 10nm, even this moment groove depth-to-width ratio can satisfy the deposition of Al metal, can in groove, not form the space.But, when the characteristic size of semiconductor fabrication process further reduces, thing followed problem is that the width of this groove also reduces thereupon, when this groove opening width less than to a certain degree (such as 10nm time), the Al metal directly deposits to and becomes very difficult in the groove.At this moment, because the diminishing of groove width, the Al metal that takes the lead in being deposited on the opening part of groove can make groove opening narrow down too early even be closed, further deposits in the groove and hinder the Al metal, and then produce the space in the Al metal electrode.The appearance in space has caused the decline of Al metal electrode conductive capability even has opened circuit, and then has reduced performance even so that the semiconductor device failure of semiconductor device.
Summary of the invention
In view of this, the invention provides a kind of metal gates manufacture method and CMOS manufacture method, avoid occurring the space in the Al metal electrode, prevent the reduction of performance of semiconductor device.
Technical scheme of the present invention is achieved in that
A kind of metal gates manufacture method comprises:
The substrate that is formed with pseudo-grid structure is provided, described pseudo-grid structure is included in boundary layer, high-dielectric-coefficient grid medium layer and the dummy poly grid that forms successively on the described substrate, be formed with side wall along described pseudo-grid structure both sides, on the substrate in the described side wall outside, also be formed with interlayer dielectric layer;
Remove described dummy poly grid and form groove, and in groove successively plated metal work function layer and separator;
The deposit spathic silicon layer also utilizes described polysilicon layer that groove is filled up;
Depositing Al metal level on described polysilicon layer;
Carry out thermal annealing and process, so that described Al metal level and polysilicon layer are replaced mutually, form the Al electrode;
Remove polysilicon layer and the Al metal that is in outside the groove after replacing, to form metal gates.
Further, on described polysilicon layer, after the depositing Al metal level, carry out also comprising before the thermal annealing processing:
Titanium deposition Ti metal level on described Al metal level.
Further, described thermal annealing temperature is 300～500 ℃, and annealing time is 10～60 minutes, and annealing atmosphere is N2.
Further, described polysilicon layer adopts the boiler tube process to make, and the temperature when adopting the boiler tube process is 300～500 ℃.
Further, described Al metal level adopts ald ALD, CVD, physical vapour deposition (PVD) PVD or electroplates EP method deposition.
Further, employing cmp CMP method is removed the polysilicon layer and the Al metal that is in outside the groove after replacing.
A kind of CMOS manufacture method comprises:
Substrate is provided, be divided into PMOS district and nmos area by the shallow trench isolation STI on the described substrate, be formed with the pseudo-grid structure in PMOS district in the described PMOS district, the pseudo-grid structure in described PMOS district is included in the PMOS regional boundary surface layer that forms successively on the described substrate, PMOS district high-dielectric-coefficient grid medium floor and PMOS district dummy poly grid, be formed with PMOS district side wall along pseudo-grid structure both sides, described PMOS district, be formed with the pseudo-grid structure of nmos area on the described nmos area, the pseudo-grid structure of described nmos area is included in the nmos area boundary layer that forms successively on the described substrate, nmos area high-dielectric-coefficient grid medium layer and nmos area dummy poly grid, be formed with the nmos area side wall along the pseudo-grid structure of described nmos area both sides, on the substrate in described PMOS district's side wall and the nmos area side wall outside, also be formed with interlayer dielectric layer;
Remove dummy poly grid formation PMOS district, PMOS district groove, and in PMOS district groove, deposit successively PMOS district metal work function floor and PMOS separates absciss layer;
The deposit spathic silicon floor also utilizes this polysilicon layer that PMOS district groove is filled up;
Depositing Al metal level on described polysilicon layer;
Carry out thermal annealing and process, so that described Al metal level and polysilicon layer are replaced mutually, form PMOS district Al electrode;
Remove polysilicon layer and the Al metal that is in outside the PMOS district groove after replacing, to form PMOS district metal gates;
Remove nmos area dummy poly grid and form the nmos area groove, and in the nmos area groove, deposit successively nmos area metal work function layer and nmos area separator;
The deposit spathic silicon layer also utilizes this polysilicon layer that the nmos area groove is filled up;
Depositing Al metal level on described polysilicon layer;
Carry out thermal annealing and process, so that described Al metal level and polysilicon layer are replaced mutually, form nmos area Al electrode;
Remove polysilicon layer and the Al metal that is in outside the nmos area groove after replacing, to form the nmos area metal gates.
Further, on described polysilicon layer, after the depositing Al metal level, carry out thermal annealing and process, so that described Al metal level and polysilicon layer are replaced mutually, form PMOS district Al electrode and also comprise before:
Titanium deposition Ti metal level on described Al metal level.
Further, on described polysilicon layer, after the depositing Al metal level, carry out thermal annealing and process, so that described Al metal level and polysilicon layer are replaced mutually, form nmos area Al electrode and also comprise before:
Titanium deposition Ti metal level on described Al metal level.
Further, described polysilicon layer adopts the boiler tube process to make, and the temperature when adopting the boiler tube process is 300～500 ℃.
Further, described thermal annealing temperature is 300～500 ℃, and annealing time is 10～60 minutes, and annealing atmosphere is N
2
Further, described PMOS district metal work function floor is individual layer or sandwich construction; When described PMOS district metal work function floor was single layer structure, material was titanium nitride TiN or tantalum nitride TaN, adopted the preparation of ald ALD method or physical vapour deposition (PVD) PVD method; When described PMOS district metal work function floor is sandwich construction, adopt the alternately described sandwich construction of stack formation of TiN layer and TaN layer, wherein said TiN layer adopts ALD method or the preparation of PVD method, and described TaN layer adopts ALD method or the preparation of PVD method; Described PMOS district metal work function layer thickness is
Further, described nmos area metal work function layer is individual layer or sandwich construction; When described nmos area metal work function layer was single layer structure, material was titanium-aluminium alloy TiAl, adopted the preparation of ALD method or PVD method; When described nmos area metal work function layer is sandwich construction, adopt the alternately described sandwich construction of stack formation of Ti layer and Al layer, perhaps adopt the alternately described sandwich construction of stack formation of TiN layer and Al layer, wherein said Ti layer adopts ALD method or the preparation of PVD method, described Al layer adopts ALD method or the preparation of PVD method, described TiN layer adopts ALD method or the preparation of PVD method, and described nmos area metal work function layer thickness is
Further, described PMOS separates absciss layer and the nmos area insolated layer materials is TaN or TiN, adopts the preparation of ALD method or PVD method, and PMOS separates absciss layer and the nmos area separation layer thickness is
In the preparation process of polysilicon, silane gas arrives in the groove, then is decomposed to form polysilicon and hydrogen in groove, the polysilicon that is decomposed to form just can Direct precipitation among groove.And in the existing Al electrode manufacturing method, the Al metal is when deposition, can't enter groove with the form of gaseous state, and further in groove, form the Al metal level, mostly the Al metal is to spread and in the groove that arrives at the device epitaxial surface, when the groove depth-to-width ratio is excessive, in the time of the Al metal can occurring and not yet fill up groove, the Al metal that groove has just been piled up by notch is shut, and then produces the space in groove.
Because the preparation of above-mentioned polysilicon is different with the sedimentation mechanism of Al metal, therefore, when making groove produce the space when the depth-to-width ratio of groove so that the Al metal can't deposit in the groove fully, adopt the boiler tube process, in the less groove of the width that polysilicon deposition can't be deposited to fully to the Al metal, and in groove, can not form the space.Utilize thermal annealing to process, can replace so that Al metal level and polysilicon layer produce mutually, and thermal annealing is processed also can eliminate the defective that produces in the replacement process, therefore in groove through formed Al electrode after replacing, the space in the time of in groove depositing Al metal just can not occurring directly.So method of the present invention has been avoided in the semiconductor device production process, the generation in space in the Al electrode of metal gates.
Metal gates manufacture method provided by the invention and CMOS manufacture method have been avoided the generation in space in the Al electrode, and then prevent the reduction of performance of semiconductor device.
Description of drawings
Fig. 1 for the semiconductor device substrates that provides among prior art and the present invention with and the upper pseudo-grid structure that forms;
Fig. 2 is that structure shown in Figure 1 is removed the semiconductor device structure that forms behind dummy poly grid and plated metal work function layer and the separator in prior art and the present invention;
Fig. 3 is the semiconductor device structure that structure shown in Figure 2 forms behind the depositing Al metal level in the prior art;
Fig. 4 is the in the prior art semiconductor device structure through forming after the CMP of structure shown in Figure 3;
Fig. 5 is metal gates manufacture method embodiment flow chart of the present invention;
Fig. 6 is the semiconductor device structure that structure shown in Figure 2 forms afterwards at the deposit spathic silicon layer;
Fig. 7 is the semiconductor device structure that structure shown in Figure 6 forms behind the depositing Al metal level;
Fig. 8 is the semiconductor device structure that structure shown in Figure 7 forms behind the depositing Ti metal level;
Fig. 9 is for carrying out the schematic diagram of thermal annealing to structure shown in Figure 8;
Figure 10 is the semiconductor device structure through forming behind the thermal annealing of Fig. 9;
Figure 11 is the semiconductor device structure of structure shown in Figure 10 through forming after the CMP;
Figure 12 is CMOS manufacture method embodiment flow chart of the present invention;
Figure 13 for the CMOS substrate that provides among the present invention with and the upper pseudo-grid structure that forms;
Figure 14 is that structure shown in Figure 13 is removed PMOS district's dummy poly grid and deposited PMOS district metal work function floor and PMOS separates the CMOS structure that forms behind the absciss layer;
Figure 15 is the CMOS structure that the deposit spathic silicon layer forms afterwards on structure shown in Figure 14;
The CMOS structure of Figure 16 for behind depositing Al metal level on the structure shown in Figure 15, forming;
The CMOS structure of Figure 17 for behind depositing Ti metal level on the structure shown in Figure 16, forming;
Figure 18 is for carrying out the schematic diagram of thermal annealing to structure shown in Figure 17;
Figure 19 is the CMOS structure through forming behind the thermal annealing shown in Figure 180;
The CMOS structure of Figure 20 for structure shown in Figure 19 being carried out form after the CMP;
Figure 21 be structure shown in Figure 20 remove nmos area dummy poly grid and deposit nmos area metal work function layer and the nmos area separator after the CMOS structure that forms;
Figure 22 is the CMOS structure that the deposit spathic silicon layer forms afterwards on structure shown in Figure 21;
The CMOS structure of Figure 23 for behind depositing Al metal level on the structure shown in Figure 22, forming;
The CMOS structure of Figure 24 for behind depositing Ti metal level on the structure shown in Figure 23, forming;
Figure 25 is for carrying out the schematic diagram of thermal annealing to structure shown in Figure 24;
Figure 26 is the CMOS structure through forming behind the thermal annealing shown in Figure 25;
The CMOS structure of Figure 27 for structure shown in Figure 26 being carried out form after the CMP.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
As shown in Figure 5, be the embodiment flow chart of metal gates manufacture method of the present invention, the method comprises:
Step 1: the substrate that is formed with pseudo-grid structure is provided, described pseudo-grid structure is included in boundary layer, high-dielectric-coefficient grid medium layer and the dummy poly grid that forms successively on the described substrate, be formed with side wall along described pseudo-grid structure both sides, on the substrate in the described side wall outside, also be formed with interlayer dielectric layer;
Step 2: remove described dummy poly grid and form groove, and in groove successively plated metal work function layer and separator;
Step 3: the deposit spathic silicon layer also utilizes described polysilicon layer that groove is filled up;
Step 4: depositing Al metal level on described polysilicon layer;
Step 5: titanium deposition Ti metal level on described Al metal level;
Step 6: carry out thermal annealing and process, so that described Al metal level and polysilicon layer are replaced mutually, form the Al electrode;
Step 7: remove polysilicon layer and the Al metal that is in outside the groove after replacing, to form metal gates.
Below in conjunction with accompanying drawing above steps is specifically introduced.
Step 1: as shown in Figure 1, the substrate 1 that is formed with pseudo-grid structure is provided, described pseudo-grid structure is included in boundary layer 2, high-dielectric-coefficient grid medium layer 3 and the dummy poly grid 4 that forms successively on the described substrate 1, be formed with side wall 5 along described pseudo-grid structure both sides, on the substrate 1 in described side wall 5 outsides, also be formed with interlayer dielectric layer 6.
Wherein, substrate 1 can comprise any can be as the basic material that makes up semiconductor device thereon, such as silicon substrate, perhaps make silicon substrate or the silicon-on-insulator substrate of an isolated area, substrate 1 can be N-type substrate or P type substrate; Boundary layer 2 can be chosen as SiO
2(silicon dioxide) material; The material of high-dielectric-coefficient grid medium layer 3 includes but not limited to high-k (High-K) materials such as hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum and lead niobate zinc; The material of side wall 5 includes but not limited to nitride or the oxide material of the various low-ks (Low-K) such as silicon nitride, silica, carborundum; Interlayer dielectric layer 6 materials can include but not limited to the inorganic silicon matrix layer (inorganic silicon based layer) of low-k, general described dielectric coefficient is less than 3.0, for example silicon oxide carbide (SiCO), fluorinated silica glass (FSG) or silicon dioxide (SiO
2) etc.
The pseudo-grid structure that comprises boundary layer 2, high-dielectric-coefficient grid medium layer 3 and dummy poly grid 4, and side wall 5 and the interlayer dielectric layer 6 of pseudo-grid structure both sides, all adopt existing semiconductor technology to form, specifically can be referring to the pertinent literatures such as patent application of publication number CN101438389A, comprise that the physical dimensions such as each layer thickness adjust according to concrete technology requirement and product needed, also comprised at substrate 1 in the existing technique and carried out Implantation to form the step of source-drain area, repeated no more herein.
Step 2: as shown in Figure 2, remove described dummy poly grid 4 and form grooves, and in groove, (comprise bottom land and sidewall) successively plated metal work function layer 7 and separator 8.
Wherein, remove the method that dummy poly grid 4 can adopt dry etching, such as RIE (Reactive Ion, reactive ion etching) method.The deposition of metal work function layer 7 and separator 8 is to carry out at the whole semiconductor device surface of removing after dummy poly grid 4 forms groove, and therefore as shown in Figure 2, the metal work function layer 7 of deposition and separator 8 also are covered in the surface of interlayer dielectric layer 6.
For PMOS (P Metal Oxide Semiconductor, P-type mos) transistor and NMOS (N Metal Oxide Semiconductor, the N-type metal-oxide semiconductor (MOS)) transistor, metal work function layer 7 is discrepant.In the PMOS transistor, metal work function layer 7 can adopt individual layer or sandwich construction; When adopting single layer structure, the material of metal work function layer 7 can be TiN (titanium nitride) or TaN (tantalum nitride) etc., adopt ALD (Atomic Layer Deposition, ald) or the method such as PVD (Physical Vapor Deposition, physical vapour deposition (PVD)) be prepared; When adopting sandwich construction, metal work function layer 7 can adopt the alternately sandwich construction of stack of TiN layer and TaN layer, and TiN layer and TaN layer all can adopt the methods such as ALD or PVD to be prepared.In the nmos pass transistor, metal work function layer 7 also adopts individual layer or sandwich construction; When adopting single layer structure, metal work function layer 7 can adopt the materials such as TiAl (titanium-aluminium alloy), can adopt the methods such as ALD or PVD to be prepared; When adopting sandwich construction, metal work function layer 7 can adopt the alternately sandwich construction of stack of Ti layer and Al layer, perhaps adopt the alternately sandwich construction of stack of TiN layer and Al layer, wherein Ti layer, Al layer and TiN layer all can adopt the methods such as ALD or PVD to be prepared.The thickness of metal work function layer 7 can for
Step 3: as shown in Figure 6, the device surface after previous step plated metal work function layer 7 and separator 8, deposit spathic silicon layer 10, and utilize this polysilicon layer 10 that groove is filled up.
In this step 3, polysilicon layer 10 carries out at whole semiconductor device surface, and therefore as shown in Figure 6, the polysilicon layer 10 that fills up groove also is covered in the surface of whole separator 8.When the making technology of semiconductor device during less than 32nm, after previous step plated metal work function layer 7 and the separator 8, the width of groove or less than 10nm, the groove depth-to-width ratio of this moment can not satisfy the deposition of carrying out the Al metal level, but because the mechanism of Al metal and polysilicon deposition is different, polysilicon can deposit in the groove.Adopt boiler tube technique (furnace process) method to carry out the deposition of polysilicon layer 10 in the present embodiment.Being deposited in the boiler tube reaction chamber of polysilicon layer 10 carried out, and the main component of reacting gas is silane, and reaction temperature is set to 300～500 ℃, and reaction chamber pressure can be controlled in 0.3～0.6Torr.
When carrying out the deposition of polysilicon layer 10, silane gas arrives in the groove, then is decomposed to form polysilicon and hydrogen in groove, and the polysilicon that is decomposed to form just Direct precipitation has arrived among the groove.Different from polysilicon is, the Al metal is in deposition process, can't enter groove with the form of gaseous state, and further in groove, form the Al metal level, mostly the Al metal is to spread and in the groove that arrives at the device epitaxial surface, when the groove depth-to-width ratio is excessive, in the time of the Al metal can occurring and not yet fill up groove, the Al metal that groove has just been piled up by notch is shut, and then produces the space in groove.
Step 4: as shown in Figure 7, depositing Al metal level 9 on polysilicon layer 10.
In this step 4, Al metal level 9 can adopt prior art to deposit, such as methods such as ALD, CVD, PVD, EP (plating).The thickness of Al metal level 9 can for
Step 5: as shown in Figure 8, depositing Ti metal level 11 on Al metal level 9.
In this step 5, Ti metal level 11 can adopt prior art to deposit, such as methods such as ALD, CVD, PVD, EP (plating).The thickness of Ti metal level 11 can for
Step 6: as shown in Figure 9, carry out thermal annealing (thermal annealing) and process, so that Al metal level 9 and polysilicon layer 10 are replaced mutually, form the Al electrode.
In this step 6, the temperature of thermal annealing process is 300～500 ℃, and annealing time is 10～60 minutes, and annealing atmosphere is N
2In the thermal annealing process, meeting phase counterdiffusion between Al metal level 9 and the polysilicon layer 10, and then so that the position of Al metal level 9 and polysilicon layer 10 replace, shown in four-headed arrow among Fig. 9, after producing replacement, former Al metal level 9 just can diffuse in the occupied whole groove of former polysilicon layer 10, and occupied former polysilicon layer 10 just can diffuse to the position of former Al metal level 9 in the groove, as shown in figure 10, carry out in addition also can eliminating in the lump in the thermal annealing process defective in Al metal level 9 and the polysilicon layer 10, and then so that the defective in the Al electrode that forms after replacing still less.Replacement about Al metal and polysilicon can be referring to document IEEE 1996 Novel High Aspect Ratio Aluminum Plug for Logic/DRAM LSIs Using Polysilicon-Aluminum Substitute (PAS), pp.14.7.1-14.7.3 (Hiroshi Horie, Masahiko Imai, Akio Itoh and Yoshihiro Arimoto) record.
Step 7: as shown in figure 11, remove polysilicon layer 10 and the Al metal that is in outside the groove after replacing, to form metal gates.
In this step 7, adopt existing widely used CMP (cmp) method to carry out, this CMP method can be removed Ti metal level 11, polysilicon layer 10 and the Al metal level 9 of whole groove outside, and device surface is polished.
It should be noted that, step 5 in the said method is optional steps, the effect of depositing Ti metal level 11 is displacements of carrying out assisting in the thermal annealing process Al metal level 9 and polysilicon layer 10 in step 6, the towards periphery volatilization in space of metal ingredient of Al metal level 9 when stoping thermal annealing, improve the displacement efficiency of Al metal level 9 and polysilicon layer 10, so that the thermal annealing temperature suitably reduces and shortens the thermal annealing time.If do not carry out the deposition of the Ti metal level 11 of step 5, in carrying out the thermal annealing process of step 6, Al metal level 9 and polysilicon layer 10 still can be replaced, but Al metal level 9 towards periphery space volatilizees, and needs suitably to improve the thermal annealing temperature and prolong the thermal annealing time to reach the displacement purpose of Al metal level 9 and polysilicon layer 10.
Based on above-mentioned metal gates manufacture method, the present invention also provides a kind of CMOS manufacture method, as shown in figure 12, comprising:
Step 1 ': as shown in figure 13, substrate 1 is provided, be divided into PMOS district and nmos area by STI (shallow trench isolation from) 12 on the substrate 1, be formed with the pseudo-grid structure in PMOS district in the PMOS district, the pseudo-grid structure in PMOS district is included in the PMOS regional boundary surface layer 21 that forms successively on the substrate 1, PMOS district high-dielectric-coefficient grid medium floor 31 and PMOS district dummy poly grid 41, be formed with PMOS district side wall 51 along pseudo-grid structure both sides, described PMOS district, be formed with the pseudo-grid structure of nmos area on the described nmos area, the pseudo-grid structure of described nmos area is included in the nmos area boundary layer 22 that forms successively on the described substrate 1, nmos area high-dielectric-coefficient grid medium layer 32 and nmos area dummy poly grid 42, be formed with nmos area side wall 52 along the pseudo-grid structure of described nmos area both sides, on the substrate 1 in described PMOS district side wall 51 and nmos area side wall 52 outsides, also be formed with interlayer dielectric layer 6.
Wherein, substrate 1 can comprise any can be as the basic material that makes up semiconductor device thereon, such as silicon substrate; STI12 can select SiO
2Material; PMOS regional boundary surface layer 21 and nmos area boundary layer 22 can be selected SiO
2Material; The material of PMOS district high-dielectric-coefficient grid medium floor 31 and nmos area high-dielectric-coefficient grid medium floor 32 includes but not limited to the high dielectric constant materials such as hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum and lead niobate zinc; The material of PMOS district side wall 51 and nmos area side wall 52 includes but not limited to nitride or the oxide material of the various low-ks such as silicon nitride, silica, carborundum; The material of interlayer dielectric layer 6 includes but not limited to the inorganic silicon matrix layer of low-k, and general described dielectric coefficient is less than 3.0, such as silicon oxide carbide, fluorinated silica glass or silicon dioxide etc.
The device architecture of this step 1 ' adopts existing semiconductor technology to form, comprise that the physical dimensions such as each layer thickness adjust according to concrete technology requirement and product needed, also comprised at substrate 1 in the existing technique and carried out Implantation to form the step of source-drain area, repeated no more herein.
Step 2 ': as shown in figure 14, remove PMOS district dummy poly grid 41 formation PMOS district grooves, and in PMOS district groove, (comprise bottom land and sidewall) and deposit successively PMOS district metal work function floor 71 and PMOS separates absciss layer 81.
Wherein, removing PMOS district dummy poly grid 41 can adopt the method for dry etching such as RIE method to carry out.The deposition that PMOS district metal work function floor 71 and PMOS separate absciss layer 81 is to carry out on the whole cmos device surface of removing after PMOS district dummy poly grid 41 forms groove, therefore as shown in figure 14, the PMOS district metal work function floor 71 of deposition and PMOS separate absciss layer 81 and also are covered in the surface of interlayer dielectric layer 6 and the surface of nmos area dummy poly grid 42.
Step 2 ' in, PMOS district metal work function floor 71 can adopt individual layer or sandwich construction; When adopting single layer structure, the material of PMOS district metal work function floor 71 can be TiN or TaN etc., adopts the methods such as ALD or PVD to be prepared; When adopting sandwich construction, PMOS district metal work function floor 71 can adopt the alternately sandwich construction of stack of TiN floor and TaN floor, and TiN layer and TaN layer all can adopt the methods such as ALD or PVD to be prepared.The thickness of PMOS district metal work function floor 71 can for
PMOS separates absciss layer 81 can select the materials such as TaN or TiN, utilizes the methods such as ALD or PVD to be prepared.The thickness that PMOS separates absciss layer 81 is approximately
Step 3 ': as shown in figure 15, deposit spathic silicon floor 10 also utilizes this polysilicon layer 10 that PMOS district groove is filled up.
In this step 3 ', polysilicon layer 10 carries out on whole cmos device surface, and therefore as shown in figure 15, the polysilicon layer 10 that fills up groove also is covered in the surface that whole PMOS separates absciss layer 81.The deposition of polysilicon layer 10 adopts the boiler tube process herein.Being deposited in the boiler tube reaction chamber of polysilicon layer 10 carried out, and the main component of reacting gas is silane, and reaction temperature is set to 300～500 ℃, and reaction chamber pressure can be controlled in 0.3～0.6Torr.
Step 4 ': as shown in figure 16, depositing Al metal level 9 on described polysilicon layer 10.
In this step 4 ', Al metal level 9 can adopt the methods such as ALD, CVD, PVD, EP to deposit.The thickness of Al metal level 9 can for
Step 5 ': as shown in figure 17, titanium deposition Ti metal level 11 on Al metal level 9.
In this step 5 ', Ti metal level 11 can adopt the methods such as ALD, CVD, PVD, EP to deposit.The thickness of Ti metal level 11 can for
Step 6 ': as shown in figure 18, carry out thermal annealing and process, so that Al metal level 9 and polysilicon layer 10 are replaced mutually, form PMOS district Al electrode.
In this step 6 ', the temperature of thermal annealing process is 300～500 ℃, and annealing time is 10～60 minutes, and annealing atmosphere is N
2In the thermal annealing process, can produce diffusion phenomena between Al metal level 9 and the polysilicon layer 10, and then so that the position of Al metal level 9 and polysilicon layer 10 replace, shown in four-headed arrow among Figure 18, after produce replacing, former Al metal level 9 just can diffuse in the occupied whole groove of former polysilicon layer 10, forms PMOS district Al electrode in groove, and occupied former polysilicon layer 10 just can diffuse to the position of former Al metal level 9 in the groove, as shown in figure 19.
Step 7 ': as shown in figure 20, remove polysilicon layer 10 and the Al metal that is in outside the PMOS district groove after replacing, to form PMOS district metal gates.
In this step 7 ', adopt the CMP method to carry out polysilicon layer 10 and the removal that is in the Al metal outside the PMOS district groove, this CMP method can be removed Ti metal level 11, polysilicon layer 10 and the Al metal level 9 of whole groove outside simultaneously, and device surface is polished.
After the CMP method, in step before, deposit to PMOS district metal work function floor 71, PMOS on the nmos area separate absciss layer 81, Al metal level 9, polysilicon layer 10 and Ti metal level 11 also be removed, nmos area dummy poly grid 42 exposes the cmos device surface, as shown in figure 20.
Step 8 ': as shown in figure 21, remove nmos area dummy poly grid 42 and form the nmos area grooves, and in the nmos area groove, (comprise bottom land and sidewall) and deposit successively nmos area metal work function layer 72 and nmos area separator 82.
Wherein, removing nmos area dummy poly grid 42 can adopt the method for dry etching such as RIE method to carry out.The deposition of nmos area metal work function layer 72 and nmos area separator 82 is to carry out on the whole cmos device surface of removing after nmos area dummy poly grid 42 forms groove, therefore as shown in figure 21, the nmos area metal work function floor 72 of deposition and nmos area separator 82 also are covered in the surface of interlayer dielectric layer 6 and the surface of the PMOS district metal gates that formed.
Step 8 ' in, nmos area metal work function layer 72 can adopt individual layer or sandwich construction; When adopting single layer structure, the material of nmos area metal work function layer 72 can adopt the materials such as TiAl, can adopt the methods such as ALD or PVD to be prepared; When adopting sandwich construction, nmos area metal work function layer 72 can adopt the alternately sandwich construction of stack of Ti layer and Al layer, perhaps adopt the alternately sandwich construction of stack of TiN layer and Al layer, wherein Ti layer, Al layer and TiN layer all can adopt the methods such as ALD or PVD to be prepared.The thickness of nmos area metal work function layer 72 can for
Nmos area separator 82 can be selected the materials such as TaN or TiN, utilizes the methods such as ALD or PVD to be prepared.The thickness of nmos area separator 82 is approximately
Step 9 ': as shown in figure 22, deposit spathic silicon layer 10 also utilizes this polysilicon layer 10 that the nmos area groove is filled up.
In this step 9 ', polysilicon layer 10 carries out on whole cmos device surface, and therefore as shown in figure 22, the polysilicon layer 10 that fills up groove also is covered in the surface of whole nmos area separator 82.With step 3 ' identical, in this step 9 ', the deposition of polysilicon layer 10 adopts the boiler tube process.Being deposited in the boiler tube reaction chamber of polysilicon layer 10 carried out, and the main component of reacting gas is silane, and reaction temperature is set to 300～500 ℃, and reaction chamber pressure can be controlled in 0.3～0.6Torr.
Step 10 ': as shown in figure 23, depositing Al metal level 9 on described polysilicon layer 10.
With step 4 ' identical, in this step 10 ', Al metal level 9 can adopt the methods such as ALD, CVD, PVD, EP to deposit.The thickness of Al metal level 9 can for
Step 11 ': as shown in figure 24, depositing Ti metal level 11 on Al metal level 9.
With step 5 ' identical, in this step 11 ', Ti metal level 11 can adopt the methods such as ALD, CVD, PVD, EP to deposit.The thickness of Ti metal level 11 can for
Step 12 ': as shown in figure 25, carry out thermal annealing and process, so that Al metal level 9 and polysilicon layer 10 are replaced mutually, form nmos area Al electrode.
With step 6 ' identical, in this step 12 ', the temperature of thermal annealing process is 300～500 ℃, and annealing time is 10～60 minutes, and annealing atmosphere is N
2In the thermal annealing process, can produce diffusion phenomena between Al metal level 9 and the polysilicon layer 10, and then so that the position of Al metal level 9 and polysilicon layer 10 replace, shown in four-headed arrow among Figure 25, after produce replacing, Al metal level 9 just can diffuse in the occupied whole groove of polysilicon layer 10, forms nmos area Al electrode in groove, and occupied polysilicon layer 10 can diffuse to the position of Al metal level 9 in the groove, as shown in figure 26.
Step 13 ': as shown in figure 27, remove polysilicon layer 10 and the Al metal that is in outside the nmos area groove after replacing, to form the nmos area metal gates.
With step 7 ' identical, in this step 13 ', adopt the CMP method to carry out polysilicon layer 10 and the removal that is in the Al metal outside the nmos area groove, this CMP method can be removed Ti metal level 11, polysilicon layer 10 and the Al metal level 9 of whole groove outside simultaneously, and device surface is polished.
After the CMP method, in step before, deposit to nmos area metal work function floor 72 in the PMOS district, nmos area separator 82, Al metal level 9, polysilicon layer 10 and Ti metal level 11 also be removed, PMOS district metal gates also exposes the cmos device surface simultaneously, as shown in figure 27.
It should be noted that, step 5 in the above-mentioned CMOS manufacture method ' and step 11 ' be optional step, carry out the displacement of auxiliary Al metal level 9 and polysilicon layer 10 in the process of thermal annealing during the effect of depositing Ti metal level 11 is in step 6 ' and step 12 ', the towards periphery volatilization in space of metal ingredient of Al metal level 9 when stoping thermal annealing, improve the displacement efficiency of Al metal level 9 and polysilicon layer 10, so that the thermal annealing temperature suitably reduces and shortens the thermal annealing time.The deposition of the Ti metal level 11 of ' and step 11 ' if carry out step 5, in the carry out step 6 thermal annealing process of ' and step 12 ', Al metal level 9 and polysilicon layer 10 still can be replaced, but Al metal level 9 towards periphery space volatilizees, and needs suitably to improve the thermal annealing temperature and prolong the thermal annealing time to reach the displacement purpose of Al metal level 9 and polysilicon layer 10.
It is emphasized that in the above that the step that does not add careful explanation all can use conventional methods acquisition, and concrete technological parameter is determined according to product requirement and process conditions.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (14)
1. metal gates manufacture method comprises:
The substrate that is formed with pseudo-grid structure is provided, described pseudo-grid structure is included in boundary layer, high-dielectric-coefficient grid medium layer and the dummy poly grid that forms successively on the described substrate, be formed with side wall along described pseudo-grid structure both sides, on the substrate in the described side wall outside, also be formed with interlayer dielectric layer;
Remove described dummy poly grid and form groove, and in groove successively plated metal work function layer and separator;
The deposit spathic silicon layer also utilizes described polysilicon layer that groove is filled up;
Depositing Al metal level on described polysilicon layer;
Carry out thermal annealing and process, so that described Al metal level and polysilicon layer are replaced mutually, form the Al electrode;
Remove polysilicon layer and the Al metal that is in outside the groove after replacing, to form metal gates.
2. metal gates manufacture method according to claim 1 is characterized in that, after the depositing Al metal level, carries out also comprising before the thermal annealing processing on described polysilicon layer:
Titanium deposition Ti metal level on described Al metal level.
3. metal gates manufacture method according to claim 1 is characterized in that, described thermal annealing temperature is 300～500 ℃, and annealing time is 10～60 minutes, and annealing atmosphere is N
2
4. according to claim 1 to 3 each described metal gates manufacture methods, it is characterized in that described polysilicon layer adopts the boiler tube process to make, the temperature when adopting the boiler tube process is 300～500 ℃.
5. according to claim 1 to 3 each described metal gates manufacture methods, it is characterized in that described Al metal level adopts ald ALD, CVD, physical vapour deposition (PVD) PVD or electroplates EP method deposition.
6. according to claim 1 to 3 each described metal gates manufacture methods, it is characterized in that, adopt polysilicon layer and the Al metal that is in outside the groove after cmp CMP method is removed replacement.
7. CMOS manufacture method comprises:
Substrate is provided, be divided into PMOS district and nmos area by the shallow trench isolation STI on the described substrate, be formed with the pseudo-grid structure in PMOS district in the described PMOS district, the pseudo-grid structure in described PMOS district is included in the PMOS regional boundary surface layer that forms successively on the described substrate, PMOS district high-dielectric-coefficient grid medium floor and PMOS district dummy poly grid, be formed with PMOS district side wall along pseudo-grid structure both sides, described PMOS district, be formed with the pseudo-grid structure of nmos area on the described nmos area, the pseudo-grid structure of described nmos area is included in the nmos area boundary layer that forms successively on the described substrate, nmos area high-dielectric-coefficient grid medium layer and nmos area dummy poly grid, be formed with the nmos area side wall along the pseudo-grid structure of described nmos area both sides, on the substrate in described PMOS district's side wall and the nmos area side wall outside, also be formed with interlayer dielectric layer;
Remove dummy poly grid formation PMOS district, PMOS district groove, and in PMOS district groove, deposit successively PMOS district metal work function floor and PMOS separates absciss layer;
The deposit spathic silicon floor also utilizes this polysilicon layer that PMOS district groove is filled up;
Depositing Al metal level on described polysilicon layer;
Carry out thermal annealing and process, so that described Al metal level and polysilicon layer are replaced mutually, form PMOS district Al electrode;
Remove polysilicon layer and the Al metal that is in outside the PMOS district groove after replacing, to form PMOS district metal gates;
Remove nmos area dummy poly grid and form the nmos area groove, and in the nmos area groove, deposit successively nmos area metal work function layer and nmos area separator;
The deposit spathic silicon layer also utilizes this polysilicon layer that the nmos area groove is filled up;
Depositing Al metal level on described polysilicon layer;
Carry out thermal annealing and process, so that described Al metal level and polysilicon layer are replaced mutually, form nmos area Al electrode;
Remove polysilicon layer and the Al metal that is in outside the nmos area groove after replacing, to form the nmos area metal gates.
8. CMOS manufacture method according to claim 7 is characterized in that, after the depositing Al metal level, carries out thermal annealing and processes on described polysilicon layer, so that described Al metal level and polysilicon layer are replaced mutually, forms PMOS district Al electrode and also comprises before:
Titanium deposition Ti metal level on described Al metal level.
9. CMOS manufacture method according to claim 7 is characterized in that, after the depositing Al metal level, carries out thermal annealing and processes on described polysilicon layer, so that described Al metal level and polysilicon layer are replaced mutually, forms nmos area Al electrode and also comprises before:
Titanium deposition Ti metal level on described Al metal level.
10. CMOS manufacture method according to claim 7 is characterized in that, described polysilicon layer adopts the boiler tube process to make, and the temperature when adopting the boiler tube process is 300～500 ℃.
11. CMOS manufacture method according to claim 7 is characterized in that, described thermal annealing temperature is 300～500 ℃, and annealing time is 10～60 minutes, and annealing atmosphere is N
2
12. according to claim 7 to 11 each described CMOS manufacture methods, it is characterized in that: described PMOS district metal work function floor is individual layer or sandwich construction according to claim; When described PMOS district metal work function floor was single layer structure, material was titanium nitride TiN or tantalum nitride TaN, adopted the preparation of ald ALD method or physical vapour deposition (PVD) PVD method; When described PMOS district metal work function floor is sandwich construction, adopt the alternately described sandwich construction of stack formation of TiN layer and TaN layer, wherein said TiN layer adopts ALD method or the preparation of PVD method, and described TaN layer adopts ALD method or the preparation of PVD method; Described PMOS district metal work function layer thickness is
13. according to claim 7 to 11 each described CMOS manufacture methods, it is characterized in that: described nmos area metal work function layer is individual layer or sandwich construction according to claim; When described nmos area metal work function layer was single layer structure, material was titanium-aluminium alloy TiAl, adopted the preparation of ALD method or PVD method; When described nmos area metal work function layer is sandwich construction, adopt the alternately described sandwich construction of stack formation of Ti layer and Al layer, perhaps adopt the alternately described sandwich construction of stack formation of TiN layer and Al layer, wherein said Ti layer adopts ALD method or the preparation of PVD method, described Al layer adopts ALD method or the preparation of PVD method, described TiN layer adopts ALD method or the preparation of PVD method, and described nmos area metal work function layer thickness is
14. according to claim according to claim 7 to 11 each described CMOS manufacture methods, it is characterized in that: described PMOS separates absciss layer and the nmos area insolated layer materials is TaN or TiN, adopt the preparation of ALD method or PVD method, PMOS separates absciss layer and the nmos area separation layer thickness is
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