CN107180794B - A kind of method and cmos device adjusting high-K metal gate cmos device threshold value - Google Patents

A kind of method and cmos device adjusting high-K metal gate cmos device threshold value Download PDF

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CN107180794B
CN107180794B CN201710449946.XA CN201710449946A CN107180794B CN 107180794 B CN107180794 B CN 107180794B CN 201710449946 A CN201710449946 A CN 201710449946A CN 107180794 B CN107180794 B CN 107180794B
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fin
work
function layer
area
barrier layer
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CN107180794A (en
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殷华湘
张青竹
赵超
叶甜春
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Semiconductor Manufacturing International Shanghai Corp
Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a kind of methods and cmos device for adjusting high-K metal gate cmos device threshold value, this method comprises: providing substrate, NMOS area includes the first fin and the second fin, and PMOS area includes third fin and the 4th fin；It is sequentially depositing the first barrier layer and the first work-function layer；Remove the first work-function layer in NMOS area；Make the first barrier layer with different thickness on the first fin and the second fin；Deposit the second work-function layer；Make the second work-function layer with different thickness on third fin and the 4th fin.Method provided by the invention and device adjust small, the poor controllability, and close on the technical issues of interface easily causes the process-induced damage to channel of distinguishing range of thickness existing for technique to solve high-K metal gate cmos device threshold value in the prior art.The controlled range for improving threshold value regulation thickness degree is realized, the technical effect to the process-induced damage of channel is reduced.

Description

A kind of method and cmos device adjusting high-K metal gate cmos device threshold value
Technical field
The present invention relates to field of semiconductor integration technology more particularly to a kind of adjust high-K metal gate cmos device threshold value Method and cmos device.
Background technique
The existing method for adjusting high-K metal gate cmos device threshold value is: the metal gate of NMOS and PMOS first deposits barrier layer With deposition PMOS work-function layer (PMOS WFL), then remove NMOS area PMOS WFL and adjust NMOS area blocking thickness Degree to adjust NMOS threshold value, then change PMOS area PMOS WFL thickness to adjust PMOS threshold value；Redeposited NMOS work content Several layers (NMOS WFL).
Due in existing method the metal gate work function threshold value of NMOS and PMOS thickness adjusting be all based on barrier layer and The corrosion of the TiNx sill of PMOS WFL, thickness differentiation range is small, poor controllability, and closes on interface and easily cause to channel Process-induced damage.
Summary of the invention
The embodiment of the present application is by providing a kind of method and cmos device for adjusting high-K metal gate cmos device threshold value, solution Thickness differentiation range existing for high-K metal gate cmos device threshold value adjusting technique in the prior art of having determined is small, poor controllability, and Close on the technical issues of interface easily causes the process-induced damage to channel.
On the one hand, in order to solve the above technical problems, the embodiment provides following technical solutions:
A method of adjusting high-K metal gate cmos device threshold value, comprising:
Substrate is provided, the substrate includes NMOS area and PMOS area, and the NMOS area includes the first fin and the Two fins, the PMOS area include third fin and the 4th fin；
It is sequentially depositing the first barrier layer and the first work-function layer；
Remove the first work-function layer in the NMOS area；
It is handled, is made with different thickness on first fin and second fin in the NMOS area First barrier layer；
Deposit the second work-function layer；
It is handled, is made with different thickness on the third fin and the 4th fin in the PMOS area Second work-function layer.
Optionally, described to be handled in the NMOS area, make to have on first fin and second fin There is first barrier layer of different-thickness, comprising: first barrier layer on first fin is thinned or is thinned described First barrier layer on second fin.
Optionally, described to be handled in the PMOS area, make to have on the third fin and the 4th fin There is second work-function layer of different-thickness, comprising: second work-function layer on the third fin is thinned or is thinned Second work-function layer on 4th fin.
Optionally, described that processing and the side handled in the PMOS area are carried out in the NMOS area Method, includes any of the following or a variety of combinations: dry etching, wet etching, ashing or removing.
Optionally, first barrier layer includes at least one of following material or a variety of combinations: TiN, TaN, TiNx、TaNx、TiNSi。
Optionally, second work-function layer includes at least one of following material or a variety of combinations: Al, TiAl, TiAlx、TiAlCx、TiCx、TaCx。
Optionally, first work-function layer includes at least one of following material or a variety of combinations: TiN, TaN, TiNx、TaNx、TiNSi。
On the other hand, a kind of cmos device is provided, comprising:
Substrate, the substrate include NMOS area and PMOS area, and the NMOS area includes the first fin and the second fin Piece, the PMOS area include third fin and the 4th fin；
First barrier layer is located in the NMOS area and PMOS area, on first fin and second fin First barrier layer with different thickness；
First work-function layer, first work-function layer are located on first barrier layer of the PMOS area；
Second work-function layer, second work-function layer are located on first barrier layer of the NMOS area and described In first work-function layer of PMOS area, wherein with different thickness on the third fin and the 4th fin Second work-function layer.
Optionally, first barrier layer includes at least one of following material or a variety of combinations: TiN, TaN, TiNx、TaNx、TiNSi。
Optionally, second work-function layer includes at least one of following material or a variety of combinations: Al, TiAl, TiAlx,TiAlCx,TiCx,TaCx；First work-function layer includes at least one of following material or a variety of combinations: TiN、TaN、TiNx、TaNx、TiNSi。
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
The method and cmos device provided by the embodiments of the present application for adjusting high-K metal gate cmos device threshold value, passes through adjusting The thickness on NMOS area metal gate barrier layer adjusts NMOS threshold value, by the NMOS WFL work-function layer thickness for adjusting PMOS area PMOS threshold value is adjusted, integrated technique is simple, and not only adjustable TiNx sill thickness, can also adjust WFL layers of NMOS Thickness, thickness controlled range is big, in addition, the control variation leafing interface of PMOS can effectively reduce the technique damage to channel farther out Wound.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only the embodiment of the present invention, for ability For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to the attached drawing of offer other Attached drawing.
Fig. 1 is the flow chart that the method for high-K metal gate cmos device threshold value is adjusted in the embodiment of the present application；
Fig. 2 is the schematic diagram of the section structure deposited after the first barrier layer and the first work-function layer；
Fig. 3 is the schematic diagram of the section structure after the first work-function layer for removing NMOS area；
Fig. 4 is the cross-section structure signal made on the first fin and the second fin behind the first barrier layer with different thickness Figure；
Fig. 5 is the schematic diagram of the section structure deposited after the second work-function layer；
Fig. 6 is the cross-section structure signal made on third fin and the 4th fin after the second work-function layer with different thickness Figure；
Fig. 7 is the main-process stream schematic diagram of high-K metal gate cmos device preparation in the present embodiment.
Specific embodiment
The embodiment of the present application is by providing a kind of method and cmos device for adjusting high-K metal gate cmos device threshold value, solution Thickness differentiation range existing for high-K metal gate cmos device threshold value adjusting technique in the prior art of having determined is small, poor controllability, and Close on the technical issues of interface easily causes the process-induced damage to channel.The controlled range for improving threshold value regulation thickness degree is realized, Reduce the technical effect to the process-induced damage of channel.
In order to solve the above technical problems, the general thought that the embodiment of the present application provides technical solution is as follows:
A method of adjusting high-K metal gate cmos device threshold value, comprising:
Substrate is provided, the substrate includes NMOS area and PMOS area, and the NMOS area includes the first fin and the Two fins, the PMOS area include third fin and the 4th fin；
It is sequentially depositing the first barrier layer and the first work-function layer；
Remove the first work-function layer in the NMOS area；
It is handled, is made with different thickness on first fin and second fin in the NMOS area First barrier layer；
Deposit the second work-function layer；
It is handled, is made with different thickness on the third fin and the 4th fin in the PMOS area Second work-function layer.
The embodiment of the present application providing method, the thickness by adjusting NMOS area metal gate barrier layer adjust NMOS threshold value, NMOS WFL work-function layer thickness by adjusting PMOS area adjusts PMOS threshold value, and integrated technique is simple, and not only can be with TiNx sill thickness is adjusted, NMOS WFL thickness degree can also be adjusted, thickness controlled range is big, in addition, the control of PMOS becomes The process-induced damage to channel can be effectively reduced farther out by changing leafing interface.
In order to better understand the above technical scheme, being carried out below in conjunction with specific embodiment to above-mentioned technical proposal It is described in detail, it should be understood that the specific features in the embodiment of the present invention and embodiment are to the detailed of technical scheme Illustrate, rather than the restriction to technical scheme, in the absence of conflict, in the embodiment of the present application and embodiment Technical characteristic can be combined with each other.
Embodiment one
In the present embodiment, a kind of method for adjusting high-K metal gate cmos device threshold value is provided, as shown in Figure 1, comprising:
S101 provides substrate, and the substrate includes NMOS area and PMOS area, and the NMOS area includes the first fin With the second fin, the PMOS area includes third fin and the 4th fin；
S102 is sequentially depositing the first barrier layer and the first work-function layer；
S103 removes the first work-function layer in the NMOS area；
S104 is handled in the NMOS area, makes have difference on first fin and second fin First barrier layer of thickness；
S105 deposits the second work-function layer；
S106 is handled in the PMOS area, makes have difference on the third fin and the 4th fin Second work-function layer of thickness.
In the following, the detailed step of the application providing method is discussed in detail in conjunction with Fig. 1-7, wherein Fig. 2-Fig. 7 is followed successively by tune Process sequence diagram during section high-K metal gate cmos device threshold value by elder generation after:
Step S101 provides substrate 100.
The substrate 100 includes NMOS area and PMOS area, and the NMOS area includes the first fin 10 and the second fin Piece 30, the PMOS area include third fin 20 and the 4th fin 40.
In the embodiment of the present application, separation layer/high-k dielectric layer can be equipped on the fin of the substrate.
Step S102 is sequentially depositing the first barrier layer 200 and the first work-function layer 300.
As shown in Fig. 2, the first barrier layer 200 of deposition.First barrier layer 200 includes at least one of following material Or a variety of combination: TiN, TaN, TiNx, TaNx, TiNSi.
Deposit the first work-function layer 300.First work-function layer 300 is PMOS WFL, and it includes in following material At least one or more of combination: TiN, TaN, TiNx, TaNx, TiNSi.
S103 removes the first work-function layer in the NMOS area.
As shown in figure 3, removing the first work-function layer 300 in the NMOS area, retain in the NMOS area One barrier layer 200, the method for removal includes but is not limited to: dry method, wet etching or ashing, removing and chemical reaction etc..
S104 makes first fin 10 and second fin as shown in figure 4, being handled in the NMOS area First barrier layer 200 with different thickness on piece 30.
In the embodiment of the present application, described to be handled in the NMOS area, make first fin 10 and described First barrier layer 200 with different thickness on second fin 30 carries out at part specially in the NMOS area Reason, comprising:
First barrier layer 200 being thinned on first fin 10 or be thinned on second fin 30 described One barrier layer 200.
Wherein, the method handled in the NMOS area includes but is not limited to: dry method, wet etching or ashing, Removing and chemical reaction etc..
S105 deposits the second work-function layer 400.
As shown in figure 5, deposition the second work-function layer 400, second work-function layer 400 be NMOS WFL, it includes with At least one of lower material or a variety of combinations: Al, TiAl, TiAlx, TiAlCx, TiCx, TaCx.
S106 makes the third fin 20 and the 4th fin as shown in fig. 6, being handled in the PMOS area Second work-function layer 400 with different thickness on piece 40.
In the embodiment of the present application, described to be handled in the PMOS area, make the third fin 20 and described Second work-function layer 400 with different thickness on 4th fin 40 carries out part specially in the PMOS area Processing, comprising:
Second work-function layer 400 that is thinned on the third fin 20 is thinned described on the 4th fin 40 Second work-function layer 400.
Wherein, the method handled in the PMOS area includes but is not limited to: dry method, wet etching or ashing, Removing and chemical reaction etc..
Specifically, since TiAl or the TiAlCx covering of second work-function layer 400 can move TiNx substrate The work function of material, it is mobile into band that device threshold absolute value is caused to increase.Therefore remaining second work-function layer can be passed through 400 thickness control threshold value.Utilize TiNx sill and NMOS WFL (for example, the TiAlCx WFL) thickness on the barrier layer of NMOS NMOS and PMOS work function is controlled respectively, it is each to form 2 different threshold values.Wherein, device architecture as shown in FIG. 6, VTN-1 < VTN-2, | VTP-1 | < | VTP-2 |, wherein VTN-1 is the threshold value of the corresponding NMOS of the first fin 10, and VTN-2 is the second fin 30 The threshold value of corresponding NMOS, the threshold value VTP-2 that VTP-1 is the corresponding PMOS of third fin 20 are the threshold of the corresponding PMOS of the 4th fin 40 Value.
After having understood the primary object of the application, below with reference to Fig. 7, the embodiment of the present invention high-K metal gate is introduced The complete process flow of cmos device, specially fin formula field effect transistor (Fin Field-Effect Transistor, FinFET process flow):
Step S701, forms fin FET on a silicon substrate；
Step S702 forms device isolation region Fin STI；
Step S703-S709 forms grid curb wall and source-drain area in each false grid stacked structure two sides.Specifically: step Rapid S703, doping form the well region and channel region of NMOS and PMOS；Step S704 forms false grid；Step S705 forms spacer (Spacer)；The source and drain doping of step S706, NMOS and PMOS；The source and drain of step S707, NMOS and PMOS distinguish selective epitaxy Si and SiGe；The source and drain of step S708, NMOS and PMOS are adulterated respectively；Step S709, doping annealing；
Step S710 forms the first interlayer electrolyte (ILD 0)；Step S711, the assembly of the first interlayer electrolyte stack (POP)；
Step S712 removes multiple false grid stacked structures, left in interlayer dielectric layer multiple NMOS gate grooves and Multiple PMOS gate trench；
Step S713, layer deposited isolating/high-k dielectric layer；
So far step S101 is completed, that is, completes to provide substrate, the substrate includes NMOS area and PMOS area, described NMOS area includes the first fin and the second fin, and the PMOS area includes third fin and the 4th fin；
Next, executing step S714, i.e. step S102 is sequentially depositing the first barrier layer (barrier-1) and the first function Function layer (PMOS WFL)；
Step S715 is executed, i.e. step S103 removes the first work-function layer in the NMOS area；
Step S716 is executed, i.e. step S104 handled in the NMOS area, makes first fin and described First barrier layer (barrier- I) with different thickness on second fin；
Step S717, i.e. step S105 are executed, is deposited the second work-function layer (NMOS WFL)；
Step S718 is executed, i.e. step S106 handled in the PMOS area, makes the third fin and described Second work-function layer with different thickness on 4th fin.
Step S719-S720 sequentially forms the second blocking in multiple NMOS gate grooves and multiple PMOS gate trench Layer and filled layer.Specifically include: step S719 forms the second barrier layer (barrier- II) and tungsten W conductive fill；Step S720, high-K metal gate laminated chemical mechanically polish (CMP)；Wherein, second barrier layer includes at least one in following material Kind or a variety of combinations: TiN, TaN, TiNx, TaNx, TiNSi.The preferred resistivity of filled layer material is low, filling rate is high The metal simple-substances such as metal, such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or The nitride of the alloy of these metals and these metals.Wherein, cmp planarization to flush at the top of metal gate structure；
Step S721-S725 completes device interconnection.Specifically include: step S721, deposition form the second interlayer electrolyte (ILD 1)；Step S722 forms metal layer (CT) and silicide layer (Silicide)；Step S723 forms tungsten plug (W ), plug it and chemically-mechanicapolish polishes；Step S724, multilayer interconnection；Step S725 forms passivation layer and pin (Pad).
Specifically, the present embodiment adjusts NMOS threshold value by adjusting the thickness on NMOS area metal gate barrier layer, passes through The NMOS WFL work-function layer thickness for adjusting PMOS area adjusts PMOS threshold value, and integrated technique is simple, and not only adjustable TiNx sill thickness can also adjust NMOS WFL thickness degree, and thickness controlled range is big, in addition, the control change layer of PMOS The process-induced damage to channel can be effectively reduced farther out from interface.Conceived based on same one side, present invention also provides using implementation The device of the method preparation of example one, detailed in Example two.
Embodiment two
In the present embodiment, a kind of cmos device is provided, as shown in Figure 6, comprising:
Substrate 100, the substrate 100 include NMOS area and PMOS area, and the NMOS area includes the first fin 10 With the second fin 30, the PMOS area includes third fin 20 and the 4th fin 40；
First barrier layer 200 is located in the NMOS area and PMOS area, first fin 10 and second fin First barrier layer 200 with different thickness on piece 30；
First work-function layer 300, first work-function layer 300 are located at first barrier layer of the PMOS area On 200；
Second work-function layer 400, second work-function layer 400 are located at first barrier layer of the NMOS area On 200 and in first work-function layer 300 of the PMOS area, wherein the third fin 20 and the 4th fin Second work-function layer 400 with different thickness on 40.
In the embodiment of the present application, first barrier layer 200 includes at least one of following material or a variety of groups It closes: TiN, TaN, TiNx, TaNx, TiNSi.First work-function layer 300 includes at least one of following material or a variety of Combination: TiN, TaN, TiNx, TaNx, TiNSi.Second work-function layer 400 include at least one of following material or A variety of combination: Al, TiAl, TiAlx, TiAlCx, TiCx, TaCx.
The laminated construction of cmos device provided by the present application is simple, can effectively improve small sized metallic grid threshold value control effect Fruit.
By the device that the embodiment of the present invention two is introduced, for the prepared device of the method for the implementation embodiment of the present invention one Part, so based on the method that the embodiment of the present invention one is introduced, the affiliated personnel in this field can understand the specific structure of the device And deformation, so details are not described herein.
Technical solution in above-mentioned the embodiment of the present application, at least have the following technical effects or advantages:
The method and cmos device provided by the embodiments of the present application for adjusting high-K metal gate cmos device threshold value, passes through adjusting The thickness on NMOS area metal gate barrier layer adjusts NMOS threshold value, by the NMOS WFL work-function layer thickness for adjusting PMOS area PMOS threshold value is adjusted, integrated technique is simple, and not only adjustable TiNx sill thickness, can also adjust WFL layers of NMOS Thickness, thickness controlled range is big, in addition, the control variation leafing interface of PMOS can effectively reduce the technique damage to channel farther out Wound.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to include these modifications and variations.

Claims (10)

1. a kind of method for adjusting high-K metal gate cmos device threshold value characterized by comprising
Substrate is provided, the substrate includes NMOS area and PMOS area, and the NMOS area includes the first fin and the second fin Piece, the PMOS area include third fin and the 4th fin；
It is sequentially depositing the first barrier layer and the first work-function layer；
Remove the first work-function layer in the NMOS area；
It is handled, is made with different thickness described on first fin and second fin in the NMOS area First barrier layer；
Deposit the second work-function layer；
It is handled, is made with different thickness described on the third fin and the 4th fin in the PMOS area Second work-function layer.
2. the method as described in claim 1, which is characterized in that it is described to be handled in the NMOS area, make described First barrier layer with different thickness on one fin and second fin, comprising:
First barrier layer being thinned on first fin or first barrier layer being thinned on second fin.
3. the method as described in claim 1, which is characterized in that it is described to be handled in the PMOS area, make described Second work-function layer with different thickness on three fins and the 4th fin, comprising:
Second work-function layer being thinned on the third fin or second work function being thinned on the 4th fin Layer.
4. method a method according to any one of claims 1-3, which is characterized in that described to carry out processing and institute in the NMOS area State the method handled in the PMOS area, include any of the following or a variety of combinations: dry etching, wet process are rotten Erosion, ashing or removing.
5. the method as described in claim 1, which is characterized in that first barrier layer includes at least one of following material Or a variety of combination: TiN, TaN, TiNx, TaNx, TiNSi.
6. the method as described in claim 1, which is characterized in that second work-function layer includes at least one in following material Kind or a variety of combinations: Al, TiAl, TiAlx, TiAlCx, TiCx, TaCx.
7. the method as described in claim 1, which is characterized in that first work-function layer includes at least one in following material Kind or a variety of combinations: TiN, TaN, TiNx, TaNx, TiNSi.
8. a kind of cmos device characterized by comprising
Substrate, the substrate include NMOS area and PMOS area, and the NMOS area includes the first fin and the second fin, institute Stating PMOS area includes third fin and the 4th fin；
First barrier layer is located in the NMOS area and PMOS area, has on first fin and second fin First barrier layer of different-thickness；
First work-function layer, first work-function layer are located on first barrier layer of the PMOS area；
Second work-function layer, second work-function layer is located on first barrier layer of the NMOS area and the PMOS In first work-function layer in region, wherein with different thickness described on the third fin and the 4th fin Second work-function layer.
9. cmos device as claimed in claim 8, which is characterized in that first barrier layer include following material at least One or more combination: TiN, TaN, TiNx, TaNx, TiNSi.
10. cmos device as claimed in claim 8, which is characterized in that second work-function layer includes in following material At least one or more of combination: Al, TiAl, TiAlx, TiAlCx, TiCx, TaCx；First work-function layer includes following At least one of material or a variety of combinations: TiN, TaN, TiNx, TaNx, TiNSi.
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