CN111554679B - SOI FinFET device and manufacturing method thereof - Google Patents

SOI FinFET device and manufacturing method thereof Download PDF

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CN111554679B
CN111554679B CN202010276290.8A CN202010276290A CN111554679B CN 111554679 B CN111554679 B CN 111554679B CN 202010276290 A CN202010276290 A CN 202010276290A CN 111554679 B CN111554679 B CN 111554679B
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layer
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tin
doping
threshold voltage
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CN111554679A (en
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王大成
蔡小五
刘海南
罗家俊
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Institute of Microelectronics of CAS
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

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Abstract

The invention discloses an SOI FinFET device and a manufacturing method thereof, wherein the SOI FinFET device comprises: a substrate having source and drain regions doped to form a group thereon; any one of the first region, the second region, the third region and the fourth region is arranged above the space between each group of the source region and the drain region; a high-K dielectric layer, a first doping layer, a second doping layer, a TiN layer and a filling layer are sequentially arranged above the substrate of the first region; a high-K dielectric layer, a first doping layer, a second doping layer, a TiN layer and a filling layer are sequentially arranged above the substrate of the second region; a high-K dielectric layer, a second doping layer, a TiN layer and the filling layer are sequentially arranged above the substrate in the third area; and a high-K dielectric layer, a second doping layer and a filling layer are sequentially arranged above the substrate in the fourth region. The SOI FinFET device does not have a thick work function layer, and the problem of metal filling of the gate electrode of a P-type device is well solved.

Description

SOI FinFET device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an SOI FinFET device and a manufacturing method thereof.
Background
The threshold voltage determines the performance of the MOS (Metal-Oxide-Semiconductor) device, such as the operating current, the switching speed, and the static power consumption, and is a key parameter of the MOS device, and how to accurately control the threshold voltage of the device is a key technology for manufacturing the MOS device.
The gate of a Fin-type Field Effect Transistor (Fin FET) device generally adopts a high-K (HK) metal gate process, the effective work function of the gate determines the threshold voltage of the high-K metal device, and the current adjustment mode of the threshold voltage of the high-K metal gate SOI (Silicon-On-Insulator) FinFET device is mainly to control the thickness of the work function metal of the gate. Experiments show that the overall effective work function of the grid changes along with the thickness change of the work function metal layer in a certain thickness range, wherein a P-type work function metal TiN (titanium nitride) is typical, the thickness of the TiN is basically in direct proportion to the overall work function of the grid, and the larger the thickness is, the larger the effective work function of the grid is. The change of the work function of the gate can be completely derived from the change of the thickness of TiN, so that the method for changing the thickness of the TiN can adjust the effective work function of the gate and achieve the aim of controlling the threshold voltage. In addition to the adjustment of the thickness of the work function Metal, the high-K Metal gate device also adjusts the threshold voltage by implanting impurities through the first Metal gate layer on the high-K dielectric layer, dopants capable of increasing the effective work function are implanted into the first Metal gate layer in a PMOS (P-type Metal-Oxide-Semiconductor) region, and dopants capable of reducing the effective work function are implanted into the first Metal gate layer in an NMOS (N-type Metal-Oxide-Semiconductor) region, so that the threshold voltage is adjusted.
In the above existing scheme, the threshold voltage is adjusted by the work function metal thickness, and the modulation amplitude of the voltage is limited. Data show that as the thickness of work function metal increases, the change rate of the effective work function of the gate gradually decreases until the effective work function does not change after a certain critical thickness, and the threshold voltage may not meet the requirement when an ultra-low threshold voltage device is manufactured; secondly, the filling of the subsequent metal of the gate may be affected by the over-thickness of the gate work function metal, as shown in fig. 1, the thicker the work function metal layer 102 is, the smaller the space left for the gate contact metal 101 is, when manufacturing a PMOS, especially an ultra low Vt (ultra low Vt) PMOS, the thicker the gate work function metal is required, which is easy to cause the filling problem and may affect the gate resistivity. Therefore, the prior art has the following disadvantages: there are limitations in fabricating ultra-low threshold voltage devices, while thicker gate metal can cause fill problems and affect the resistivity of the gate.
Disclosure of Invention
In view of the above problems, the present invention provides an SOI FinFET device and method of fabricating the same, wherein the gate structure of the device does not require a thick gate work function metal and the gate resistivity is stable; the manufacturing method can effectively avoid the filling problem of grid metal, and can simultaneously manufacture the P-type and N-type low-threshold voltage devices, and the P-type and N-type standard-threshold voltage devices are arranged on the same chip, thereby solving the limitation problem.
In a first aspect, the present application provides the following technical solutions through an embodiment of the present application:
an SOI FinFET device comprising:
a substrate having doped source and drain regions forming a group thereon;
any one of a first region, a second region, a third region and a fourth region is arranged above the space between each group of the source region and the drain region; the first region is used for forming a grid electrode of a P-type low threshold voltage device, the second region is used for forming a grid electrode of a P-type standard threshold voltage device, the third region is used for forming a grid electrode of an N-type low threshold voltage device, and the fourth region is used for forming a grid electrode of an N-type standard threshold voltage device;
the first region is sequentially provided with a high-K dielectric layer, a first doping layer, a second doping layer, a TiN layer and a filling layer from bottom to top; the first doping layer is a TiN layer containing a dopant for increasing the effective work function, and the second doping layer is a TiN layer containing a dopant for reducing the effective work function;
the second region is sequentially provided with the high-K dielectric layer, the first doping layer, the second doping layer, the TiN layer and the filling layer from bottom to top;
the third region is sequentially provided with the high-K dielectric layer, the second doping layer, the TiN layer and the filling layer from bottom to top;
the fourth region is sequentially provided with the high-K dielectric layer, the second doping layer and the filling layer from bottom to top.
Preferably, an etching barrier layer is disposed on an adjacent layer above the second doping layer in any one or more of the first region, the second region, the third region and the fourth region.
Preferably, a thickness of the TiN layer in the first region is greater than a thickness of the TiN layer in the second region.
Preferably, the filling layer sequentially comprises a TiAl layer, a TiN layer and metal tungsten from bottom to top.
Preferably, the first doped layer is BF 2 And the second doping layer is a TiN layer of P ions.
In a second aspect, based on the same inventive concept, the present application provides the following technical solutions through an embodiment of the present application:
a method of fabricating an SOI FinFET device, comprising:
depositing a first doping layer on a first area and a second area on a high-K dielectric layer on a substrate; wherein the substrate has a set of source and drain regions, the first and second regions being located above and between the set of source and drain regions, respectively, the first region being for forming a gate of a P-type low threshold voltage device and the second region being for forming a gate of a P-type standard threshold voltage device, wherein the first doped layer is a TiN layer containing a dopant that increases the effective work function;
continuously depositing a second doping layer on the first region, the second region, the third region and the fourth region on the high-K dielectric layer; the second region and the third region are respectively positioned above the grouped source region and drain region, the third region is used for forming a grid electrode of an N-type low threshold voltage device, the fourth region is used for forming a grid electrode of an N-type standard threshold voltage device, and the second doping layer is a TiN layer containing a dopant for reducing an effective work function;
continuing to deposit TiN layers on the first region, the second region and the third region on the high-K dielectric layer;
and continuously depositing filling layers in the first area, the second area, the third area and the fourth area on the high-K dielectric layer.
Preferably, the depositing a first doped layer on the first region and the second region on the high-K dielectric layer on the substrate includes:
depositing a first doping layer on the high-K dielectric layer on the substrate;
coating a BARC layer on the first doping layer, and stripping the BARC layer of the third area and the fourth area;
and removing the first doping layer of the third region and the fourth region by adopting an etching method.
Preferably, after depositing the second doping layer on the high-K dielectric layer in the first, second, third and fourth regions, and before depositing the TiN layer on the high-K dielectric layer in the first, second and third regions, further comprising:
and depositing an etching barrier layer in the first area, the second area, the third area and the fourth area.
Preferably, the depositing a TiN layer on the first region, the second region and the third region on the high-K dielectric layer includes:
depositing a first layer of the TiN layer over the etch stop layer;
etching the second region and the third region to the etching barrier layer;
continuously laminating a second TiN layer above the etching barrier layer;
and etching the fourth region to the etching barrier layer.
Preferably, the depositing a filling layer in the first region, the second region, the third region and the fourth region on the high-K dielectric layer includes:
and sequentially depositing a TiAl layer, a TiN layer and metal tungsten in the first region, the second region, the third region and the fourth region on the high-K dielectric layer.
According to the SOI FinFET device, the gate threshold voltage is influenced by the TiN layer and the first/second doping layers, so that the gate structure of the SOI FinFET device has a wider threshold voltage adjusting range, a thick work function layer is not needed for ultra-low threshold voltage P-type devices (namely the first area and the second area), and the gate metal filling problem of the P-type devices is well improved.
When a first layer of a metal gate is formed, tiN is deposited and dopants which are needed by a P type device (namely a first area and a second area) and are used for increasing the effective work function are doped, then TiN in an N type area (namely a third area and a fourth area) is etched, tiN is deposited and dopants which are needed by the N type area and are used for reducing the effective work function are doped, the doping metering is controllable, and therefore the threshold voltage can be controlled. Compared with the mode of adjusting the threshold voltage by changing the thickness of the gate work function layer in the prior art, the adjusting range is larger, and the limitation problem is solved; for the ultra-low threshold voltage P-type FinFET device, a thick work function layer is not needed any more, and the gate metal filling problem of the P-type device is greatly improved. Furthermore, in the embodiment of the present invention, for different work function requirements of devices of each threshold voltage type, impurity metering is not required, but the requirements are met by subsequently depositing work function metal layers TiN with corresponding thicknesses in each region, and finally, filling of gate metal is completed. The thickness of the deposited work function metal layer is decreased aiming at the P type low threshold voltage device, the P type standard threshold voltage device, the N type low threshold voltage device and the N type standard threshold voltage device, so that the steps of multiple times of deposition, doping and etching can be omitted, and the P type low threshold voltage device, the N type low threshold voltage device, the P type standard threshold voltage device and the N type standard threshold voltage device can be manufactured on the same chip, so that the manufacturing cost of the manufacturing process is greatly reduced.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a schematic diagram illustrating the thickness structure of a gate contact metal and a work function metal layer in the prior art provided in the present invention;
fig. 2 is a schematic structural diagram illustrating a gate structure of an SOI FinFET device according to a first embodiment of the present invention;
fig. 3 is a flow chart illustrating a method of fabricating a gate structure of an SOI FinFET device in accordance with a second embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a gate structure when depositing a TiN layer and doping BF2 ions are performed according to a second embodiment of the present invention;
FIG. 5 is a schematic diagram of a gate structure when etching BF2 ion-doped TiN layers deposited in a third area and a fourth area is performed according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram of a gate structure when a TiN layer is deposited and P ions are doped in a second embodiment of the invention;
FIG. 7 is a diagram illustrating a gate structure during deposition of an etch stop layer according to a second embodiment of the present invention;
FIG. 8 is a schematic diagram of a gate structure during deposition of a first TiN layer on top of an etch stop layer in a second embodiment of the invention;
FIG. 9 is a schematic diagram showing a gate structure when etching of the first TiN layer over the second area and the third area etching barrier layer is performed in the second embodiment of the invention;
FIG. 10 is a schematic diagram of a gate structure when a second TiN layer is deposited over the etch stop layer in a second embodiment of the invention;
FIG. 11 is a schematic diagram showing a gate structure when etching a first TiN layer and a second TiN layer on the etching stop layer of the fourth area is performed according to the second embodiment of the invention;
fig. 12 is a schematic diagram of a gate structure after a filling layer is deposited in a second embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc. indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally placed when the products of the present invention are used, and are only for convenience of description and simplification of the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly stated or limited, the terms "disposed," "connected," and "connected" are to be construed broadly and may be, for example, directly connected, indirectly connected through intervening media, or interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
First embodiment
Referring to fig. 2, a schematic structural diagram of a gate structure 10 of an SOI FinFET device according to a first embodiment of the present invention is shown. The gate structure 10 of the SOI FinFET device comprises: a substrate having a source region and a drain region doped to form a set thereon; any one of a first region a, a second region b, a third region c and a fourth region d is arranged above the space between each group of the source region and the drain region; the four regions correspond to the following: the first region a is used for forming a gate of a P-type low threshold voltage device (pulsevt), the second region b is used for forming a gate of a P-type Standard threshold voltage device (PSVT), the third region c is used for forming a gate of an N-type low threshold voltage device (NULVT), and the fourth region d is used for forming a gate of an N-type Standard threshold voltage device (NSVT). A high-K dielectric layer 12, a first doping layer 13, a second doping layer 14, a TiN (titanium nitride) layer 160 and a filling layer 18 are sequentially arranged above the substrate of the first region a from bottom to top; wherein the first doping layer 13 is a TiN layer containing a dopant for increasing an effective work function, and the second doping layer 14 is a TiN layer containing a dopant for decreasing an effective work function; a high-K dielectric layer 12, a first doping layer 13, a second doping layer 14, a TiN layer 17 and a filling layer 18 are sequentially arranged above the substrate of the second area b from bottom to top; a high-K dielectric layer 12, a second doping layer 14, a TiN layer 17 and a filling layer 18 are sequentially arranged above the substrate of the third region c from bottom to top; a high-K dielectric layer 12, a second doped layer 14 and a filling layer 18 are sequentially arranged above the substrate of the fourth region d from bottom to top.
In this embodiment, the position structure of the source region and the drain region relative to the gate may refer to a relative position structure relationship in the existing FinFET device, and is not described again.
In the present embodiment, the thickness of the TiN layer 160 in the first region a is greater than the thickness of the TiN layer 17 in the second region b and the third region c; specifically, two TiN layers, i.e., the TiN layer 16 and the TiN layer 17, may be deposited in the first region a, and one TiN layer 17 may be deposited in the second region b and the third region c. By adjusting the thickness 160 of the TiN, the work function can be correspondingly changed, so that different threshold voltages can be realized.
Through the gate structure 10 of the SOI FinFET device, a deposition layer for increasing the effective work function can be obtained in a P-type device, a deposition layer for reducing the effective work function can be obtained in an N-type device, and the adjustment range of a voltage threshold is enlarged; furthermore, the thicker the TiN in the P-type device, the lower the threshold voltage, the thinner the TiN in the N-type device, the lower the threshold voltage, and the TiN deposition with different thicknesses is performed in different regions, so that the threshold voltage adjustment range of the gate structure 10 of the SOI FinFET device in this embodiment is larger, and the preparation is more flexible, thereby avoiding the filling problem caused by the thicker gate metal, and avoiding affecting the resistivity of the gate.
Further, an etching barrier layer 15 is disposed above the second doped layer 14 in each of the first region a, the second region b, the third region c and the fourth region d. The thickness of the deposited TiN can be more accurately controlled in the manufacturing process of the gate structure 10 by the arrangement of the etching barrier layer 15. Specifically, the etch stopper layer 15 is located between the second doped layer 14 and the TiN layer 16 in the first region a. The etch barrier layer 15 is located between the second doped layer 14 and the TiN layer 17 in the second region b. The etch-barrier layer 15 is located between the second doped layer 14 and the TiN layer 17 in the third region c, and the etch-barrier layer 15 is located between the second doped layer 14 and the filling layer 18 in the fourth region d.
The dopants for increasing the effective work function corresponding to the first doping layer 13 may be: BF (BF) generator 2 (boron fluoride), al (aluminum), B (boron), mo (molybdenum), pt (platinum), etc.; the corresponding dopants for reducing the effective work function of the second doped layer 14 may be: la (lanthanum), as (arsenic), sb (antimony), and the like.
The filling layer 18 is a TiAl layer (TiAl-based alloy), a TiN layer, and a metal W (tungsten) in this order from bottom to top, so as to form the complete gate structure 10.
In this embodiment, the substrate material is a Si (silicon) material. For the high K dielectric layer 12, al in this embodiment 2 O 3 (alumina) dielectric constant is too low, zrO 2 (zirconium dioxide) and TiO 2 (titanium dioxide) readily reacted with Si substrate, la 2 O 3 (lanthanum oxide) readily absorbs water; therefore, the preferred high-K dielectric layer 12 is the following: hfO 2 (hafnium oxide), hfSiO 4 (hafnium orthosilicate), hfON (hafnium oxynitride), hfAlO (hafnium aluminum oxide), hfSiO (hafnium silicate), hfSiON (hafnium silicon oxynitride), and the like. In addition, an IL layer (interface layer) may be deposited between the substrate and the high-K dielectric layer 12 for improving the contact characteristics between the substrate and the high-K dielectric layer 12, and the interface layer may be SiO2.
The SOI FinFET device in this embodiment may be fabricated to form different device types, such as a P-type low threshold voltage region, a P-type standard threshold voltage region, an N-type low threshold voltage region, and an N-type standard threshold voltage region, on the same chip, and the gate structure 10 of the SOI FinFET device in this embodiment is fabricated without using ion implantation doping, thereby avoiding damage to the metal film due to large ion implantation doping energy. In the gate structure 10 in this embodiment, the gate threshold voltage is affected by the TiN layer and the first/second doping layer 14, so that the gate structure 10 of the SOI FinFET has a wider threshold voltage adjustment range, and thus the ultra-low threshold voltage P-type FinFET does not need a thick work function layer any longer, and the problem of filling the gate metal of the P-type FinFET is well improved.
Second embodiment
Referring to fig. 3, a method for fabricating an SOI FinFET device is also provided in the present embodiment, and a method flowchart of the method is shown in fig. 2.
Specifically, the method for manufacturing the SOI FinFET device includes:
step S10: depositing a first doping layer on a first area and a second area on a high-K dielectric layer on a substrate; wherein the substrate has a set of source and drain regions, the first and second regions being located above and between the set of source and drain regions, respectively, the first region being for forming a gate of a P-type low threshold voltage device and the second region being for forming a gate of a P-type standard threshold voltage device, wherein the first doped layer is a TiN layer containing a dopant that increases the effective work function;
step S20: continuously depositing a second doping layer on the first region, the second region, the third region and the fourth region on the high-K dielectric layer; the second region and the third region are respectively positioned above the grouped source region and drain region, the third region is used for forming a grid electrode of an N-type low threshold voltage device, the fourth region is used for forming a grid electrode of an N-type standard threshold voltage device, and the second doping layer is a TiN layer containing a dopant for reducing an effective work function;
step S30: continuing to deposit TiN layers on the first region, the second region and the third region on the high-K dielectric layer;
step S40: and continuously depositing filling layers in the first area, the second area, the third area and the fourth area on the high-K dielectric layer.
In step S10, the specific implementation may be: doping to form a group of source and drain regions on the substrate, and depositing a first doped layer on the high-K dielectric layer above and between the group of source and drain regions. Specifically, a first metal gate TiN is deposited by PEALD (Plasma Enhanced Atomic Layer Deposition), and a dopant capable of increasing the effective work function, such as BF, is doped in situ 2 As shown in fig. 4. Further, a BARC layer (Bottom Anti-Reflective Coatings) is coated on the first doped layer, and the BARC layers of the third and fourth regions are stripped, as shown in fig. 5. And finally, removing the first doping layers of the third region and the fourth region by adopting an etching method, and stopping etching on the high-K layer dielectric layer, namely only keeping the first doping layers on the first region and the second region. The BARC layer on the first doped layer is stripped after the etch is completed for subsequent deposition steps. PEALD (atomic layer deposition) is an improved technology of the traditional ALD (atomic layer deposition), and is formed by adding a plasma discharge device in an ALD (atomic layer deposition) device, PEALD in-situ doping is plasma discharge doping while depositing a metal gate thin film, so that monoatomic layer deposition can be realized, and the technology is overThe process is the same as ALD, the method is suitable for a FinFET three-dimensional gate structure, and the quantity of deposited impurities in the deposition process can be accurately controlled by parameters such as plasma power, gas inflow flow and the like; in addition, the PEALD in-situ doping can realize surface deposition, and the impurity quantity requirement in the deposition process is low, so that the plasma power can be greatly reduced, and the damage to the surface structure of the grid electrode caused by ion implantation is less.
Further, step S20 is performed. In step S20, a second doped layer is deposited by PEALD, specifically, a layer of TiN is deposited, and a dopant, such as P, which can reduce the effective work function is doped by an in-situ doping method, as shown in fig. 6.
In order to facilitate etching, the accuracy of etching is improved. In this embodiment, a deposition of an etching barrier layer may be performed after step S20 and before step S30, as shown in fig. 7. Specifically, an etching barrier layer is deposited in the first region, the second region, the third region and the fourth region. And in the first region, the second region, the third region and the fourth region, the etching barrier layer is connected with the second doped layer. The etch stop layer may be TaN (tantalum nitride).
Further, step S30 is performed. In step S30, a first TiN layer is first atomic layer deposited on the etch stop layer, as shown in fig. 8. Then, a BARC layer is applied and the BARC layer over the second and third regions is stripped, followed by etching away the first TiN layer in both regions, i.e., etching stops at the TaN layer (etch stop layer), as shown in fig. 9. The BARC layers of the first and fourth regions are stripped and the deposition of a second TiN layer is continued over the etch stop layer, as shown in fig. 10. Further, a BARC layer is applied, the BARC layer in the fourth region is stripped, then the first TiN layer and the second TiN layer in the region are etched away, and the etching stops at the TaN layer, as shown in FIG. 11. Finally, the remaining BARC layer is removed. Therefore, the redundant TiN layers (the first TiN layer and the second TiN layer) in the fourth area can be removed at one time, the clear operation of multiple BARC layers in the fourth area is avoided, and the manufacturing steps are simplified. Meanwhile, two TiN layers can be deposited above the etching barrier layer in the first area through the operation, so that a thicker TiN layer is obtained, and a lower threshold voltage is obtained.
Further, step S40 is performed, specifically, a TiAl layer and a TiN layer are sequentially deposited in the first region, the second region, the third region and the fourth region on the high-K dielectric layer, and finally, the Tial layer, the TiN layer and the TiN layer are filled with metal tungsten, as shown in fig. 12.
The method in the embodiment can realize the following beneficial effects:
1. by adopting the preparation method in the embodiment to manufacture the SOI FinFET device, the thickness of the work function metal of the grid electrode can be effectively controlled, the subsequent metal filling of the grid electrode cannot be influenced, and the stability of the resistivity of the grid electrode of the device is ensured. Specifically, in this embodiment, a TiN layer is deposited on the high-K dielectric layer by using PEALD, and simultaneously, impurities are doped by using a PEALD in-situ doping method, impurities capable of increasing an effective work function are doped in the P-type region (the first region and the second region), impurities capable of reducing an effective work function are doped in the N-type region (the third region and the fourth region), and the doping amount is controllable, so that the threshold voltage can be controlled. Compared with the mode of adjusting the threshold voltage by changing the thickness of the gate work function layer in the prior art, the adjusting amplitude is larger, and the problem of manufacturing limitation is solved; for the ultra-low threshold voltage P-type FinFET device, a thick work function layer is not needed any more, and the gate metal filling problem of the P-type device is greatly improved.
2. In the prior art, there is a manufacturing method that the MOS FET device in the high-K metal gate process can adjust the threshold voltage by ion implantation of impurities into the first layer of metal gate. Specifically, a dopant capable of increasing the effective work function is implanted into the first metal gate of the P-type device, and a dopant capable of reducing the effective work function is implanted into the first metal gate of the N-type device, so as to adjust the threshold voltage. On one hand, the implementation mode of the prior art has larger ion implantation doping energy, can damage the metal film, and is especially suitable for Fin FET devices under advanced process nodes; on the other hand, the work functions of the P-type device and the N-type device are different: the effective work function of the P-type device should be near the top of the valence band of Si, and the work function of the N-type device should be near the bottom of the conduction band of Si; the same type device can be divided into an ultra-low threshold voltage device and a standard threshold voltage device according to different threshold voltages, and work function requirements are different. If devices of different types and different threshold voltages need to be formed on one chip, different doping types or different measurements needed by different devices during the manufacturing process of the gate electrode need to be performed for the P-type low threshold voltage device, the P-type standard threshold voltage device, the N-type low threshold voltage device and the N-type standard threshold voltage device respectively, so that the process is complex and the cost is high. The manufacturing method of the SOI FinFET device in the embodiment adopts a PEALD in-situ doping technology for doping, and compared with ion implantation doping, the technology has the advantages that the energy is smaller, and the damage to the surface structure of the grid electrode is smaller; meanwhile, when the first layer of the metal gate is formed, tiN is deposited and dopants which are needed by the P-type devices (namely the first area and the second area) and are used for increasing the effective work function are doped, then TiN in the N-type areas (namely the third area and the fourth area) is etched, and then TiN is deposited and dopants which are needed by the N-type areas and are used for reducing the effective work function are doped. For different work function requirements of devices of various threshold voltage types, impurity metering is not needed, the work function requirements are met by depositing work function metal layers TiN with corresponding thickness in various regions subsequently, and finally filling of gate metal is completed. The thickness of the deposited work function metal layer is decreased aiming at the P type low threshold voltage device, the P type standard threshold voltage device, the N type low threshold voltage device and the N type standard threshold voltage device, so that the steps of multiple times of deposition, doping and etching can be omitted, and the P type low threshold voltage device, the N type low threshold voltage device, the P type standard threshold voltage device and the N type standard threshold voltage device can be manufactured on the same chip, so that the manufacturing cost of the manufacturing process is greatly reduced.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

Claims (10)

1. A soi finfet device, comprising:
a substrate having a source region and a drain region doped to form a set thereon;
any one of a first region, a second region, a third region and a fourth region is arranged above the space between each group of the source region and the drain region; the first region is used for forming a grid electrode of a P-type low threshold voltage device, the second region is used for forming a grid electrode of a P-type standard threshold voltage device, the third region is used for forming a grid electrode of an N-type low threshold voltage device, and the fourth region is used for forming a grid electrode of an N-type standard threshold voltage device;
the first region is sequentially provided with a high-K dielectric layer, a first doping layer, a second doping layer, a TiN layer and a filling layer from bottom to top; the first doping layer is a TiN layer containing a dopant for increasing the effective work function, and the second doping layer is a TiN layer containing a dopant for reducing the effective work function;
the second region is sequentially provided with the high-K dielectric layer, the first doping layer, the second doping layer, the TiN layer and the filling layer from bottom to top;
the third region is sequentially provided with the high-K dielectric layer, the second doping layer, the TiN layer and the filling layer from bottom to top;
the fourth region is sequentially provided with the high-K dielectric layer, the second doping layer and the filling layer from bottom to top.
2. The soi finfet device of claim 1, wherein an etch stop layer is disposed over the second doped layer in any one or more of the first, second, third and fourth regions.
3. The SOI FinFET device of claim 1, wherein a thickness of the TiN layer in the first region is greater than a thickness of the TiN layer in the second region.
4. The SOI FinFET device of claim 1, wherein the fill layer is a TiAl layer, a TiN layer and metal tungsten in sequence from bottom to top.
5. The SOI FinFET device of claim 1, wherein the first doped layer is BF 2 The second doping layer is a TiN layer of P ions.
6. A method for fabricating a SOFFINFET device, comprising:
depositing a first doping layer on a first region and a second region on a high-K dielectric layer on a substrate; wherein the substrate has a set of source and drain regions, the first and second regions being located above and between the set of source and drain regions, respectively, the first region being for forming a gate of a P-type low threshold voltage device and the second region being for forming a gate of a P-type standard threshold voltage device, wherein the first doped layer is a TiN layer containing a dopant that increases the effective work function;
continuously depositing a second doping layer on the first region, the second region, the third region and the fourth region on the high-K dielectric layer; the second region and the third region are respectively positioned above the grouped source regions and drain regions, the third region is used for forming a grid electrode of an N-type low threshold voltage device, the fourth region is used for forming a grid electrode of an N-type standard threshold voltage device, and the second doping layer is a TiN layer containing a dopant for reducing an effective work function;
continuing to deposit TiN layers on the first region, the second region and the third region on the high-K dielectric layer;
and continuously depositing filling layers in the first area, the second area, the third area and the fourth area on the high-K dielectric layer.
7. The method of claim 6, wherein depositing a first doped layer in the first region and the second region on the high-K dielectric layer on the substrate comprises:
depositing a first doping layer on the high-K dielectric layer on the substrate;
coating a BARC layer on the first doping layer, and stripping the BARC layer of the third area and the fourth area;
and removing the first doping layer in the third region and the fourth region by adopting an etching method.
8. The method of claim 6, wherein after the depositing a second doped layer on the high-K dielectric layer in the first, second, third, and fourth regions and before the depositing a TiN layer on the high-K dielectric layer in the first, second, and third regions, further comprises:
depositing an etch stop layer in the first region, the second region, the third region, and the fourth region.
9. The method of claim 8, wherein depositing a TiN layer on the first, second, and third regions on the high-K dielectric layer comprises:
depositing a first layer of the TiN layer over the etch stop layer;
etching the second region and the third region to the etching barrier layer;
continuously laminating a second TiN layer above the etching barrier layer;
and etching the fourth region to the etching barrier layer.
10. The method of claim 6, wherein depositing a fill layer on the first, second, third, and fourth regions on the high-K dielectric layer comprises:
and sequentially depositing a TiAl layer, a TiN layer and metal tungsten in the first region, the second region, the third region and the fourth region on the high-K dielectric layer.
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