CN108258028A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN108258028A CN108258028A CN201611239033.7A CN201611239033A CN108258028A CN 108258028 A CN108258028 A CN 108258028A CN 201611239033 A CN201611239033 A CN 201611239033A CN 108258028 A CN108258028 A CN 108258028A
- Authority
- CN
- China
- Prior art keywords
- areas
- work
- layer
- function layer
- gate dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 68
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000005530 etching Methods 0.000 claims abstract description 74
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 63
- 239000001301 oxygen Substances 0.000 claims abstract description 63
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 63
- 238000002161 passivation Methods 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims description 72
- 239000000758 substrate Substances 0.000 claims description 57
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 21
- 238000001039 wet etching Methods 0.000 claims description 16
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 14
- 229910052718 tin Inorganic materials 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 229910004166 TaN Inorganic materials 0.000 claims description 8
- 229910004200 TaSiN Inorganic materials 0.000 claims description 8
- 229910008482 TiSiN Inorganic materials 0.000 claims description 8
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 7
- 229910010038 TiAl Inorganic materials 0.000 claims description 6
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 claims description 4
- 229910004491 TaAlN Inorganic materials 0.000 claims description 4
- 229910010041 TiAlC Inorganic materials 0.000 claims description 4
- 229910010037 TiAlN Inorganic materials 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 372
- 239000000243 solution Substances 0.000 description 28
- 230000005611 electricity Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 230000009931 harmful effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, forming method includes：The first work-function layer is etched, retains the first work-function layer positioned at the 2nd P areas, the first N areas and the 2nd N areas；After the first work-function layer is etched, the second work-function layer is formed in the first N areas, the 2nd N areas, the first P areas and the 2nd P areas；Second work-function layer in the 2nd N areas of etching removal, until exposing the gate dielectric layer in the 2nd N areas；Lacking oxygen Passivation Treatment is carried out to the gate dielectric layer in the 2nd N areas, reduces the Lacking oxygen content in the gate dielectric layer in the 2nd N areas；Etching removes second work-function layer in the first N areas, until exposing the gate dielectric layer in the first N areas；Third work-function layer is formed on the gate dielectric layer in the first N areas and the 2nd N areas and in second work-function layer in the first P areas and the 2nd P areas.Present invention reduces semiconductor structures to form process complexity, has saved processing step.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
The main semiconductor devices of integrated circuit especially super large-scale integration is Metal-oxide-semicondutor field effect
It should manage (MOS transistor).With the continuous development of production of integrated circuits technology, semiconductor device art node constantly reduces, and half
The geometric dimension of conductor structure follows Moore's Law and constantly reduces.It is various when semiconductor structure is reduced in size to a certain degree
Because second-order effect caused by the physics limit of semiconductor structure occurs in succession, the characteristic size of semiconductor structure contracts in proportion
It is small to become more and more difficult.Wherein, in field of semiconductor fabrication, most challenging is how to solve semiconductor structure leakage current
The problem of big.The leakage current of semiconductor structure is big, caused mainly by the constantly reduction of traditional gate dielectric layer thickness.
The solution currently proposed is to replace traditional silicon dioxide gate dielectric material using high-k gate dielectric material, and
Using metal as gate electrode, fermi level pinning effect occurs with conventional gate electrodes material to avoid high-g value and boron oozes
Penetration effect.The introducing of high-k/metal gate reduces the leakage current of semiconductor structure.
It is existing although the introducing of high-k/metal gate can improve the electric property of semiconductor structure to a certain extent
There is the semiconductor structure complex process that technology is formed.
Invention content
It is of the invention to solve the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, meeting semiconductor structure to threshold
While threshold voltage different demands, simplify processing step.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, it is described
Substrate includes being used to form the first N areas of the first N-type device, the 2nd N areas for being used to form the second N-type device, is used to form the
First P areas of one P-type device and the 2nd P areas for being used to form the second P-type device, and the threshold value electricity of the first N-type device
Pressure is less than the threshold voltage of the second N-type device, and the threshold voltage of first P-type device is more than the threshold value electricity of the second P-type device
Pressure；Gate dielectric layer is formed in the substrate in the first N areas, the 2nd N areas, the first P areas and the 2nd P areas and positioned at the grid
The first work-function layer on dielectric layer；It etches first work-function layer, retains positioned at the 2nd P areas, the first N areas and the
First work-function layer in two N areas；After first work-function layer is etched, in the first N areas, the 2nd N areas, the first P areas
And the 2nd form the second work-function layer in P areas；Etching removes second work-function layer and the first work function in the 2nd N areas
Layer, until the gate dielectric layer in the 2nd N areas is exposed, until exposing the gate dielectric layer in the 2nd N areas；To described second
The gate dielectric layer in N areas carries out Lacking oxygen Passivation Treatment, reduces the Lacking oxygen content in the gate dielectric layer in the 2nd N areas；Etching
Second work-function layer and the first work-function layer in the first N areas are removed, until exposing the gate medium in the first N areas
Layer；On the gate dielectric layer in the first N areas and the 2nd N areas and second work-function layer in the first P areas and the 2nd P areas
Upper formation third work-function layer.
Optionally, using wet-etching technology, etching removes second work-function layer in the 2nd N areas, until exposing
The gate dielectric layer in the 2nd N areas, and the etch liquids of the wet-etching technology have oxidisability.
Optionally, the wet-etching technology includes main etching technique and over etching technique, wherein, it is carved using described cross
Etching technique carries out the Lacking oxygen Passivation Treatment.
Optionally, the etch liquids that the wet-etching technology uses is SC1 solution, SC2 solution or SPM solution.
Optionally, the etching duration of the over etching technique is 10s~2min.
Optionally, using the processing solution containing hydrogen peroxide, the Lacking oxygen Passivation Treatment is carried out.
Optionally, in the processing solution, hydrogen peroxide mass concentration is 5%~20%, and processing solution temperature is 20 DEG C
~50 DEG C.
Optionally, the processing solution is SC1 solution, SC2 solution or SPM solution.
Optionally, first carry out the Lacking oxygen Passivation Treatment, rear etching remove second work-function layer in the first N areas with
And first work-function layer.
Optionally, the material of the gate dielectric layer is high-k gate dielectric material.
Optionally, before the gate dielectric layer is formed, also in the first N areas, the 2nd N areas, the first P areas and second
Boundary layer is formed in the substrate in P areas.
Optionally, the material of the material of first work-function layer, the second work-function layer and third work-function layer is P
Type work function material.
Optionally, the p-type work function material includes one or more of Ta, TiN, TaN, TaSiN or TiSiN.
Optionally, step is further included：Third work function in the first N areas, the 2nd N areas, the first P areas and the 2nd P areas
N-type workfunction layer, and the material of the material work functions type of the N-type workfunction layer and the third work-function layer are formed on layer
Work function type is different；Gate electrode layer is formed on the N-type workfunction layer.
Optionally, the material of the N-type workfunction layer is one in TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN
Kind is several.
Optionally, the processing step for etching first work-function layer includes：In the first N areas, the 2nd N areas and second
The first graph layer is formed in first work-function layer in P areas；Using first graph layer as mask, etching removal is located at described first
First work-function layer in P areas；Remove first graph layer.
Optionally, etching removes second work-function layer in the first N areas and the processing step packet of the first work-function layer
It includes：Second is formed on the gate dielectric layer in the 2nd N areas and in second work-function layer in the first P areas and the 2nd P areas
Graph layer；Using the second graph layer as mask, etching removes second work-function layer and the first work function in the first N areas
Layer；Remove the second graph layer.The present invention also provides a kind of semiconductor structure, including：Substrate, the substrate include having the
First N areas of one N-type device, the 2nd N areas with the second N-type device, the first P areas with the first P-type device and with
2nd P areas of the second P-type device, and the threshold voltage of the first N-type device is less than the threshold voltage of the second N-type device, institute
The threshold voltage for stating the first P-type device is more than the threshold voltage of the second P-type device；Positioned at the first N areas, the 2nd N areas, first
Gate dielectric layer in the substrate in P areas and the 2nd P areas, wherein, Lacking oxygen content is more than institute in the gate dielectric layer in the first N areas
State Lacking oxygen content in the gate dielectric layer in the 2nd N areas；The first work-function layer on the gate dielectric layer in the 2nd P areas；Position
In the second work-function layer on the gate dielectric layer in the first P areas and in first work-function layer in the 2nd P areas；Positioned at described
Third work content on the gate dielectric layer in one N areas and the 2nd N areas and in second work-function layer in the first P areas and the 2nd P areas
Several layers.
Optionally, the material of the material of first work-function layer, the material of the second work-function layer and third work-function layer
Material is p-type work function material.
Optionally, the semiconductor structure further includes：N-type workfunction layer in the third work-function layer；It is located at
Gate electrode layer on the N-type workfunction layer.
Compared with prior art, technical scheme of the present invention has the following advantages：
In the technical solution of the forming method of semiconductor structure provided in an embodiment of the present invention, there are different threshold values being formed
The the first N-type device and the second N-type device of voltage have the first P-type device and the second P-type device of different threshold voltages
Technical process in, Lacking oxygen Passivation Treatment is carried out to the gate dielectric layer in the 2nd N areas so that oxygen in the gate dielectric layer in the first N areas
Vacancy content is more than Lacking oxygen content in the gate dielectric layer in the 2nd N areas, passes through difference the first N-type device of Lacking oxygen content
There is otherness with the threshold voltage of the second N-type device；Therefore, the third work-function layer of formation is both also located at positioned at the first N areas
2nd N areas, avoid the processing step of the third work-function layer in the first N areas of etching removal, and not necessarily form the 4th work-function layer,
So as to simplify processing step, and meets the needs of the first N-type device threshold voltage is less than the second N-type device threshold voltage.And
And the quantity of the work-function layer film layer The present invention reduces formation so that the semiconductor structure of formation is simpler, and cause after
The continuous process window for forming gate electrode layer increases.
In alternative, second work-function layer in the 2nd N areas, and institute are located at using wet-etching technology etching removal
It states wet-etching technology and includes main etching technique and over etching technique, it is blunt to carry out the Lacking oxygen using the over etching technique
Change is handled, and there is no need to additional processing steps to carry out the Lacking oxygen Passivation Treatment.
Description of the drawings
Fig. 1 to Fig. 3 is a kind of corresponding cross-sectional view of each step of method for forming semiconductor structure；
Fig. 4 to Figure 11 shows for the corresponding cross-section structure of each step of method for forming semiconductor structure provided in an embodiment of the present invention
It is intended to.
Specific embodiment
By background technology it is found that the electric property for the semiconductor structure that the prior art is formed is to be improved.Especially when half
Conductor structure includes P-type device with different threshold voltages (Threshold Voltage) and with different threshold values electricity
During the N-type device of pressure, the problem of semiconductor structure forms complex process, is especially pronounced.
In order to meet the requirement of NMOS tube and PMOS tube improvement threshold voltage simultaneously, the different metal material of generally use is made
For work function (WF, Work Function) layer material in the gate structure of NMOS tube and PMOS tube, the work function in NMOS tube
Layer material can be described as N-type work function material, and the work-function layer material in PMOS tube can be described as p-type work function material.Generally use
The mode of the thickness of the P-type workfunction layer between gate dielectric layer and N-type workfunction layer is adjusted, realization meets device difference threshold value electricity
The demand of pressure.
Fig. 1 to Fig. 3 is a kind of corresponding cross-sectional view of each step of method for forming semiconductor structure.
With reference to figure 1, substrate 11 is provided, the substrate 11 includes the first N areas 101 and the 2nd N areas 102, the first N areas 101
The first N-type device is used to form, the 2nd N areas 104 are used to form the second N-type device, and the threshold voltage of the first N-type device is less than
The threshold voltage of second N-type device；Boundary layer 12 is formed in the substrate 11；Gate dielectric layer is formed on the boundary layer 12
13；Formed on 101 gate dielectric layer 13 of the first N areas the first work-function layer 14 and in the first work-function layer 14
Two work-function layers 15；Shape in second work-function layer 15 in the first N areas 101 and on the gate dielectric layer 13 in the 2nd N areas 101
Into third work-function layer 16.
The substrate further includes the first P areas and the 2nd P areas, and the P-type device threshold voltage and the 2nd P that the first P areas are formed
The P-type device threshold voltage that area is formed is different.
With reference to figure 2, etching removal is located at third work-function layer 16, the second work-function layer 15 in the first N areas 101
(with reference to figure 1) and the first work-function layer 14 exposes 13 surface of gate dielectric layer in the first N areas 101.
With reference to figure 3, on the gate dielectric layer 13 in the first N areas 101 and the third work-function layer 16 in the 2nd N areas 102
The 4th work-function layer 17 of upper formation.
Above-mentioned forming method is complicated, and in order to meet the first N-type device, the second N-type device, the first P-type device and the
Two P-type devices need to be formed at least four layers of work-function layer to the different demands of threshold voltage.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, it is described
Substrate includes being used to form the first N areas of the first N-type device, the 2nd N areas for being used to form the second N-type device, is used to form the
First P areas of one P-type device and the 2nd P areas for being used to form the second P-type device, and the threshold value electricity of the first N-type device
Pressure is less than the threshold voltage of the second N-type device, and the threshold voltage of first P-type device is more than the threshold value electricity of the second P-type device
Pressure；Gate dielectric layer is formed in the substrate in the first N areas, the 2nd N areas, the first P areas and the 2nd P areas and positioned at the grid
The first work-function layer on dielectric layer；First work-function layer is etched, retains the first work function positioned at the 2nd P areas
Layer；After first work-function layer is etched, formed in the first N areas, the 2nd N areas, the first P areas and the 2nd P areas
Second work-function layer；Etching removes second work-function layer in the 2nd N areas, until exposing the gate medium in the 2nd N areas
Layer；Lacking oxygen Passivation Treatment is carried out to the gate dielectric layer in the 2nd N areas, reduces the oxygen in the gate dielectric layer in the 2nd N areas
Vacancy content；Etching removes second work-function layer in the first N areas, until exposing the gate dielectric layer in the first N areas；
It is formed on the gate dielectric layer in the first N areas and the 2nd N areas and in second work-function layer in the first P areas and the 2nd P areas
Third work-function layer.
The present invention formed with the first N-type device of different threshold voltages, the second N-type device, the first P-type device and
While second P-type device, processing step has been saved, has simplified process complexity, and cause the work-function layer film layer number formed
Amount is few.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 11 shows for the corresponding cross-section structure of each step of method for forming semiconductor structure provided in an embodiment of the present invention
It is intended to.
With reference to figure 4, substrate 201 is provided.
The substrate 201 includes the first N areas I1 for being used to form the first N-type device, be used to form the second N-type device the
Two N areas I2, it is used to form the first P areas II1 of the first P-type device and is used to form the 2nd P areas II2 of the second P-type device, and
The threshold voltage of the first N-type device is less than the threshold voltage of the second N-type device, the threshold voltage of first P-type device
More than the threshold voltage of the second P-type device.
Adjacent with the first N areas I2 and the 2nd N areas I2, the 2nd N areas I2 and the first P areas II1 are adjacent, described
First P areas II1 and the 2nd P areas II2 is adjacent to be used as example.
In the present embodiment, by the semiconductor structure of formation for for planar device, the substrate 201 is planar substrate；Institute
The material for stating substrate 201 is silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium, and the substrate 201 also is able to as insulator
On silicon substrate or insulator on germanium substrate.
In other embodiments, the semiconductor structure of formation be fin field effect pipe when, the substrate include substrate and
Fin on the substrate, the substrate further include, positioned at the fin expose substrate on isolation structure, it is described every
Partial sidewall from structure covering fin, and less than at the top of the fin at the top of the isolation structure.
In the present embodiment, the first N areas I1 includes N-type ultralow threshold value voltage (ULVT, Ultra-low VT) area and N
Type low threshold voltage (low VT) area；The 2nd N areas I2 is N-type standard threshold voltage area (Standard VT).In other realities
It applies in example, the first N areas can also only include one kind in N-type low-threshold power pressure area or N-type ultralow threshold value voltage zone.
In the present embodiment, the first P areas II1 is p-type standard threshold voltage area, and the 2nd P areas II2 surpasses including p-type
Low-threshold power pressure area and p-type low-threshold power pressure area.In other embodiments, it is ultralow can also only to include p-type for the 2nd P areas
One kind in threshold voltage area or p-type low-threshold power pressure area.
It should be noted that in the present embodiment, before gate dielectric layer 203 is subsequently formed, further include：The N-type is surpassed
The corresponding substrate 201 of low-threshold power pressure area carries out the first N-type threshold value and adjusts doping treatment, to the N-type low-threshold power pressure area pair
The substrate 201 answered carries out the second N-type threshold value and adjusts doping treatment；To the corresponding substrate 201 in the p-type ultralow threshold value voltage zone into
The first p-type of row threshold value adjusts doping treatment, and the second p-type threshold value tune is carried out to the corresponding substrate 201 of the p-type low-threshold power pressure area
Save doping treatment.
Specifically, the first N-type threshold value adjusts doping treatment and the second N-type threshold value adjusts the Doped ions of doping treatment
For N-type ion, N-type ion includes P, As or Sb, and the doping concentration that the first N-type threshold value adjusts doping treatment is less than described the
Two N-type threshold values adjust the doping concentration of doping treatment.The first p-type threshold value adjusts doping treatment and the second p-type threshold value is adjusted
The Doped ions of doping treatment are p-type ion, and p-type ion includes B, Ga or In, and the first p-type threshold value adjusts doping treatment
Doping concentration is less than the doping concentration that the second p-type threshold value adjusts doping treatment.
In the present embodiment, to form formation gate electrode layer (high k last metal after high-k gate dielectric layer after use
Gate last) technique, formed for the gate structure of semiconductor structure.Before gate dielectric layer 203 is formed, further include：
Pseudo- grid are formed in the substrate 201 of the first N areas I1, the 2nd N areas I2, the first P areas II1 and the 2nd P areas II2
Structure, wherein, since the first N areas I1 and the first P areas II1 are adjacent, dummy gate structure is across the first N areas
I1 and the first P areas II1, correspondingly, the gate electrode layer being subsequently formed is across the first N areas I1 and the first P areas II1.
After dummy gate structure is formed, the source of each device is formed in the substrate 201 of each region puppet grid structure both sides
Leak doped region；After the source and drain doping area is formed, inter-level dielectric is formed in the substrate 201 that is exposed in dummy gate structure
Layer, the interlayer dielectric layer expose the top of dummy gate structure；After the interlayer dielectric layer is formed, the pseudo- grid are removed
Structure.
Subsequently on the part of substrate 201 of the first N areas I1, the 2nd N areas I2, the first P areas II1 and the 2nd P areas II2
Form the gate dielectric layer 203.It should be noted that it in other embodiments, can also use after being initially formed high-k gate dielectric layer
The technique for forming gate electrode layer (high k first metal gate last), forms the semiconductor structure.
With continued reference to Fig. 4, in the substrate of the first N areas I1, the 2nd N areas I2, the first P areas II1 and the 2nd P areas II2
Gate dielectric layer 203 and the first work-function layer 204 on the gate dielectric layer 203 are formed on 201.
The material of the gate dielectric layer 203 is high-k gate dielectric material, wherein, high-k gate dielectric material is relative dielectric constant
More than the gate dielectric material of silica relative dielectric constant.
In the present embodiment, the material of the gate dielectric layer 203 is HfO2.In other embodiments, the gate dielectric layer
Material can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2Or Al2O3。
In order to improve the interface performance between the substrate 201 and the gate dielectric layer 203, the gate dielectric layer is being formed
Before 203, boundary layer 202 is formed also in the substrate 201, correspondingly, the gate dielectric layer 203 is located at the boundary layer
202 surfaces.
The boundary layer 202 provides good interface basis to form the gate dielectric layer 203, so as to improve the grid of formation
The quality of dielectric layer 203 reduces the interface state density between the gate dielectric layer 203 and the substrate 201, and avoids the grid
Harmful effect caused by dielectric layer 203 is in direct contact with the substrate 201.
In the present embodiment, the material of the boundary layer 202 is silica.In other embodiments, the material of the boundary layer
Material can also be silicon nitride or silicon oxynitride.
The material of first work-function layer 204 is p-type work function material.Specifically, on the 2nd P areas II2
A part of first work-function layer 204 as the corresponding work-function layer of the second P-type device, for adjusting the second p-type device
The threshold voltage of part.
The p-type work function material workfunction range is 5.1eV to 5.5eV, for example, 5.2eV, 5.3eV or 5.4eV.Institute
The material for stating the first work-function layer 204 is one or more of Ta, TiN, TaN, TaSiN or TiSiN, and chemical gas may be used
Phase depositing operation, physical gas-phase deposition or atom layer deposition process form first work-function layer 204.
In the present embodiment, the material of first work-function layer 204 is TiN, and the thickness of first work-function layer 204 is
10 angstroms~30 angstroms.
With reference to figure 5, etch first work-function layer 204, retain positioned at the 2nd P areas II2, the first N areas I1 and
The first work-function layer 204 of 2nd N areas I2.
In the present embodiment, first work-function layer 204 is etched, retains the first work function positioned at the first P areas II2
Layer 204, including：Etching removes the first work-function layer 204 of the first P areas II1, retains positioned at the first N areas I1, second
The first work-function layer 204 of N areas II2 and the 2nd P areas II2.
Specifically, the processing step for etching first work-function layer 204 includes：In the first N areas I1, the 2nd N areas
The first graph layer is formed in the first work-function layer 204 of I2 and the 2nd P areas II2；Using first graph layer as mask, etching is gone
Except the first work-function layer 204 positioned at the first P areas II1；Remove first graph layer.
In the present embodiment, in the technical process for etching first work-function layer 204, retain and be located at the first N areas
The first work-function layer 204 of I1 and the 2nd N areas I2 avoid making the gate dielectric layer 203 of the first N areas I1 and the 2nd N areas I2
Into etching injury, the damage that the gate dielectric layer 203 of the first N areas I1 and the 2nd N areas I2 is subject in technical process is reduced.
With reference to figure 6, after first work-function layer 204 is etched, in the first N areas I1, the 2nd N areas I2, the first P
The second work-function layer 205 is formed on area II1 and the 2nd P areas II2.
In the present embodiment, second work-function layer 205 is formed, including：In the first N areas I1, the 2nd N areas I2 and
Second work-function layer is formed in the first work-function layer 204 of two P areas II2 and on the gate dielectric layer 203 of the first P areas II1
205。
The material of second work-function layer 205 is p-type work function material.The second work(on the first P areas II1
Function layer 205 is a part for the corresponding work-function layer of the first P-type device, plays the threshold value electricity for adjusting first P-type device
The effect of pressure；The second work-function layer 205 on the 2nd P areas II2 is the one of the corresponding work-function layer of the second P-type device
The threshold voltage of second P-type device is played the role of adjusting in part.
The material of second work-function layer 205 is one or more of Ta, TiN, TaN, TaSiN or TiSiN.
In the present embodiment, the material of second work-function layer 205 is TiN, and the thickness of second work-function layer 205 is
10 angstroms~30 angstroms.
With reference to figure 7, etching removes the second work-function layer 205 and the first work-function layer 204 of the 2nd N areas I2, cruelly
Expose the gate dielectric layer 203 of the 2nd N areas I2.
In the present embodiment, due to aforementioned before the second work-function layer 205 is formed, remain positioned at the 2nd N areas I2
The first work-function layer 204；Therefore, etching removes the second work-function layer 205 of the 2nd N areas I2, including：Etching removal institute
The second work-function layer 205 of the 2nd N areas I2 is stated, and also etching removes the first work-function layer 204 of the 2nd N areas I2.
Before the second work-function layer 205 for removing the 2nd N areas I2 in etching, further include：The first N areas I1,
Mask layer 200 is formed in the second work-function layer 205 of first P areas II1 and the 2nd P areas II2.
In the present embodiment, the material of the mask layer 200 is silicon nitride.In other embodiments, the material of the mask layer
Material can also be Other substrate materials.
The mask layer 200 plays the second work-function layer of the first N areas I1 of protection, the first P areas II1 and the 2nd P areas II2
205 effects being not etched.Also, in the present embodiment, after subsequently Lacking oxygen Passivation Treatment is carried out, the mask layer is removed
200, the mask layer 200 is also during Lacking oxygen Passivation Treatment to the first N areas I1, the first P areas II1 and the 2nd P areas II2
It plays a protective role.
Using wet-etching technology, etching removes the second work-function layer 205 and the first work function of the 2nd N areas I2
Layer 204, until exposing the gate dielectric layer 203 of the 2nd N areas I2.
In the present embodiment, the etch liquids of the wet-etching technology have oxidisability.It is advantageous in that：The wet method is carved
Etching technique can not only etch the second work-function layer 205 and the first work-function layer 204 for removing the 2nd N areas I2, and also
Lacking oxygen Passivation Treatment can be carried out to the gate dielectric layer 203 that the 2nd N areas I2 exposes.
Specifically, the wet-etching technology includes main etching technique (main etch) and over etching technique (over
Etch), wherein, subsequent Lacking oxygen Passivation Treatment is carried out using the over etching technique.
The etch liquids that the wet-etching technology uses is SC1 solution, SC2 solution or SPM solution.
Wherein, SC1 solution is ammonium hydroxide and the aqueous solution of hydrogen peroxide；SC2 solution is hydrochloric acid and the aqueous solution of hydrogen peroxide；SPM
Solution is sulfuric acid and the aqueous solution of hydrogen peroxide.
With reference to figure 8, Lacking oxygen Passivation Treatment 206 is carried out to the gate dielectric layer 203 of the 2nd N areas I2, reduces described the
Lacking oxygen content in the gate dielectric layer 203 of two N areas I2.
Defect is easily formed in the gate dielectric layer 203, the defect is included in Lacking oxygen, dangling bonds or non-bonding ion
It is one or more.In the present embodiment, the gate dielectric layer 203 includes aerobic vacancy defect.
Lacking oxygen Passivation Treatment 206 is carried out to the gate dielectric layer 203 of the 2nd N areas I2, advantageously reduces the 2nd N
Lacking oxygen content in the gate dielectric layer 203 of area I2 so that the Lacking oxygen content in the gate dielectric layer 203 of the first N areas I1 is more than
Lacking oxygen content in the gate dielectric layer 203 of 2nd N areas I2.
Since the Lacking oxygen content in the gate dielectric layer 203 of the first N areas I1 is more than the gate dielectric layer of the 2nd N areas I2
Lacking oxygen content in 203 so that grid of the dipole quantity more than the 2nd N areas I2 in the gate dielectric layer 203 of the first N areas I1 are situated between
203 interior dipole quantity of matter layer；Correspondingly, the flat rubber belting electricity between gate structure and substrate 201 that the first N-type device is subsequently formed
Flat-band voltage between gate structure and substrate 201 that pressure is subsequently formed higher than the second N-type device, so that formed first
N-type device threshold voltage is higher than the second N-type device threshold voltage.
In the present embodiment, by extending the etching duration of the over etching technique in aforementioned wet-etching technology, described in progress
Lacking oxygen Passivation Treatment 206 so that the technological operation of the Lacking oxygen Passivation Treatment 206 is simple, without additional processing step.
Specifically, the etching duration of the over etching technique is unsuitable too short, also unsuitable long.If the over etching technique
Etching duration is too short, then it is low to reduce degree for the Lacking oxygen content in the gate dielectric layer 203 of the 2nd N areas I2；If described cross is carved
The etching duration of etching technique is long, then the Lacking oxygen Passivation Treatment 206 can make the gate dielectric layer 203 of the 2nd N areas I2
Into harmful effect.
For this purpose, in the present embodiment, the etching duration of the over etching technique is 10s~2min.
In other embodiments, second work-function layer and the first work function in the 2nd N areas can also be removed in etching
After layer, using the processing solution containing hydrogen peroxide, the Lacking oxygen Passivation Treatment is carried out, the processing solution can be
SC1 solution, SC2 solution or SPM solution.
It should be noted that in the processing solution, content of hydrogen peroxide is unsuitable too low, also unsuitable excessively high.If the mistake
It is too low to aoxidize hydrogen content, then the inefficiency of the Lacking oxygen Passivation Treatment；If the content of hydrogen peroxide is excessively high, the oxygen is empty
Position Passivation Treatment easily causes harmful effect to the gate dielectric layer in the 2nd N areas.Correspondingly, the processing solution temperature is also unsuitable too low
It is and unsuitable excessively high.
For this purpose, when carrying out the Lacking oxygen Passivation Treatment using the processing solution containing hydrogen peroxide, the processing is molten
In liquid, hydrogen peroxide mass concentration is 5%~20%, and processing solution temperature is 20 DEG C~50 DEG C.
After the Lacking oxygen Passivation Treatment 206 is carried out, the mask layer 200 is removed.
With reference to figure 9, etching removes the second work-function layer 205 and the first work-function layer 204 of the first N areas I1, directly
To the gate dielectric layer 203 for exposing the first N areas I1.
In the present embodiment, due to before second work-function layer 205 is formed, remaining positioned at the first N areas I1
On the first work-function layer 204, for this purpose, the second work-function layer 205 that etching removes the first N areas I1 includes：Etching removal
The second work-function layer 205 of the first N areas I1, and also etching removes the first work-function layer 204 of the first N areas I1.
Using wet-etching technology, etching removes the second work-function layer 205 and the first work function of the first N areas I1
Layer 204.Specifically, etching removes the second work-function layer 205 of the first N areas I1 and the technique of the first work-function layer 204
Step includes：On the gate dielectric layer 203 of the 2nd N areas I2 and the first P areas II1 and the 2nd P areas II2 second
Second graph layer is formed in work-function layer 205；Using the second graph layer as mask, etching removes the of the first N areas I1
Two work-function layers 205 and the first work-function layer 204；Remove the second graph layer.
In the present embodiment, the Lacking oxygen Passivation Treatment 206 (with reference to figure 8) is first carried out, rear etching removes the first N areas
The second work-function layer 205 and the first work-function layer 204 of I1, avoids the Lacking oxygen Passivation Treatment to the first N areas I1
Gate dielectric layer 203 impact.
It should also be noted that, in other embodiments, it can also be before the Lacking oxygen Dunhua processing be carried out, etching
Remove second work-function layer and the first work-function layer in the first N areas；Wherein, in the processing step with along with, etching is gone
Except second work-function layer and the first work-function layer in the first N areas and the 2nd N areas；And it is carrying out at the Lacking oxygen passivation
It before reason, further includes, protective layer is formed on the gate dielectric layer in the first N areas.
With reference to figure 10, on the gate dielectric layer 203 of the first N areas I1 and the 2nd N areas I2 and the first P areas II1
With formation third work-function layer 207 in the second work-function layer 205 of the 2nd P areas II2.
Third work-function layer 204 on the first N areas I1 as the corresponding work-function layer of the first N-type device one
Part plays the role of adjusting the first N-type device threshold voltage；Third work-function layer 204 on the 2nd N areas I2 is made
For a part for the corresponding work-function layer of the second N-type device, play the role of adjusting the second N-type device threshold voltage.
The second work-function layer 205 and third work-function layer 207 on the first P areas II1 are used as the first P-type device
Corresponding work-function layer plays the role of adjusting the first P-type device threshold voltage；The first work(on the 2nd P areas II2
Function layer 204, the second work-function layer 205 and third work-function layer 207 are played as the corresponding work-function layer of the second P-type device
Adjust the effect of the second P-type device threshold voltage.
For P-type device, the thickness of work-function layer is thicker, and the P-type device threshold voltage being correspondingly formed is smaller.Due to
The thickness work-function layer corresponding compared with the second P-type device of the corresponding work-function layer of first P-type device it is thinner, therefore
The first P-type device threshold voltage being subsequently formed is more than the second P-type device threshold voltage.
The material of the third work-function layer 207 is p-type work function material；The material of the third work-function layer 207 is
One or more of Ta, TiN, TaN, TaSiN or TiSiN.
In the present embodiment, the material of the third work-function layer 207 is TiN, and the thickness of the third work-function layer 207 is
10 angstroms~30 angstroms.
Using chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process, the third is formed
Work-function layer 207.
Flat-band voltage Vfb and the first N-type device between the gate structure of the first N-type device and substrate 201
Work-function layer thickness it is related, and the flat-band voltage of the first N-type device also in the gate dielectric layer 203 of the first N areas I1
Dipole (dipole) quantity it is related；Flat-band voltage between the gate structure of the second N-type device and the substrate 201
Vfb is related with the thickness of the work-function layer of the second N-type device, and the flat-band voltage of the second N-type device also with the 2nd N
Dipole quantity in the gate dielectric layer 230 of area I2 is related.
Since the aforementioned gate dielectric layer 203 to the 2nd N areas I2 has carried out Lacking oxygen Passivation Treatment 206, the 2nd N areas I2
Gate dielectric layer 203 in Lacking oxygen content less than the first N areas I1 gate dielectric layer 203 in Lacking oxygen content so that the 2nd N
The dipole amount in gate dielectric layer 203 of the dipole compared with the first N areas I1 in the gate dielectric layer 203 of area I2 is few.Therefore, though
The work-function layer thickness of one N-type device is equal with the work-function layer thickness of the second N-type device, the flat rubber belting of the first N-type device
Voltage is more than the flat-band voltage of the second N-type device, so that the first N-type device threshold voltage formed is higher than the second N-type device
Part threshold voltage.
For this purpose, in the present embodiment, before N-type workfunction layer is subsequently formed, positioned at the first N areas I1 and the 2nd N areas
The thickness of work-function layer on I2 is identical, without performing etching the third work-function layer 207 in the first N areas of removal and in the first N
The processing step of the 4th work-function layer is formed in area and the 2nd N areas, so as to simplify the formation process step of semiconductor structure, is made
The work function film layer quantity obtained in semiconductor structure is reduced.
With reference to figure 11, in the third work function of the first N areas I1, the 2nd N areas I2, the first P areas II1 and the 2nd P areas II2
N-type workfunction layer 208, and the material work functions type of the N-type workfunction layer 208 and the third work content are formed on layer 207
Several layers 207 of material work functions type is different；Gate electrode layer (not shown) is formed on the N-type workfunction layer 208.
Third work-function layer 207 and N-type workfunction layer 208 on the first N areas I1 are used as the first N-type device pair
The work-function layer answered plays the role of adjusting the first N-type device threshold voltage；Third work content on the 2nd N areas I2
Several layers 207 work-function layers corresponding with the second N-type device of conduct of N-type workfunction layer 208, play and adjust the second N-type device threshold
The effect of voltage.
For N-type device, since Lacking oxygen content is less than the first N areas I1's in the gate dielectric layer 203 of the 2nd N areas I2
Lacking oxygen content in gate dielectric layer 203, and the thickness and the second N-type device pair of the corresponding work-function layer of the first N-type device
The thickness for the work-function layer answered is equal, therefore the threshold voltage of the second N-type device being subsequently formed is more than the threshold of the first N-type device
Threshold voltage.
It should be noted that in order to reduce processing step, save light shield, in the present embodiment, the N-type work function is being formed
After layer 208, retain the N-type workfunction layer 208 being located on the first P areas II1 and the 2nd P areas II2.
The material of the N-type workfunction layer 208 is N-type work function material, and N-type work function material workfunction range is
3.9eV to 4.5eV, for example, 4eV, 4.1eV or 4.3eV.The material of the N-type workfunction layer 208 for TiAl, TiAlC,
It is one or more in TaAlN, TiAlN, TaCN and AlN, chemical vapor deposition method, physical gas-phase deposition may be used
Or atom layer deposition process forms the N-type workfunction layer 208.
In the present embodiment, the material of the N-type workfunction layer 208 is TiAl, and the thickness of the N-type workfunction layer 208 is
10 angstroms~50 angstroms.
Subsequent processing step further includes：Gate electrode layer is formed on the N-type workfunction layer 208.
In the present embodiment, the gate electrode layer is across the first N areas I1, the first P areas II1, the 2nd P areas II2 and
Two N areas I2, correspondingly, the first N areas I1, the first P areas II1, the 2nd P areas II2 and the 2nd N areas I2 share same grid electricity
Pole layer.In other embodiments, the gate electrode layer positioned at the first N areas, the 2nd N areas, the first P areas and the 2nd P areas may be used also
With mutual indepedent.
The material of the gate electrode layer includes one or more in Al, Cu, Ag, Au, Pt, Ni, Ti or W.
Specifically, the processing step for forming the gate electrode layer includes：Grid electricity is formed on the N-type workfunction layer 208
Pole film, the gate electrode film top top (not shown) higher than the interlayer dielectric layer；Grinding removal is higher than the inter-level dielectric
The gate electrode film at layer top, forms the gate electrode layer.
In the technical solution of the forming method of semiconductor structure provided in an embodiment of the present invention, there are different threshold values being formed
The the first N-type device and the second N-type device of voltage have the first P-type device and the second P-type device of different threshold voltages
Technical process in, Lacking oxygen Passivation Treatment is carried out to the gate dielectric layer 203 of the 2nd N areas I2 so that the gate medium of the first N areas I1
Lacking oxygen content in gate dielectric layer 203 of the Lacking oxygen content more than the 2nd N areas I2, passes through the difference of Lacking oxygen content in floor 203
So that the threshold voltage of the first N-type device and the second N-type device has otherness；Therefore, the third work-function layer of formation both position
The 2nd N areas I2 is also located in the first N areas I1, avoids the technique step of the third work-function layer 207 of the first N areas I1 of etching removal
Suddenly, it and not necessarily forms the 4th work-function layer, so as to simplify processing step, and meets the first N-type device threshold voltage and be less than the
The demand of two N-type device threshold voltages.
Correspondingly, the present invention also provides a kind of semiconductor structure, with reference to figure 11, the semiconductor structure includes：
Substrate, the substrate include the first N areas I1 with the first N-type device, the 2nd N areas with the second N-type device
I2, the first P areas II1 with the first P-type device and the 2nd P areas II2 with the second P-type device, and the first N-type device
The threshold voltage of part is less than the threshold voltage of the second N-type device, and the threshold voltage of first P-type device is more than the 2nd P
The threshold voltage of type device；
Gate medium in the substrate of the first N areas I1, the 2nd N areas I2, the first P areas II1 and the 2nd P areas II2
Layer 203, wherein, Lacking oxygen content is more than the gate dielectric layer of the 2nd N areas I2 in the gate dielectric layer 203 of the first N areas I1
Lacking oxygen content in 203；
The first work-function layer 204 on the gate dielectric layer 203 of the 2nd P areas II2；
On the gate dielectric layer 203 of the first P areas II1 and in the first work-function layer 204 of the 2nd P areas II2
Second work-function layer 205；
On the gate dielectric layer 203 of the first N areas I1 and the 2nd N areas I2 and the first P areas II1 and the 2nd P areas
Third work-function layer 207 in the second work-function layer 205 of II2.
Semiconductor structure provided in an embodiment of the present invention is described in detail below with reference to attached drawing.
Description in relation to the substrate 201 and gate dielectric layer 203 can refer to the respective description of previous embodiment, herein not
It repeats again.In the present embodiment, the semiconductor structure further includes：Between the substrate 201 and the gate dielectric layer 203
Boundary layer 202.
The semiconductor structure further includes：N-type workfunction layer 208 in the third work-function layer 207；Positioned at institute
State the gate electrode layer on N-type workfunction layer 208.
The material of first work-function layer 204 is one or more of Ta, TiN, TaN, TaSiN or TiSiN；It is described
The material of second work-function layer 205 is one or more of Ta, TiN, TaN, TaSiN or TiSiN；The third work-function layer
207 material is one or more of Ta, TiN, TaN, TaSiN or TiSiN；The material of the N-type workfunction layer 208 is
One or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN.
In the present embodiment, the material of first work-function layer 204 is TiN, and the material of second work-function layer 205 is
TiN, the material of the third work-function layer 207 is TiN, and the material of the N-type workfunction layer 208 is TiAl.First work(
The thickness of function layer 204 is 10 angstroms~30 angstroms；The thickness of second work-function layer 205 is 10 angstroms~30 angstroms；The third work(
The thickness of function layer 207 is 10 angstroms~30 angstroms；The thickness of the N-type workfunction layer 208 is 10 angstroms~50 angstroms.
In the present embodiment, since Lacking oxygen content is more than the 2nd N areas I2's in the gate dielectric layer 203 of the first N areas I1
Lacking oxygen content in gate dielectric layer 203, and third work-function layer 207 and N-type workfunction layer 208 are respectively positioned on the first N areas I and
On two N areas I2 so that the work-function layer thickness on the first N areas I1 and the 2nd N areas I2 is identical, and also meets the first N-type device threshold
Threshold voltage is less than the demand of the second N-type device threshold voltage.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, the substrate includes the first N areas for being used to form the first N-type device, be used to form the second N-type device the
Two N areas, the first P areas for being used to form the first P-type device and the 2nd P areas for being used to form the second P-type device, and described first
The threshold voltage of N-type device is less than the threshold voltage of the second N-type device, and the threshold voltage of first P-type device is more than the 2nd P
The threshold voltage of type device；Gate dielectric layer is formed in the substrate in the first N areas, the 2nd N areas, the first P areas and the 2nd P areas
And the first work-function layer on the gate dielectric layer；
First work-function layer is etched, retains the first work function positioned at the 2nd P areas, the first N areas and the 2nd N areas
Layer；
After first work-function layer is etched, formed in the first N areas, the 2nd N areas, the first P areas and the 2nd P areas
Second work-function layer；
Etching removes second work-function layer and the first work-function layer in the 2nd N areas, until exposing the 2nd N areas
Gate dielectric layer；
Lacking oxygen Passivation Treatment is carried out to the gate dielectric layer in the 2nd N areas, reduces the oxygen in the gate dielectric layer in the 2nd N areas
Vacancy content；
Etching removes second work-function layer and the first work-function layer in the first N areas, until exposing the first N areas
Gate dielectric layer；
On the gate dielectric layer in the first N areas and the 2nd N areas and second work-function layer in the first P areas and the 2nd P areas
Upper formation third work-function layer.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that using wet-etching technology, etching
Second work-function layer in the 2nd N areas is removed, until exposing the gate dielectric layer in the 2nd N areas, and the wet etching
The etch liquids of technique have oxidisability.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the wet-etching technology includes master
Etching technics and over etching technique, wherein, carry out the Lacking oxygen Passivation Treatment using the over etching technique.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the wet-etching technology used
Etch liquids are SC1 solution, SC2 solution or SPM solution.
5. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that during the etching of the over etching technique
A length of 10s~2min.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that use the processing containing hydrogen peroxide
Solution carries out the Lacking oxygen Passivation Treatment.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that in the processing solution, peroxidating
Hydrogen mass concentration is 5%~20%, and processing solution temperature is 20 DEG C~50 DEG C.
8. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the processing solution for SC1 solution,
SC2 solution or SPM solution.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that first carry out at the Lacking oxygen passivation
Reason, rear etching remove second work-function layer and the first work-function layer in the first N areas.
10. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the gate dielectric layer is
High-k gate dielectric material.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that formed the gate dielectric layer it
Before, also boundary layer is formed in the substrate in the first N areas, the 2nd N areas, the first P areas and the 2nd P areas.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of first work-function layer
The material of material, the second work-function layer and third work-function layer is p-type work function material.
13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the p-type work function material packet
Include one or more of Ta, TiN, TaN, TaSiN or TiSiN.
14. the forming method of semiconductor structure as described in claim 1, which is characterized in that further include step：Described first
N areas, the 2nd N areas, the first P areas and the 2nd P areas third work-function layer on form N-type workfunction layer, and the N-type workfunction layer
Material work functions type it is different from the material work functions type of the third work-function layer；The shape on the N-type workfunction layer
Into gate electrode layer.
15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that the material of the N-type workfunction layer
Expect for one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN.
16. the forming method of semiconductor structure as described in claim 1, which is characterized in that etching first work-function layer
Processing step include：The first graph layer is formed in first work-function layer in the first N areas, the 2nd N areas and the 2nd P areas；
Using first graph layer as mask, etching removal is positioned at first work-function layer in the first P areas；Remove first figure
Layer.
17. the forming method of semiconductor structure as described in claim 1, which is characterized in that etching removes the first N areas
The processing step of second work-function layer and the first work-function layer includes：It is on the gate dielectric layer in the 2nd N areas and described
Second graph floor is formed in second work-function layer in the first P areas and the 2nd P areas；Using the second graph layer as mask, etching is gone
Except second work-function layer and the first work-function layer in the first N areas；Remove the second graph layer.
18. a kind of semiconductor structure, which is characterized in that including：
Substrate, the substrate include the first N areas with the first N-type device, the 2nd N areas with the second N-type device, with the
First P areas of one P-type device and the 2nd P areas with the second P-type device, and the threshold voltage of the first N-type device is small
In the threshold voltage of the second N-type device, the threshold voltage of first P-type device is more than the threshold voltage of the second P-type device；
Gate dielectric layer in the substrate in the first N areas, the 2nd N areas, the first P areas and the 2nd P areas, wherein, described
Lacking oxygen content is more than Lacking oxygen content in the gate dielectric layer in the 2nd N areas in the gate dielectric layer in one N areas；
The first work-function layer on the gate dielectric layer in the 2nd P areas；
The second work-function layer on the gate dielectric layer in the first P areas and in first work-function layer in the 2nd P areas；
On the gate dielectric layer in the first N areas and the 2nd N areas and second work function in the first P areas and the 2nd P areas
Third work-function layer on layer.
19. semiconductor structure as claimed in claim 18, which is characterized in that material, the second work(of first work-function layer
The material of function layer and the material of third work-function layer are p-type work function material.
20. semiconductor structure as claimed in claim 18, which is characterized in that the semiconductor structure further includes：Positioned at described
N-type workfunction layer in third work-function layer；Gate electrode layer on the N-type workfunction layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611239033.7A CN108258028B (en) | 2016-12-28 | 2016-12-28 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611239033.7A CN108258028B (en) | 2016-12-28 | 2016-12-28 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108258028A true CN108258028A (en) | 2018-07-06 |
| CN108258028B CN108258028B (en) | 2020-06-09 |
Family
ID=62720392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611239033.7A Active CN108258028B (en) | 2016-12-28 | 2016-12-28 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108258028B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111554679A (en) * | 2020-04-09 | 2020-08-18 | 中国科学院微电子研究所 | SOI FinFET device and manufacturing method thereof |
| CN112242299A (en) * | 2019-07-18 | 2021-01-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103594365A (en) * | 2012-08-14 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | A method for forming a PMOS transistor |
| CN104425384A (en) * | 2013-09-10 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN104916589A (en) * | 2014-03-12 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Method for producing semiconductor devices |
| CN105518848A (en) * | 2013-07-18 | 2016-04-20 | 格罗方德半导体股份有限公司 | Fin field effect transistors having multiple threshold voltages |
| US20160225867A1 (en) * | 2015-01-29 | 2016-08-04 | Juyoun Kim | Semiconductor device having work-function metal and method of forming the same |
| US20160365347A1 (en) * | 2015-06-12 | 2016-12-15 | International Business Machines Corporation | ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs |
-
2016
- 2016-12-28 CN CN201611239033.7A patent/CN108258028B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103594365A (en) * | 2012-08-14 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | A method for forming a PMOS transistor |
| CN105518848A (en) * | 2013-07-18 | 2016-04-20 | 格罗方德半导体股份有限公司 | Fin field effect transistors having multiple threshold voltages |
| CN104425384A (en) * | 2013-09-10 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN104916589A (en) * | 2014-03-12 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Method for producing semiconductor devices |
| US20160225867A1 (en) * | 2015-01-29 | 2016-08-04 | Juyoun Kim | Semiconductor device having work-function metal and method of forming the same |
| US20160365347A1 (en) * | 2015-06-12 | 2016-12-15 | International Business Machines Corporation | ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112242299A (en) * | 2019-07-18 | 2021-01-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US11373912B2 (en) * | 2019-07-18 | 2022-06-28 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor structure and method for forming the same |
| CN111554679A (en) * | 2020-04-09 | 2020-08-18 | 中国科学院微电子研究所 | SOI FinFET device and manufacturing method thereof |
| CN111554679B (en) * | 2020-04-09 | 2023-03-31 | 中国科学院微电子研究所 | SOI FinFET device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108258028B (en) | 2020-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10269927B2 (en) | Semiconductor structures and fabrication methods thereof | |
| CN108010884B (en) | Semiconductor structure and forming method thereof | |
| US9786664B2 (en) | Fabricating a dual gate stack of a CMOS structure | |
| CN106952908B (en) | Semiconductor structure and manufacturing method thereof | |
| CN107591437A (en) | The forming method of semiconductor devices | |
| CN106558584A (en) | Semiconductor structure and forming method thereof | |
| CN107346783A (en) | Semiconductor structure and its manufacture method | |
| CN105226023A (en) | The formation method of semiconductor device | |
| KR101347943B1 (en) | Cmos devices with metal gates and methods for forming the same | |
| CN105990114B (en) | The forming method of semiconductor devices | |
| US9941152B2 (en) | Mechanism for forming metal gate structure | |
| US8652917B2 (en) | Superior stability of characteristics of transistors having an early formed high-K metal gate | |
| CN106847874A (en) | The forming method of the semiconductor devices with different threshold voltages | |
| CN106935503A (en) | The forming method of semiconductor devices | |
| CN108258028A (en) | Semiconductor structure and forming method thereof | |
| CN107591363B (en) | Method for forming semiconductor device | |
| CN106876273B (en) | The manufacturing method of semiconductor structure | |
| CN108257918B (en) | Semiconductor structure and forming method thereof | |
| CN106847695A (en) | The forming method of fin field effect pipe | |
| CN106469652A (en) | Semiconductor device and forming method thereof | |
| CN105826256B (en) | Method for forming CMOS transistor | |
| CN108155235A (en) | Semiconductor structure and forming method thereof | |
| CN108389835B (en) | Semiconductor structure and forming method thereof | |
| CN105826260B (en) | The forming method of semiconductor devices | |
| CN107492499A (en) | The forming method of semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |