CN108258028B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN108258028B
CN108258028B CN201611239033.7A CN201611239033A CN108258028B CN 108258028 B CN108258028 B CN 108258028B CN 201611239033 A CN201611239033 A CN 201611239033A CN 108258028 B CN108258028 B CN 108258028B
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region
work function
layer
function layer
gate dielectric
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CN108258028A (en
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贺鑫
林曦
杨晓蕾
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: etching the first work function layer, and reserving the first work function layer positioned in the second P area, the first N area and the second N area; after the first work function layer is etched, forming a second work function layer on the first N area, the second N area, the first P area and the second P area; etching and removing the second work function layer of the second N region until the gate dielectric layer of the second N region is exposed; performing oxygen vacancy passivation treatment on the gate dielectric layer of the second N region to reduce the oxygen vacancy content in the gate dielectric layer of the second N region; etching and removing the second work function layer of the first N region until the gate dielectric layer of the first N region is exposed; and forming third work function layers on the gate dielectric layers of the first N region and the second N region and on the second work function layers of the first P region and the second P region. The invention reduces the complexity of the semiconductor structure forming process and saves the process steps.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
The principal semiconductor devices of integrated circuits, particularly very large scale integrated circuits, are metal-oxide-semiconductor field effect transistors (MOS transistors). With the continuous development of integrated circuit manufacturing technology, the technology node of the semiconductor device is continuously reduced, and the geometric dimension of the semiconductor structure is continuously reduced following moore's law. As the size of semiconductor structures decreases to a certain extent, various secondary effects due to the physical limitations of the semiconductor structures continue to emerge, and scaling down the feature sizes of semiconductor structures becomes increasingly difficult. Among them, in the field of semiconductor fabrication, how to solve the problem of large leakage current of a semiconductor structure is the most challenging. The leakage current of the semiconductor structure is large and is mainly caused by the fact that the thickness of a traditional gate dielectric layer is continuously reduced.
The solution proposed at present is to use a high-k gate dielectric material instead of the conventional silicon dioxide gate dielectric material and use metal as the gate electrode to avoid fermi level pinning effect and boron penetration effect between the high-k material and the conventional gate electrode material. The introduction of the high-k metal gate reduces the leakage current of the semiconductor structure.
Although the introduction of high-k metal gates can improve the electrical performance of semiconductor structures to some extent, the semiconductor structures formed by the prior art are complex in process.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can meet different requirements of the semiconductor structure on threshold voltage and simplify the process steps.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first N region for forming a first N type device, a second N region for forming a second N type device, a first P region for forming a first P type device and a second P region for forming a second P type device, and the threshold voltage of the first N type device is less than the threshold voltage of the second N type device, and the threshold voltage of the first P type device is greater than the threshold voltage of the second P type device; forming a gate dielectric layer and a first work function layer on the gate dielectric layer on the substrate of the first N region, the second N region, the first P region and the second P region; etching the first work function layer, and reserving the first work function layers positioned in the second P area, the first N area and the second N area; after the first work function layer is etched, forming a second work function layer on the first N area, the second N area, the first P area and the second P area; etching to remove the second work function layer and the first work function layer of the second N region until the gate dielectric layer of the second N region is exposed and the gate dielectric layer of the second N region is exposed; performing oxygen vacancy passivation treatment on the gate dielectric layer of the second N region to reduce the oxygen vacancy content in the gate dielectric layer of the second N region; etching to remove the second work function layer and the first work function layer of the first N region until the gate dielectric layer of the first N region is exposed; and forming third work function layers on the gate dielectric layers of the first N region and the second N region and on the second work function layers of the first P region and the second P region.
Optionally, a wet etching process is used to remove the second work function layer in the second N region by etching until the gate dielectric layer in the second N region is exposed, and an etching liquid of the wet etching process has an oxidizing property.
Optionally, the wet etching process includes a main etching process and an over-etching process, wherein the oxygen vacancy passivation process is performed by using the over-etching process.
Optionally, the etching liquid adopted in the wet etching process is an SC1 solution, an SC2 solution, or an SPM solution.
Optionally, the etching time of the over-etching process is 10 s-2 min.
Optionally, the oxygen vacancy passivation treatment is performed using a treatment solution containing hydrogen peroxide.
Optionally, in the treatment solution, the mass concentration of the hydrogen peroxide is 5-20%, and the temperature of the treatment solution is 20-50 ℃.
Optionally, the treatment solution is an SC1 solution, an SC2 solution, or an SPM solution.
Optionally, the oxygen vacancy passivation treatment is performed first, and then the second work function layer and the first work function layer in the first N region are removed by etching.
Optionally, the gate dielectric layer is made of a high-k gate dielectric material.
Optionally, before forming the gate dielectric layer, an interface layer is further formed on the substrate of the first N region, the second N region, the first P region, and the second P region.
Optionally, the material of the first work function layer, the material of the second work function layer, and the material of the third work function layer are all P-type work function materials.
Optionally, the P-type work function material includes one or more of Ta, TiN, TaN, TaSiN, and TiSiN.
Optionally, the method further comprises the steps of: forming an N-type work function layer on a third work function layer of the first N region, the second N region, the first P region and the second P region, wherein the type of a material work function of the N-type work function layer is different from that of the third work function layer; and forming a gate electrode layer on the N-type work function layer.
Optionally, the material of the N-type work function layer is one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN.
Optionally, the process step of etching the first work function layer includes: forming a first graph layer on the first work function layer of the first N area, the second N area and the second P area; etching and removing the first work function layer positioned in the first P area by taking the first graph layer as a mask; and removing the first graphic layer.
Optionally, the step of removing the second work function layer and the first work function layer in the first N region by etching includes: forming a second graph layer on the gate dielectric layer of the second N region and the second work function layers of the first P region and the second P region; etching and removing the second work function layer and the first work function layer in the first N area by taking the second graph layer as a mask; and removing the second graphic layer. The present invention also provides a semiconductor structure comprising: a substrate comprising a first N region having a first N type device, a second N region having a second N type device, a first P region having a first P type device, and a second P region having a second P type device, and the first N type device having a threshold voltage less than the threshold voltage of the second N type device, the first P type device having a threshold voltage greater than the threshold voltage of the second P type device; the gate dielectric layer is positioned on the substrate of the first N region, the second N region, the first P region and the second P region, wherein the content of oxygen vacancies in the gate dielectric layer of the first N region is greater than that of oxygen vacancies in the gate dielectric layer of the second N region; the first work function layer is positioned on the gate dielectric layer of the second P area; a second work function layer located on the gate dielectric layer of the first P region and on the first work function layer of the second P region; and the third work function layer is positioned on the gate dielectric layers of the first N region and the second N region and on the second work function layers of the first P region and the second P region.
Optionally, the material of the first work function layer, the material of the second work function layer, and the material of the third work function layer are all P-type work function materials.
Optionally, the semiconductor structure further includes: an N-type work function layer on the third work function layer; and the gate electrode layer is positioned on the N-type work function layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the method for forming the semiconductor structure provided by the embodiment of the invention, in the process of forming the first N-type device and the second N-type device with different threshold voltages and the first P-type device and the second P-type device with different threshold voltages, the gate dielectric layer of the second N region is subjected to oxygen vacancy passivation treatment, so that the content of oxygen vacancies in the gate dielectric layer of the first N region is greater than that of oxygen vacancies in the gate dielectric layer of the second N region, and the threshold voltages of the first N-type device and the second N-type device are different due to the difference of the content of oxygen vacancies; therefore, the formed third work function layer is located in the first N region and the second N region, the process step of removing the third work function layer in the first N region through etching is avoided, and the fourth work function layer does not need to be formed, so that the process step is simplified, and the requirement that the threshold voltage of the first N-type device is smaller than that of the second N-type device is met. In addition, the number of the formed work function layer films is reduced, so that the formed semiconductor structure is simpler, and the process window for forming the gate electrode layer subsequently is increased.
In an alternative scheme, a second work function layer located in the second N region is removed by etching through a wet etching process, the wet etching process comprises a main etching process and an over-etching process, and the oxygen vacancy passivation treatment is performed through the over-etching process, so that extra process steps are not needed for performing the oxygen vacancy passivation treatment.
Drawings
FIGS. 1-3 are schematic cross-sectional views of steps of a method for forming a semiconductor structure;
fig. 4 to fig. 11 are schematic cross-sectional structures corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As is known in the art, the electrical performance of the semiconductor structure formed by the prior art needs to be improved. The problem of complex formation process of the semiconductor structure is particularly significant when P-type devices with different Threshold voltages (Threshold voltages) and N-type devices with different Threshold voltages are included in the semiconductor structure.
In order to meet the requirement of improving the threshold voltage of the NMOS transistor and the PMOS transistor at the same time, different metal materials are usually used as Work Function (WF) layer materials in the gate structures of the NMOS transistor and the PMOS transistor, the Work Function layer materials in the NMOS transistor may be referred to as N-type Work Function materials, and the Work Function layer materials in the PMOS transistor may be referred to as P-type Work Function materials. The requirements of different threshold voltages of the device are met by adjusting the thickness of the P-type work function layer between the gate dielectric layer and the N-type work function layer.
Fig. 1 to fig. 3 are schematic cross-sectional views corresponding to steps of a semiconductor structure forming method.
Referring to fig. 1, a substrate 11 is provided, where the substrate 11 includes a first N region 101 and a second N region 102, the first N region 101 is used to form a first N-type device, the second N region 102 is used to form a second N-type device, and a threshold voltage of the first N-type device is smaller than a threshold voltage of the second N-type device; forming an interfacial layer 12 on the substrate 11; forming a gate dielectric layer 13 on the interface layer 12; forming a first work function layer 14 and a second work function layer 15 on the first work function layer 14 on the gate dielectric layer 13 of the first N region 101; a third work function layer 16 is formed on the second work function layer 15 of the first N region 101 and on the gate dielectric layer 13 of the second N region 102.
The substrate further comprises a first P region and a second P region, and the threshold voltage of a P type device formed by the first P region is different from the threshold voltage of a P type device formed by the second P region.
Referring to fig. 2, the third work function layer 16, the second work function layer 15 (refer to fig. 1), and the first work function layer 14 on the first N region 101 are removed by etching, and the surface of the gate dielectric layer 13 of the first N region 101 is exposed.
Referring to fig. 3, a fourth work function layer 17 is formed on the gate dielectric layer 13 of the first N region 101 and on the third work function layer 16 of the second N region 102.
The above-mentioned forming method is complex, and in order to meet different requirements of the first N type device, the second N type device, the first P type device and the second P type device for threshold voltage, at least four work function layers need to be formed.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first N region for forming a first N type device, a second N region for forming a second N type device, a first P region for forming a first P type device and a second P region for forming a second P type device, and the threshold voltage of the first N type device is less than the threshold voltage of the second N type device, and the threshold voltage of the first P type device is greater than the threshold voltage of the second P type device; forming a gate dielectric layer and a first work function layer on the gate dielectric layer on the substrate of the first N region, the second N region, the first P region and the second P region; etching the first work function layer, and reserving the first work function layer positioned in the second P area; after the first work function layer is etched, forming a second work function layer on the first N area, the second N area, the first P area and the second P area; etching and removing the second work function layer of the second N region until the gate dielectric layer of the second N region is exposed; performing oxygen vacancy passivation treatment on the gate dielectric layer of the second N region to reduce the oxygen vacancy content in the gate dielectric layer of the second N region; etching and removing the second work function layer of the first N region until the gate dielectric layer of the first N region is exposed; and forming third work function layers on the gate dielectric layers of the first N region and the second N region and on the second work function layers of the first P region and the second P region.
The invention saves the process steps, simplifies the process complexity and ensures that the formed work function layer film has less quantity while forming the first N type device, the second N type device, the first P type device and the second P type device with different threshold voltages.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to fig. 11 are schematic cross-sectional structures corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention.
Referring to fig. 4, a substrate 201 is provided.
The substrate 201 includes a first N region I1 for forming a first N type device, a second N region I2 for forming a second N type device, a first P region II1 for forming a first P type device, and a second P region II2 for forming a second P type device, and the threshold voltage of the first N type device is less than the threshold voltage of the second N type device and the threshold voltage of the first P type device is greater than the threshold voltage of the second P type device.
The first N region I1 is adjacent to the second N region I2, the second N region I2 is adjacent to the first P region II1, and the first P region II1 is adjacent to the second P region II 2.
In this embodiment, taking a formed semiconductor structure as a planar device as an example, the base 201 is a planar substrate; the substrate 201 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 201 can also be a silicon substrate on an insulator or a germanium substrate on an insulator.
In other embodiments, when the formed semiconductor structure is a fin field effect transistor, the base includes a substrate and a fin portion located on the substrate, the base further includes an isolation structure located on the substrate where the fin portion is exposed, the isolation structure covers a portion of a sidewall of the fin portion, and a top of the isolation structure is lower than a top of the fin portion.
In the embodiment, the first N region I1 includes an N-type Ultra-low threshold voltage (ULVT, Ultra-low VT) region and an N-type low threshold voltage (low VT) region; the second N region I2 is an N-type Standard threshold voltage region (Standard VT). In other embodiments, the first N region may further include only one of an N-type low threshold voltage region or an N-type ultra-low threshold voltage region.
In this embodiment, the first P region II1 is a P-type standard threshold voltage region, and the second P region II2 includes a P-type ultra-low threshold voltage region and a P-type low threshold voltage region. In other embodiments, the second P region may further include only one of a P-type ultra-low threshold voltage region or a P-type low threshold voltage region.
In this embodiment, before forming the gate dielectric layer 203, the method further includes: performing first N-type threshold adjustment doping processing on the substrate 201 corresponding to the N-type ultra-low threshold voltage region, and performing second N-type threshold adjustment doping processing on the substrate 201 corresponding to the N-type low threshold voltage region; and performing first P-type threshold adjusting doping treatment on the substrate 201 corresponding to the P-type ultralow threshold voltage region, and performing second P-type threshold adjusting doping treatment on the substrate 201 corresponding to the P-type ultralow threshold voltage region.
Specifically, the doping ions of the first N-type threshold adjustment doping process and the second N-type threshold adjustment doping process are N-type ions, the N-type ions include P, As or Sb, and the doping concentration of the first N-type threshold adjustment doping process is less than the doping concentration of the second N-type threshold adjustment doping process. The doping ions of the first P-type threshold adjustment doping treatment and the second P-type threshold adjustment doping treatment are P-type ions, the P-type ions include B, Ga or In, and the doping concentration of the first P-type threshold adjustment doping treatment is smaller than the doping concentration of the second P-type threshold adjustment doping treatment.
In this embodiment, a gate structure of a semiconductor structure is formed by using a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high-k gate metal last). Before forming the gate dielectric layer 203, the method further comprises:
a dummy gate structure is formed on the substrate 201 of the first N region I1, the second N region I2, the first P region II1 and the second P region II2, wherein the dummy gate structure spans the first N region I1 and the first P region II1 due to the first N region I1 and the first P region II1 being adjacent, and correspondingly, a subsequently formed gate electrode layer spans the first N region I1 and the first P region II 1.
After the pseudo gate structure is formed, forming source-drain doped regions of each device in the substrate 201 on two sides of the pseudo gate structure of each region; after the source-drain doped region is formed, forming an interlayer dielectric layer on the substrate 201 exposed out of the dummy gate structure, wherein the interlayer dielectric layer exposes out of the top of the dummy gate structure; and after the interlayer dielectric layer is formed, removing the pseudo gate structure.
And forming the gate dielectric layer 203 on the first N region I1, the second N region I2, the first P region II1 and the second P region II2 on the part of the substrate 201. In other embodiments, the semiconductor structure may be formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high-k first gate last).
With continued reference to fig. 4, a gate dielectric layer 203 and a first work function layer 204 on the gate dielectric layer 203 are formed on the substrate 201 of the first N region I1, the second N region I2, the first P region II1 and the second P region II 2.
The gate dielectric layer 203 is made of a high-k gate dielectric material, wherein the high-k gate dielectric material is a gate dielectric material with a relative dielectric constant greater than that of silicon oxide.
In this embodiment, the gate dielectric layer 203 is made of HfO2. In other embodiments, the gate dielectric layer may also be made of HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
In order to improve the interface performance between the substrate 201 and the gate dielectric layer 203, before the gate dielectric layer 203 is formed, an interface layer 202 is further formed on the substrate 201, and correspondingly, the gate dielectric layer 203 is located on the surface of the interface layer 202.
The interface layer 202 provides a good interface basis for forming the gate dielectric layer 203, so that the quality of the formed gate dielectric layer 203 is improved, the interface state density between the gate dielectric layer 203 and the substrate 201 is reduced, and adverse effects caused by direct contact between the gate dielectric layer 203 and the substrate 201 are avoided.
In this embodiment, the interface layer 202 is made of silicon oxide. In other embodiments, the material of the interface layer may also be silicon nitride or silicon oxynitride.
The first work function layer 204 is made of a P-type work function material. Specifically, the first work function layer 204 located on the second P region II2 is used as a part of a work function layer corresponding to a second P-type device, and is used for adjusting a threshold voltage of the second P-type device.
The P-type workfunction material workfunction ranges from 5.1eV to 5.5eV, for example, 5.2eV, 5.3eV, or 5.4 eV. The first work function layer 204 is made of one or more of Ta, TiN, TaN, TaSiN, and TiSiN, and the first work function layer 204 may be formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the material of the first work function layer 204 is TiN, and the thickness of the first work function layer 204 is 10 angstroms to 30 angstroms.
Referring to fig. 5, the first work function layer 204 is etched, and the first work function layer 204 located in the second P region II2, the first N region I1, and the second N region I2 is remained.
In this embodiment, etching the first work function layer 204 and reserving the first work function layer 204 in the first P region II2 includes: and etching to remove the first work function layer 204 of the first P region II1, and leaving the first work function layer 204 located in the first N region I1, the second N region II2, and the second P region II 2.
Specifically, the process for etching the first work function layer 204 includes: forming a first patterning layer on the first work function layer 204 of the first N region I1, the second N region I2 and the second P region II 2; etching and removing the first work function layer 204 positioned in the first P region II1 by taking the first pattern layer as a mask; and removing the first graphic layer.
In this embodiment, in the process of etching the first work function layer 204, the first work function layer 204 located in the first N region I1 and the second N region I2 is retained, so as to avoid etching damage to the gate dielectric layer 203 of the first N region I1 and the second N region I2, and reduce damage to the gate dielectric layer 203 of the first N region I1 and the second N region I2 in the process.
Referring to fig. 6, after the first work function layer 204 is etched, a second work function layer 205 is formed on the first N region I1, the second N region I2, the first P region II1, and the second P region II 2.
In this embodiment, the forming the second work function layer 205 includes: the second work function layer 205 is formed on the first work function layer 204 of the first N region I1, the second N region I2 and the second P region II2, and on the gate dielectric layer 203 of the first P region II 1.
The material of the second work function layer 205 is a P-type work function material. The second work function layer 205 located on the first P region II1 is a part of a work function layer corresponding to a first P-type device, and plays a role in adjusting a threshold voltage of the first P-type device; the second work function layer 205 located on the second P region II2 is a part of a work function layer corresponding to a second P-type device, and plays a role in adjusting a threshold voltage of the second P-type device.
The material of the second work function layer 205 is one or more of Ta, TiN, TaN, TaSiN, and TiSiN.
In this embodiment, the material of the second work function layer 205 is TiN, and the thickness of the second work function layer 205 is 10 angstroms to 30 angstroms.
Referring to fig. 7, the second work function layer 205 and the first work function layer 204 of the second N region I2 are removed by etching, and the gate dielectric layer 203 of the second N region I2 is exposed.
In this embodiment, since the first work function layer 204 located in the second N region I2 is reserved before the second work function layer 205 is formed; therefore, the etching to remove the second work function layer 205 of the second N region I2 includes: the second work function layer 205 of the second N region I2 is removed by etching, and the first work function layer 204 of the second N region I2 is also removed by etching.
Before the etching to remove the second work function layer 205 of the second N region I2, the method further includes: a mask layer 200 is formed on the second work function layer 205 of the first N region I1, the first P region II1, and the second P region II 2.
In this embodiment, the mask layer 200 is made of silicon nitride. In other embodiments, the material of the mask layer may also be a photoresist material.
The mask layer 200 serves to protect the second work function layer 205 of the first N region I1, the first P region II1, and the second P region II2 from being etched. In addition, in this embodiment, after the subsequent oxygen vacancy passivation treatment, the mask layer 200 is removed, and the mask layer 200 also plays a role in protecting the first N region I1, the first P region II1, and the second P region II2 during the oxygen vacancy passivation treatment.
And removing the second work function layer 205 and the first work function layer 204 of the second N region I2 by etching by using a wet etching process until the gate dielectric layer 203 of the second N region I2 is exposed.
In this embodiment, the etching liquid of the wet etching process has an oxidizing property. The advantages are that: the wet etching process can not only remove the second work function layer 205 and the first work function layer 204 of the second N region I2 by etching, but also perform oxygen vacancy passivation on the gate dielectric layer 203 exposed by the second N region I2.
Specifically, the wet etching process comprises a main etching process (main etch) and an over etching process (over etch), wherein the over etching process is used for performing subsequent oxygen vacancy passivation treatment.
The etching liquid adopted by the wet etching process is SC1 solution, SC2 solution or SPM solution.
Wherein the SC1 solution is an aqueous solution of ammonia water and hydrogen peroxide; the SC2 solution is the aqueous solution of hydrochloric acid and hydrogen peroxide; the SPM solution is an aqueous solution of sulfuric acid and hydrogen peroxide.
Referring to fig. 8, the gate dielectric layer 203 of the second N region I2 is subjected to an oxygen vacancy passivation process 206 to reduce the oxygen vacancy content in the gate dielectric layer 203 of the second N region I2.
Defects are easily formed in the gate dielectric layer 203, and the defects comprise one or more of oxygen vacancies, dangling bonds or unbound ions. In this embodiment, the gate dielectric layer 203 contains oxygen vacancy defects.
And performing oxygen vacancy passivation 206 on the gate dielectric layer 203 of the second N region I2, which is favorable for reducing the oxygen vacancy content in the gate dielectric layer 203 of the second N region I2, so that the oxygen vacancy content in the gate dielectric layer 203 of the first N region I1 is greater than the oxygen vacancy content in the gate dielectric layer 203 of the second N region I2.
Because the oxygen vacancy content in the gate dielectric layer 203 of the first N region I1 is greater than the oxygen vacancy content in the gate dielectric layer 203 of the second N region I2, the number of dipoles in the gate dielectric layer 203 of the first N region I1 is greater than the number of dipoles in the gate dielectric layer 203 of the second N region I2; accordingly, the flatband voltage between the subsequently formed gate structure of the first N-type device and the substrate 201 is higher than the flatband voltage between the subsequently formed gate structure of the second N-type device and the substrate 201, such that the threshold voltage of the first N-type device is formed higher than the threshold voltage of the second N-type device.
In this embodiment, the oxygen vacancy passivation treatment 206 is performed by prolonging the etching duration of the over-etching process in the wet etching process, so that the process operation of the oxygen vacancy passivation treatment 206 is simple and no additional process step is required.
Specifically, the etching duration of the over-etching process should not be too short, nor too long. If the etching time of the over-etching process is too short, the reduction degree of the oxygen vacancy content in the gate dielectric layer 203 of the second N region I2 is low; if the etching duration of the over-etching process is too long, the oxygen vacancy passivation 206 may have an adverse effect on the gate dielectric layer 203 of the second N region I2.
Therefore, in the embodiment, the etching time of the over-etching process is 10s to 2 min.
In other embodiments, after the second work function layer and the first work function layer of the second N region are removed by etching, the oxygen vacancy passivation treatment may be performed using a treatment solution containing hydrogen peroxide, where the treatment solution may be an SC1 solution, an SC2 solution, or an SPM solution.
It should be noted that the hydrogen peroxide content in the treatment solution should not be too low, nor too high. If the hydrogen peroxide content is too low, the efficiency of the oxygen vacancy passivation treatment is low; if the hydrogen peroxide content is too high, the oxygen vacancy passivation treatment easily causes adverse effects on the gate dielectric layer of the second N region. Accordingly, the temperature of the treatment solution should not be too low and not too high.
Therefore, when the oxygen vacancy passivation treatment is carried out by adopting the treatment solution containing the hydrogen peroxide, the mass concentration of the hydrogen peroxide in the treatment solution is 5-20%, and the temperature of the treatment solution is 20-50 ℃.
After the oxygen vacancy passivation process 206 is performed, the mask layer 200 is removed.
Referring to fig. 9, the second work function layer 205 and the first work function layer 204 of the first N region I1 are removed by etching until the gate dielectric layer 203 of the first N region I1 is exposed.
In this embodiment, since the first work function layer 204 on the first N region I1 is remained before the second work function layer 205 is formed, the etching to remove the second work function layer 205 of the first N region I1 includes: the second work function layer 205 of the first N region I1 is removed by etching, and the first work function layer 204 of the first N region I1 is also removed by etching.
And etching to remove the second work function layer 205 and the first work function layer 204 of the first N region I1 by using a wet etching process. Specifically, the process of removing the second work function layer 205 and the first work function layer 204 of the first N region I1 by etching includes: forming a second pattern layer on the gate dielectric layer 203 of the second N region I2 and on the second work function layer 205 of the first P region II1 and the second P region II 2; etching and removing the second work function layer 205 and the first work function layer 204 of the first N region I1 by using the second pattern layer as a mask; and removing the second graphic layer.
In this embodiment, the oxygen vacancy passivation 206 (refer to fig. 8) is performed first, and then the second work function layer 205 and the first work function layer 204 of the first N region I1 are removed by etching, so as to avoid the oxygen vacancy passivation from affecting the gate dielectric layer 203 of the first N region I1.
It should be further noted that, in other embodiments, the second work function layer and the first work function layer of the first N region may also be removed by etching before the oxygen vacancy passivation treatment is performed; in the same process step, etching and removing the second work function layer and the first work function layer of the first N region and the second N region; and before the oxygen vacancy passivation treatment, forming a protective layer on the gate dielectric layer of the first N region.
Referring to fig. 10, a third work function layer 207 is formed on the gate dielectric layer 203 of the first N region I1 and the second N region I2, and on the second work function layer 205 of the first P region II1 and the second P region II 2.
The third work function layer 204 located on the first N region I1 is used as a part of a work function layer corresponding to the first N-type device, and plays a role in adjusting a threshold voltage of the first N-type device; the third work function layer 204 located on the second N region I2 is used as a part of a work function layer corresponding to the second N-type device, and plays a role in adjusting a threshold voltage of the second N-type device.
The second work function layer 205 and the third work function layer 207 on the first P region II1 are used as corresponding work function layers of a first P-type device, and play a role in adjusting the threshold voltage of the first P-type device; the first work function layer 204, the second work function layer 205, and the third work function layer 207 on the second P region II2 serve as corresponding work function layers of a second P-type device, and play a role in adjusting a threshold voltage of the second P-type device.
For a P-type device, the thicker the work function layer, the lower the threshold voltage of the correspondingly formed P-type device. Because the thickness of the work function layer corresponding to the first P-type device is thinner than that of the work function layer corresponding to the second P-type device, the threshold voltage of the subsequently formed first P-type device is greater than that of the second P-type device.
The third work function layer 207 is made of a P-type work function material; the material of the third work function layer 207 is one or more of Ta, TiN, TaN, TaSiN, or TiSiN.
In this embodiment, the material of the third work function layer 207 is TiN, and the thickness of the third work function layer 207 is 10 angstroms to 30 angstroms.
The third work function layer 207 is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The flatband voltage Vfb between the gate structure of the first N-type device and the substrate 201 is related to the thickness of the work function layer of the first N-type device, and the flatband voltage of the first N-type device is also related to the number of dipoles (dipoles) in the gate dielectric layer 203 of the first N-region I1; the flatband voltage Vfb between the gate structure of the second N-type device and the substrate 201 is related to the thickness of the work function layer of the second N-type device, and the flatband voltage of the second N-type device is also related to the number of dipoles in the gate dielectric layer 203 of the second N-region I2.
Due to the fact that the oxygen vacancy passivation treatment 206 is conducted on the gate dielectric layer 203 of the second N region I2, the content of oxygen vacancies in the gate dielectric layer 203 of the second N region I2 is lower than that of oxygen vacancies in the gate dielectric layer 203 of the first N region I1, and therefore dipoles in the gate dielectric layer 203 of the second N region I2 are smaller than the dipoles in the gate dielectric layer 203 of the first N region I1. Thus, even if the work function layer thickness of the first N type device is equal to the work function layer thickness of the second N type device, the flatband voltage of the first N type device is greater than the flatband voltage of the second N type device, thereby resulting in a first N type device threshold voltage that is higher than the second N type device threshold voltage.
Therefore, in this embodiment, before the N-type work function layer is formed subsequently, the work function layers on the first N region I1 and the second N region I2 have the same thickness, and the process steps of removing the third work function layer 207 of the first N region and forming the fourth work function layer on the first N region and the second N region by etching are not required, so that the process steps of forming the semiconductor structure are simplified, and the number of work function film layers in the semiconductor structure is reduced.
Referring to fig. 11, an N-type work function layer 208 is formed on the third work function layer 207 of the first N region I1, the second N region I2, the first P region II1 and the second P region II2, and a material work function type of the N-type work function layer 208 is different from a material work function type of the third work function layer 207; a gate electrode layer (not shown) is formed on the N-type work function layer 208.
The third work function layer 207 and the N-type work function layer 208 on the first N region I1 are used as work function layers corresponding to the first N-type device, and play a role in adjusting the threshold voltage of the first N-type device; the third work function layer 207 and the N-type work function layer 208 on the second N region I2 serve as corresponding work function layers of a second N-type device, and play a role in adjusting the threshold voltage of the second N-type device.
For an N-type device, since the oxygen vacancy content in the gate dielectric layer 203 of the second N-region I2 is less than the oxygen vacancy content in the gate dielectric layer 203 of the first N-region I1, and the thickness of the work function layer corresponding to the first N-type device is equal to that of the work function layer corresponding to the second N-type device, the threshold voltage of the subsequently formed second N-type device is greater than that of the first N-type device.
It should be noted that, in order to reduce the process steps and save the mask, in the present embodiment, after the N-type work function layer 208 is formed, the N-type work function layer 208 on the first P region II1 and the second P region II2 is remained.
The material of the N-type work function layer 208 is an N-type work function material having a work function in a range of 3.9eV to 4.5eV, such as 4eV, 4.1eV, or 4.3 eV. The N-type work function layer 208 is made of one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN, and the N-type work function layer 208 may be formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the material of the N-type work function layer 208 is TiAl, and the thickness of the N-type work function layer 208 is 10 to 50 angstroms.
The subsequent process steps further comprise: a gate electrode layer is formed on the N-type work function layer 208.
In this embodiment, the gate electrode layer spans the first N region I1, the first P region II1, the second P region II2 and the second N region I2, and accordingly, the first N region I1, the first P region II1, the second P region II2 and the second N region I2 share the same gate electrode layer. In other embodiments, the gate electrode layers in the first N region, the second N region, the first P region and the second P region may be independent of each other.
The material of the gate electrode layer comprises one or more of Al, Cu, Ag, Au, Pt, Ni, Ti or W.
Specifically, the process steps for forming the gate electrode layer include: forming a gate electrode film on the N-type work function layer 208, wherein the top of the gate electrode film is higher than the top of the interlayer dielectric layer (not shown); and grinding and removing the gate electrode film higher than the top of the interlayer dielectric layer to form the gate electrode layer.
In the technical scheme of the method for forming the semiconductor structure provided by the embodiment of the invention, in the process of forming the first N-type device and the second N-type device with different threshold voltages and the first P-type device and the second P-type device with different threshold voltages, the gate dielectric layer 203 of the second N region I2 is subjected to oxygen vacancy passivation treatment, so that the content of oxygen vacancies in the gate dielectric layer 203 of the first N region I1 is greater than the content of oxygen vacancies in the gate dielectric layer 203 of the second N region I2, and the threshold voltages of the first N-type device and the second N-type device are different due to the difference of the content of oxygen vacancies; therefore, the formed third work function layer is located in both the first N region I1 and the second N region I2, so that the process step of removing the third work function layer 207 of the first N region I1 by etching is avoided, and the fourth work function layer is not required to be formed, thereby simplifying the process step and meeting the requirement that the threshold voltage of the first N-type device is less than the threshold voltage of the second N-type device.
Accordingly, the present invention also provides a semiconductor structure, referring to fig. 11, comprising:
a substrate comprising a first N region I1 with a first N type device, a second N region I2 with a second N type device, a first P region II1 with a first P type device, and a second P region II2 with a second P type device, and a threshold voltage of the first N type device is less than a threshold voltage of the second N type device, the threshold voltage of the first P type device is greater than a threshold voltage of the second P type device;
the gate dielectric layer 203 is positioned on the substrate of the first N region I1, the second N region I2, the first P region II1 and the second P region II2, wherein the content of oxygen vacancies in the gate dielectric layer 203 of the first N region I1 is greater than the content of oxygen vacancies in the gate dielectric layer 203 of the second N region I2;
a first work function layer 204 positioned on the gate dielectric layer 203 of the second P region II 2;
a second work function layer 205 on the gate dielectric layer 203 of the first P region II1 and on the first work function layer 204 of the second P region II 2;
and a third work function layer 207 on the gate dielectric layer 203 of the first N region I1 and the second N region I2, and on the second work function layer 205 of the first P region II1 and the second P region II 2.
The semiconductor structure provided by the embodiment of the invention will be described in detail with reference to the accompanying drawings.
For the description of the substrate 201 and the gate dielectric layer 203, reference may be made to the corresponding description of the foregoing embodiments, and further description is omitted here. In this embodiment, the semiconductor structure further includes: and the interface layer 202 is positioned between the substrate 201 and the gate dielectric layer 203.
The semiconductor structure further includes: an N-type work function layer 208 on the third work function layer 207; a gate electrode layer over the N-type work function layer 208.
The first work function layer 204 is made of one or more of Ta, TiN, TaN, TaSiN or TiSiN; the material of the second work function layer 205 is one or more of Ta, TiN, TaN, TaSiN and TiSiN; the third work function layer 207 is made of one or more of Ta, TiN, TaN, TaSiN or TiSiN; the material of the N-type work function layer 208 is one or more of TiAl, TiAl C, TaAlN, TiAlN, TaCN and AlN.
In this embodiment, the first work function layer 204 is made of TiN, the second work function layer 205 is made of TiN, the third work function layer 207 is made of TiN, and the N-type work function layer 208 is made of TiAl. The thickness of the first work function layer 204 is 10-30 angstroms; the thickness of the second work function layer 205 is 10 to 30 angstroms; the thickness of the third work function layer 207 is 10 to 30 angstroms; the thickness of the N-type work function layer 208 is 10 to 50 angstroms.
In this embodiment, because the content of oxygen vacancies in the gate dielectric layer 203 of the first N region I1 is greater than the content of oxygen vacancies in the gate dielectric layer 203 of the second N region I2, and the third work function layer 207 and the N-type work function layer 208 are both located on the first N region I2 and the second N region I2, the thicknesses of the work function layers on the first N region I1 and the second N region I2 are the same, and the requirement that the threshold voltage of the first N-type device is less than the threshold voltage of the second N-type device is also satisfied.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first N region for forming a first N type device, a second N region for forming a second N type device, a first P region for forming a first P type device and a second P region for forming a second P type device, and the threshold voltage of the first N type device is less than the threshold voltage of the second N type device, and the threshold voltage of the first P type device is greater than the threshold voltage of the second P type device; forming a gate dielectric layer and a first work function layer on the gate dielectric layer on the substrate of the first N region, the second N region, the first P region and the second P region;
etching the first work function layer, and reserving the first work function layers positioned in the second P area, the first N area and the second N area;
after the first work function layer is etched, forming a second work function layer on the first N area, the second N area, the first P area and the second P area;
etching to remove the second work function layer and the first work function layer of the second N region until the gate dielectric layer of the second N region is exposed;
performing oxygen vacancy passivation treatment on the gate dielectric layer of the second N region to reduce the oxygen vacancy content in the gate dielectric layer of the second N region;
etching to remove the second work function layer and the first work function layer of the first N region until the gate dielectric layer of the first N region is exposed;
and forming third work function layers on the gate dielectric layers of the first N region and the second N region and on the second work function layers of the first P region and the second P region.
2. The method for forming a semiconductor structure according to claim 1, wherein the second work function layer and the first work function layer in the second N region are removed by etching by using a wet etching process until the gate dielectric layer in the second N region is exposed, and an etching liquid in the wet etching process has an oxidizing property.
3. The method of forming a semiconductor structure of claim 2, wherein the wet etching process comprises a main etching process and an over-etching process, wherein the oxygen vacancy passivation process is performed using the over-etching process.
4. The method for forming a semiconductor structure according to claim 3, wherein the etching liquid used in the wet etching process is a SC1 solution, a SC2 solution, or a SPM solution.
5. The method for forming a semiconductor structure according to claim 3, wherein an etching time of the over-etching process is 10s to 2 min.
6. The method of forming a semiconductor structure of claim 1, wherein said oxygen vacancy passivation treatment is performed using a treatment solution containing hydrogen peroxide.
7. The method of claim 6, wherein the treatment solution has a hydrogen peroxide concentration of 5% to 20% by mass and a treatment solution temperature of 20 ℃ to 50 ℃.
8. The method of claim 6, wherein the treatment solution is a SC1 solution, a SC2 solution, or a SPM solution.
9. The method of claim 1, wherein the oxygen vacancy passivation is performed first, and then the second work function layer and the first work function layer of the first N region are removed by etching.
10. The method of claim 1, wherein the gate dielectric layer is formed of a high-k gate dielectric material.
11. The method of claim 10, further comprising forming an interfacial layer over the substrate of the first N region, the second N region, the first P region, and the second P region prior to forming the gate dielectric layer.
12. The method of claim 1, wherein the first work function layer, the second work function layer, and the third work function layer are all P-type work function materials.
13. The method of forming a semiconductor structure of claim 12, wherein the P-type work function material comprises one or more of Ta, TiN, TaN, TaSiN, or TiSiN.
14. The method of forming a semiconductor structure of claim 1, further comprising the steps of: forming an N-type work function layer on a third work function layer of the first N region, the second N region, the first P region and the second P region, wherein the type of a material work function of the N-type work function layer is different from that of the third work function layer; and forming a gate electrode layer on the N-type work function layer.
15. The method for forming a semiconductor structure according to claim 14, wherein a material of the N-type work function layer is one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN.
16. The method of forming a semiconductor structure of claim 1, wherein the process step of etching the first work function layer comprises: forming a first graph layer on the first work function layer of the first N area, the second N area and the second P area; etching and removing the first work function layer positioned in the first P area by taking the first graph layer as a mask; and removing the first graphic layer.
17. The method for forming a semiconductor structure according to claim 1, wherein the step of removing the second work function layer and the first work function layer of the first N region by etching comprises: forming a second graph layer on the gate dielectric layer of the second N region and the second work function layers of the first P region and the second P region; etching and removing the second work function layer and the first work function layer in the first N area by taking the second graph layer as a mask; and removing the second graphic layer.
18. A semiconductor structure, comprising:
a substrate comprising a first N region having a first N type device, a second N region having a second N type device, a first P region having a first P type device, and a second P region having a second P type device, and the first N type device having a threshold voltage less than the threshold voltage of the second N type device, the first P type device having a threshold voltage greater than the threshold voltage of the second P type device;
the gate dielectric layer is positioned on the substrate of the first N region, the second N region, the first P region and the second P region, wherein the content of oxygen vacancies in the gate dielectric layer of the first N region is greater than that of oxygen vacancies in the gate dielectric layer of the second N region;
the first work function layer is positioned on the gate dielectric layer of the second P area;
a second work function layer located on the gate dielectric layer of the first P region and on the first work function layer of the second P region;
and the third work function layer is positioned on the gate dielectric layers of the first N region and the second N region and on the second work function layers of the first P region and the second P region.
19. The semiconductor structure of claim 18, wherein the material of the first work function layer, the material of the second work function layer, and the material of the third work function layer are all P-type work function materials.
20. The semiconductor structure of claim 18, wherein the semiconductor structure further comprises: an N-type work function layer on the third work function layer; and the gate electrode layer is positioned on the N-type work function layer.
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