CN109309050B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109309050B CN109309050B CN201710622852.8A CN201710622852A CN109309050B CN 109309050 B CN109309050 B CN 109309050B CN 201710622852 A CN201710622852 A CN 201710622852A CN 109309050 B CN109309050 B CN 109309050B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate comprising a first device area and a second device area which are adjacent; forming a functional layer on a substrate; forming an organic mask layer on the functional layer of the first device area; forming a sacrificial layer on at least the side wall of the organic mask layer close to one side of the second device area; taking the organic mask layer and the sacrificial layer as masks, and etching and removing the functional layer of the second device area by adopting a wet etching process; and removing the organic mask layer and the sacrificial layer. According to the invention, the sacrificial layer is formed on the side wall of the organic mask layer at least close to one side of the second device area, and the sacrificial layer can effectively reduce the probability that an etching solution adopted by the wet etching process permeates into the organic mask layer, so that the probability that the etching solution causes etching loss on the functional layer of the first device area through the organic mask layer is reduced, and the performance of the formed semiconductor structure is further improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The principal semiconductor devices of integrated circuits, particularly very large scale integrated circuits, are metal-oxide-semiconductor field effect transistors (MOS transistors). With the continuous development of integrated circuit manufacturing technology, the technology node of the semiconductor device is continuously reduced, and the geometric dimension of the semiconductor device is continuously reduced following moore's law. As semiconductor device dimensions are reduced to a certain extent, various secondary effects due to the physical limitations of semiconductor devices continue to emerge, and scaling down of feature sizes of semiconductor devices becomes increasingly difficult. Among them, in the field of semiconductor manufacturing, how to solve the problem of large leakage current of a semiconductor device is the most challenging. The leakage current of the semiconductor device is large and is mainly caused by the fact that the thickness of a traditional gate dielectric layer is continuously reduced.
The solution proposed at present is to use a high-k gate dielectric material instead of the conventional silicon dioxide gate dielectric material and use metal as the gate electrode to avoid fermi level pinning effect and boron penetration effect between the high-k material and the conventional gate electrode material. The introduction of the high-k metal gate reduces the leakage current of the semiconductor device.
However, in semiconductor structures incorporating high-k metal gates, there are still many issues to be solved, one of which is matching of work function, since work function will directly affect the threshold voltage (Vt) and performance of the device. The work function must be adjusted to be within a suitable operating range of the semiconductor device.
In the prior art, the adjustment of the threshold voltage of the transistor is realized by forming a work function layer in a gate structure of the transistor, but the transistor introduced with the work function layer still has the problem of poor electrical performance, so that the formed semiconductor structure has poor performance.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first device area and a second device area which are adjacent; forming a functional layer on the substrate; forming an organic mask layer on the functional layer of the first device area; forming a sacrificial layer on at least the side wall of the organic mask layer close to one side of the second device area; taking the organic mask layer and the sacrificial layer as masks, and etching and removing the functional layer of the second device area by adopting a wet etching process; and removing the organic mask layer and the sacrificial layer.
Accordingly, the present invention also provides a semiconductor structure comprising: a substrate including a first device region and a second device region adjacent to each other; a functional layer on the substrate; the organic mask layer is positioned on the functional layer of the first device area; and the sacrificial layer is at least positioned on the side wall of the organic mask layer close to one side of the second device area.
Compared with the prior art, the technical scheme of the invention has the following advantages:
after an organic mask layer is formed on a functional layer of a first device area, a sacrificial layer is formed on at least one side wall of the organic mask layer, which is close to one side of a second device area; in the subsequent process of removing the functional layer of the second device area by adopting a wet etching process, the sacrificial side wall can effectively reduce the probability that an etching solution adopted by the wet etching process permeates into the organic mask layer, so that the probability that the etching solution causes etching loss on the functional layer of the first device area through the organic mask layer is reduced, and the performance of the formed semiconductor structure is improved.
In an alternative scheme, the thickness of the organic mask layer is 90nm to 300nm, and compared with the thickness of a commonly adopted organic mask layer, the thickness of the organic mask layer is increased to increase the path length of the etching solution contacting the functional layer of the first device region through the top of the organic mask layer, so that the probability of etching loss of the etching solution on the functional layer of the first device region is reduced.
In an alternative scheme, the functional layer is a P-type work function layer or an N-type work function layer, and by the technical scheme, adverse effects on the threshold voltage and the performance of the device formed in the first device region can be avoided.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure formed by a method;
FIGS. 2 to 12 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
FIG. 13 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As is known in the art, the performance of semiconductor structures is to be improved. The cause of the poor performance is analyzed in conjunction with a method of forming a semiconductor structure. Referring to fig. 1, a schematic structural diagram corresponding to a method for forming a semiconductor structure is shown.
The forming method comprises the following steps: providing a base (not labeled), wherein the base comprises a substrate 10 and a discrete fin part 11 positioned on the substrate 10, and the base comprises a first device area I and a second device area II which are adjacent; forming a high-k gate dielectric layer 13 crossing the fin portion 11, wherein the high-k gate dielectric layer 13 covers part of the top and part of the side wall of the fin portion 11; forming a work function layer 14 on the high-k gate dielectric layer 13; forming an organic mask layer 20 on the work function layer 14 of the first device region I; and etching and removing the work function layer 14 of the second device area II by using the organic mask layer 20 as a mask through a wet etching process.
Taking the formed semiconductor structure as an SRAM (Static Random Access Memory) as an example, when the work function layer 14 is a P-type work function layer material, the first device region I is a PMOS region for forming a Pull-Up (PU, Pull Up) transistor, the second device region II is an NMOS region for forming a Pull-Down (PD, Pull Down) transistor and a transfer Gate (PG, Pass Gate) transistor, and the wet etching process is used to remove the work function layer 14 of the NMOS region to retain the work function layer 14 of the PMOS region; when the work function layer 14 is made of an N-type work function layer material, the first device region I is an NMOS region for forming a pull-down transistor and a transfer gate transistor, the second device region II is a PMOS region for forming a pull-up transistor, and the wet etching process is used for removing the work function layer 14 of the PMOS region to retain the work function layer 14 of the NMOS region.
Since the organic mask layer 20 is made of an organic material, for example, the organic mask layer 20 may be a photoresist layer, and the organic mask layer 20 is made of a porous material, the etching solution easily permeates into the photoresist layer 20 through the sidewall and the top of the photoresist layer 20, so that the etching loss of the work function layer 14 below the photoresist layer 20 is easily caused, and the etching loss of the work function layer 14 (shown by a dashed circle in fig. 1) at a side of the first device region I close to the second device region II is especially severe, so that the performance of the formed semiconductor structure is easily reduced.
In order to solve the technical problem, after an organic mask layer is formed on a functional layer of a first device area, a sacrificial layer is formed at least on the side wall of the organic mask layer close to one side of a second device area, and the sacrificial layer can effectively reduce the probability of an etching solution penetrating into the organic mask layer, so that the probability of etching loss of the etching solution on the functional layer of the first device area through the organic mask layer is reduced, and the performance of a formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate (not labeled) is provided, the substrate including adjacent first and second device regions I and II.
In the present embodiment, the formed semiconductor structure has a fin structure, that is, the formed device is a fin field effect transistor, and therefore, the base includes a substrate 100 and a discrete fin 110 on the substrate 100. In other embodiments, the formed semiconductor structure may also be a planar structure, and accordingly, the base is a planar substrate.
The substrate 100 provides a processing platform for subsequent formation of semiconductor structures, and the fin 110 is used to provide a channel for a finfet to be formed.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
The material of the fin 110 is the same as the material of the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the top dimension of the fin 110 is smaller than the bottom dimension, i.e., the sidewall of the fin 110 is an inclined surface. In other embodiments, the top dimension of the fin may be equal to the bottom dimension, i.e., the sidewalls of the fin are perpendicular to the substrate surface.
In this embodiment, the first device region I is a PMOS region for forming a P-type device, and the second device region II is an NMOS region for forming an N-type device. In other embodiments, the first device region is an NMOS region and the second device region is a PMOS region.
In some embodiments, the subsequently formed semiconductor structure is an SRAM, and thus, the first device region I is used to form pull-up transistors, the second device region II includes a pull-down region 111N used to form pull-down transistors, and a pass-gate region 121N used to form pass-gate transistors, and the pull-down region 111N is adjacent to the first device region I. The pitch of the adjacent fins 110 in the first device region I and the pull-down region 111N is different from the pitch of the adjacent fins 110 in the second device region II, and in order to avoid an etching Loading Effect (Loading Effect) in a process of forming the fins 110 by etching, the fins 110 are formed by a Cut Last process.
Specifically, after forming the fins 110 with equal spacing, the fins 110 at the junctions of the first device region I and the second device region II are etched, and the dummy fins 115 are formed at the junctions of the first device region I and the second device region II, so that the spacing between the adjacent fins 110 in the first device region I and the second device region II is increased, and the fins 115 have a small height and are covered by the subsequently formed isolation structure, thereby having little or no influence on the device performance.
In this embodiment, after the substrate 100 and the fin portion 110 are formed, the method further includes: an isolation structure 101 is formed on the substrate 100 (as shown in fig. 1), wherein the isolation structure 101 covers a portion of the sidewall of the fin 110, and the top of the isolation structure 101 is lower than the top of the fin 110.
The isolation structure 101 serves as an isolation structure of a semiconductor device and is used for isolating adjacent devices or adjacent fins 110. In this embodiment, the isolation structure 101 covers the dummy fins 115, so as to prevent the dummy fins 115 from being used for forming devices.
In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the isolation structure may also be made of other insulating materials such as silicon nitride or silicon oxynitride.
Referring to fig. 3, in this embodiment, a metal gate structure of a semiconductor structure is formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high-k metal gate last), so that after the isolation structure 101 is formed, the method further includes the steps of: a dummy gate structure (not shown) is formed across the fin 110, covering a portion of the top and a portion of the sidewall surface of the fin 110.
The dummy gate structure is used for occupying a space position for the formation of a subsequent metal gate structure.
In this embodiment, the dummy gate structure is a stacked structure, and includes a dummy oxide layer 121 and a dummy gate 122 located on the dummy oxide layer 121. In other embodiments, the dummy gate structure may also be a single-layer structure, and accordingly, the dummy gate structure only includes a dummy gate layer.
In this embodiment, the material of the dummy oxide layer 121 is silicon oxide. In other embodiments, the material of the dummy oxide layer may also be silicon oxynitride.
In this embodiment, the material of the dummy gate layer 122 is polysilicon. In other embodiments, the material of the dummy gate layer may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, amorphous carbon, or other materials.
In this embodiment, the dummy gate layer 122 spans the first device region I and the second device region II according to actual process requirements. In other embodiments, the dummy gate layers of the first device region I and the second device region II may be separated from each other.
It should be noted that, after the pseudo gate structure is formed, the method further includes the steps of: forming source-drain doped regions (not shown) in the fin portions 110 on two sides of the dummy gate structure; after the source-drain doped region is formed, an interlayer dielectric layer (not shown) is formed on the substrate 100, and the interlayer dielectric layer exposes the top of the dummy gate structure.
In this embodiment, the first device region I is configured to form a P-type device, and the second device region II is configured to form an N-type device, so that the doped ions of the source-drain doped region of the first device region I are P-type ions, the P-type ions include one or more of B, Ga and In, the doped ions of the source-drain doped region of the second device region II are N-type ions, and the N-type ions include one or more of P, As and Sb. .
The interlayer dielectric layer is used for realizing electric isolation between adjacent semiconductor structures.
The interlayer dielectric layer is made of an insulating material. In this embodiment, the interlayer dielectric layer is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.
Specifically, the step of forming the interlayer dielectric layer includes: forming an interlayer dielectric film on the substrate 100, wherein the interlayer dielectric film also covers the top of the pseudo gate structure; and grinding to remove the interlayer dielectric film higher than the top of the pseudo gate structure, exposing the top of the pseudo gate structure, and taking the residual interlayer dielectric film as the interlayer dielectric layer.
In this embodiment, after the interlayer dielectric layer is formed, the top of the interlayer dielectric layer is flush with the top of the dummy gate structure.
Therefore, referring to fig. 4 in combination, the dummy gate structure (not shown) is removed, and a gate opening (not shown) is formed in the interlayer dielectric layer (not shown).
In this embodiment, the dummy gate layer 122 (shown in fig. 3) and the dummy oxide layer 121 (shown in fig. 3) are sequentially removed, and the gate opening provides a spatial location for a metal gate structure to be formed subsequently. In other embodiments, according to actual process requirements, only the dummy gate layer may be removed, and the dummy oxide layer may be remained.
Referring to fig. 5 and 6 in combination, a functional layer (not labeled) is formed on the substrate (not labeled).
The functional layer is used as part of the formed semiconductor structure to adjust the electrical parameters of the formed device.
In this embodiment, the functional Layer is defined as a first functional Layer 230 (as shown in fig. 6), the first functional Layer 230 is a Work Function Layer (Work Function Layer), and the first functional Layer 230 is used to adjust a threshold voltage of a formed device. Therefore, the material of the first functional layer 230 may be one or more of Ta, TiN, TaN, TaSiN, TiSiN, TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN.
Specifically, the first device region I is a PMOS region, and the second device region II is an NMOS region, so that the first functional layer 230 is a P-type work function layer, and the first functional layer 230 is used for adjusting the threshold voltage of the formed pull-up transistor. In other embodiments, for example, when the first device region is an NMOS region and the second device region is a PMOS region, the first functional layer is an N-type work function layer. In this embodiment, the first functional layer 230 is made of TiN.
The thickness of the first functional layer 230 depends on the threshold voltage of the device to be formed and the material of the first functional layer 230. In this embodiment, the thickness of the first functional layer 230 is
To
It should be noted that, as shown in fig. 5, before forming the first functional layer 230 on the substrate (not labeled), the method further includes the steps of: a gate dielectric layer (not labeled) is formed across the fin 110, and the gate dielectric layer covers part of the top and part of the sidewall of the fin 110.
The gate dielectric layer is used for realizing the electric isolation between the metal gate structure formed subsequently and the channel in the substrate.
In this embodiment, the gate dielectric Layer includes an Interfacial Layer (IL) 210 and a high-k gate dielectric Layer 220 located on the surface of the Interfacial Layer 210; accordingly, the first functional layer 230 is formed on the high-k gate dielectric layer 220.
The interfacial layer 210 provides a good interface basis for forming the high-k gate dielectric layer 220, thereby improving the quality of the high-k gate dielectric layer 220, reducing the interface state density between the high-k gate dielectric layer 220 and the fin portion 110, and avoiding adverse effects caused by direct contact between the high-k gate dielectric layer 220 and the fin portion 110. The interface layer 210 is made of silicon oxide or silicon oxynitride.
In this embodiment, the interfacial layer 210 is formed by an oxidation process, so that the interfacial layer 210 is only formed on the top surface and the sidewall surface of the fin 110 exposed by the gate opening (not shown). In other embodiments, the interfacial layer may also be formed by a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, and accordingly, the interfacial layer is also formed on the isolation structure exposed by the gate opening.
The high-k gate dielectric layer 220 is made of a gate dielectric material with a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer 220 is HfO2. In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
The process for forming the high-k gate dielectric layer 220 may be a chemical vapor deposition, physical vapor deposition, or atomic layer deposition process. In this embodiment, the high-k gate dielectric layer 220 is formed by an atomic layer deposition process, so that the high-k gate dielectric layer 220 has good step coverage. Therefore, the high-k gate dielectric layer 220 is also formed on the isolation structure 101 exposed by the gate opening.
It should be further noted that, after the high-k gate dielectric layer 220 is formed, before the first functional layer 230 is formed, the method further includes the steps of: a capping layer (not shown) is formed on the high-k gate dielectric layer 220.
The cap layer can play a role in protecting the high-k gate dielectric layer 220, so as to prevent unnecessary etching loss of the high-k gate dielectric layer 220 caused by a subsequent etching process, and is also beneficial to preventing metal ions in the first functional layer 230 or a functional layer formed subsequently from diffusing into the high-k gate dielectric layer 220, and in addition, the cap layer can also prevent oxygen ions in the high-k gate dielectric layer 220 from diffusing into the first functional layer 230 or a functional layer formed subsequently, so that the problem of increasing the content of oxygen vacancies in the high-k gate dielectric layer 220 is avoided.
In this embodiment, the capping layer is made of TiN. In other embodiments, the material of the cap layer may also be TiSiN or TaSiN.
Referring to fig. 7, an organic mask layer 300 is formed on the first functional layer 230 of the first device region I.
The organic mask layer 300 is used as an etching mask for subsequently etching the first functional layer 230.
In this embodiment, the organic mask layer 300 is a photoresist layer (PR), and the organic mask layer 300 is formed on the first functional layer 230 in the first device region I through an exposure and development process. In other embodiments, the Organic mask Layer may also be an Organic Dielectric Layer (ODL), a Bottom Anti-Reflective Coating (BARC), or a Deep ultraviolet absorption Layer (DUO).
When the organic mask layer is an organic dielectric layer, a bottom anti-reflection coating or a deep ultraviolet light absorption layer, the step of forming the organic mask layer comprises the following steps: forming an organic mask material layer on the first functional layer; forming a photoresist layer on the organic mask material layer of the first device region through an exposure and development process; and etching and removing the organic mask material layer in the second device area by taking the photoresist layer as a mask, and reserving the organic mask material layer in the first device area as the organic mask layer. Correspondingly, the laminated structure of the photoresist layer and the organic mask layer is used as an etching mask subsequently.
It should be noted that the material of the organic mask layer 300 is an organic material, so that the organic mask layer 300 is a porous material, when the wet etching process is subsequently adopted to etch and remove the first functional layer 230 of the second device region II, an etching solution is likely to permeate into the organic mask layer 300 through the top of the organic mask layer 300, and in a severe case, the etching solution permeates through the organic mask layer 300 and contacts the first functional layer 230 of the first device region I, so as to cause etching loss to the first functional layer 230 of the first device region I, thereby easily causing performance degradation of the formed semiconductor structure.
For this reason, in this embodiment, compared with the thickness of the commonly used photoresist layer, the thickness of the organic mask layer 300 is appropriately increased to increase the path length of the etching solution contacting the first functional layer 230 of the first device region I through the top of the photoresist layer 300, so as to reduce the probability that the etching solution causes etching loss on the first functional layer 230 of the first device region I.
The larger the thickness of the organic mask layer 300 is, the better the effect of preventing the first functional layer 230 in the first device region I from being subjected to etching loss is, but the thickness of the organic mask layer 300 is not suitable to be too large, otherwise, in the process of forming the organic mask layer 300, the problem that the organic mask layer 300 is easy to collapse (for example, PR Peeling) occurs, and the process risk and the process difficulty are high; moreover, under the condition of better effect of preventing the first functional layer 230 in the first device region I from being etched, the thickness of the organic mask layer 300 is too large, which may also cause waste of process cost. Therefore, in this embodiment, the thickness of the organic mask layer 300 is set to be 90nm to 300nm while reducing the probability of the first device region I, i.e., the first functional layer 230, being subjected to the etching loss and avoiding the generation of side effects.
Referring to fig. 8, a sacrificial layer 310 is formed on at least a sidewall of the organic mask layer 300 near the second device region II.
When the first functional layer 230 of the second device region II is removed by etching using a wet etching process, an etching solution easily permeates into the organic mask layer 300 through the sidewall of the organic mask layer 300, so that etching loss is easily caused to the first functional layer 230 of the first device region I, especially to the first functional layer 230 on the side of the first device region I close to the second device region II; the sacrificial layer 310 is used for protecting the side wall of the organic mask layer 300, and effectively reduces the probability that the etching solution penetrates into the organic mask layer 300 through the side wall of the organic mask layer 300, so that the probability that the etching solution causes etching loss to the first functional layer 230 of the first device region I is reduced, and the performance of the formed semiconductor structure is improved.
Therefore, the material of the sacrificial layer 310 is selected as follows: the density of the sacrificial layer 310 is greater than that of the organic mask layer 300, and the etching rate of the wet etching process to the sacrificial layer 310 is less than that to the first functional layer 230, so that after the first functional layer 230 in the second device region II is removed by etching, the sacrificial layer 310 is still kept, and the problem that the etching solution penetrates into the sacrificial layer 310 and then penetrates into the organic mask layer 300 from the sacrificial layer 310 can be avoided; in addition, the sacrificial layer 310 is required to be removed subsequently, so that the etching process adopted for removing the sacrificial layer 310 has less etching loss on the first functional layer 230 and the high-k gate dielectric layer 220.
In this embodiment, the material of the sacrificial layer 310 is silicon oxide. In other embodiments, the material of the sacrificial layer may also be amorphous silicon, amorphous carbon, or silicon nitride.
In this embodiment, the ratio of the etching rate of the wet etching process to the etching rate of the sacrificial layer 310 and the first functional layer 230 is less than 1: 1. Therefore, after the first functional layer 230 in the second device region II is removed by subsequent etching, it can be ensured that the sacrificial layer 310 still remains on the sidewall of the organic mask layer 300.
It should be noted that the thickness of the sacrificial layer 310 is not too small, nor too large. If the thickness of the sacrificial layer 310 is too small, it is difficult to protect the sidewall of the organic mask layer 300, and it is easy to cause a problem that the sacrificial layer 310 is completely removed before the etching of the first functional layer 230 of the first device region I is not completed, thereby easily causing the etching loss of the first functional layer 230 of the first device region I; if the thickness of the sacrificial layer 310 is too large, the sacrificial layer 310 may easily cover the first functional layer 230 of the second device region II too much, so that the first functional layer 230 of the second device region II remains too much after the subsequent wet etching process, and thus the electrical performance of the formed pull-down transistor and the pass-gate transistor is easily affected, and accordingly the performance of the formed semiconductor structure is reduced.
For this reason, in the present embodiment, the thickness of the sacrificial layer 310 is 2nm to 10 nm. That is, the sacrificial layer 310 has a size of 2nm to 10nm in a direction perpendicular to the sidewalls of the organic mask layer 300.
In this embodiment, in order to improve the thickness uniformity of the sacrificial Layer 310 and the coverage effect on the sidewall of the photoresist Layer 300, the process for forming the sacrificial Layer 310 is an Atomic Layer Deposition (ALD) process. In other embodiments, the process of forming the sacrificial layer may also be a Low Temperature Oxidation (LTO) or a Plasma Enhanced Chemical Vapor Deposition (PECVD).
Specifically, the step of forming the sacrificial layer 310 includes: forming a sacrificial film conformally covering the organic mask layer 300 and the first functional layer 230; and etching to remove the top of the organic mask layer 300 and the sacrificial film on the first functional layer 230, and reserving the sacrificial film on the side wall of the organic mask layer 300 as the sacrificial side wall 310.
In this embodiment, a maskless etching process is used to etch and remove the top of the organic mask layer 300 and the sacrificial film on the first functional layer 230. Because the top dimension of the fin 110 may be smaller than the bottom dimension, that is, the sidewall of the fin 110 is an inclined surface, the sacrificial film on the sidewall of the photoresist layer 300 can be retained while the sacrificial film on the sidewall of the fin 110 is removed by using the scheme of the maskless etching process; moreover, by adopting the scheme of the maskless etching process, the use of a newly added Mask (Mask) can be avoided, so that the increase of the process cost is avoided.
Specifically, the maskless etching process is a dry etching process. The sacrificial side wall 310 is made of silicon oxide, and the sacrificial film is made of silicon oxide, so that the dry etching process adopts fluorine-containing gas to etch the sacrificial film. The specific parameters of the dry etching process are determined according to the thickness of the sacrificial sidewall 310.
In other embodiments, the sacrificial layer also covers a top portion of the organic mask layer.
Therefore, the sacrificial layer not only protects the side wall of the organic mask layer, but also protects the top of the organic mask layer, so that the probability that the etching solution penetrates into the organic mask layer through the top of the organic mask layer is reduced, and the probability that the etching solution causes etching loss on the first function layer of the first device area can be further reduced.
Accordingly, the step of forming the sacrificial layer includes: forming a sacrificial film covering the organic mask layer and the first functional layer by adopting an atomic layer deposition process, a low-temperature oxidation process or a plasma enhanced chemical vapor deposition process; forming a pattern layer on the sacrificial film on the top of the organic mask layer, wherein the projections of the sacrificial film on the top and the side wall of the organic mask layer on the substrate are overlapped with the projection of the pattern layer on the substrate; etching the sacrificial film by taking the graphic layer as a mask, and reserving the sacrificial film positioned at the top and the side wall of the organic mask layer as the sacrificial layer; and removing the graph layer.
Referring to fig. 9, the organic mask layer 300 and the sacrificial layer 310 are used as masks, and the first functional layer 230 in the second device region II is removed by etching through a wet etching process.
A wet etching process is used to etch the first functional layer 230, so as to prevent the high-k gate dielectric layer 220 from being damaged by Plasma (Plasma Damage), and further avoid the performance of the formed semiconductor structure from being adversely affected.
In this embodiment, the first functional layer 230 is made of TiN, and correspondingly, the etching solution used in the wet etching process is NH4OH、H2O2Mixed solution with water (i.e. SC1 solution), or NH4、H2O2And water, or HCl、H2O2And water (i.e., SC2 solution).
Under the protection of the sacrificial layer 310, the first device region I and the first functional layer 230 have a low etching loss probability, and thus, the performance of the formed semiconductor structure is improved. Specifically, the first functional layer 230 is a work function layer, so that the threshold voltage and performance of the device formed in the first device region I can be prevented from being adversely affected.
Referring to fig. 10, the organic mask layer 300 (shown in fig. 9) and the sacrificial layer 310 (shown in fig. 9) are removed.
By removing the organic mask layer 300 and the sacrificial layer 310, the remaining first functional layer 230 is exposed, thereby providing a process base for subsequent processes.
In this embodiment, the sacrificial layer 310 is removed first, and then the organic mask layer 300 is removed. In other embodiments, the organic mask layer may be removed first, and then the sacrificial layer may be removed.
By removing the sacrificial layer 310 first, the risk of collapse of the sacrificial layer 310 due to loss of support can be reduced.
In this embodiment, the organic mask layer 300 is removed by ashing or wet stripping.
In this embodiment, the sacrificial layer 310 is removed by a wet etching process. The sacrificial layer 310 is made of silicon oxide, and the etching solution adopted by the wet etching process is a diluted hydrofluoric acid (DHF) solution. Wherein, the specific parameters of the wet etching process are determined according to the thickness of the sacrificial layer 310.
In other embodiments, when the sacrificial layer is made of amorphous silicon, a wet etching process is used to remove the sacrificial layer, and an etching solution used in the wet etching process is a tetramethylammonium hydroxide (TMAH) solution; when the material of the sacrificial layer is amorphous carbon, ozone or N is adopted2And H2The mixed gas of (2) and performing dry etching on the sacrificial layer; when the sacrificial layer is made of silicon nitride, removing by wet etching processThe etching solution adopted by the wet etching process of the sacrificial layer is phosphoric acid solution correspondingly.
Referring to fig. 11 and 12 in combination, after removing the organic mask layer 300 (shown in fig. 9) and the sacrificial layer 310 (shown in fig. 9), the method further includes the steps of: forming a second functional layer 240 (as shown in fig. 11) covering the second device region II, where the second functional layer 240 is an N-type work function layer; a gate electrode layer 250 is formed on the first functional layer 230 and the second functional layer 240 (as shown in fig. 12).
In this embodiment, the second functional layer 240 is used to adjust the threshold voltages of the pull-down transistors and the pass-gate transistors formed.
Therefore, the material of the second functional layer 240 may be one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN. In this embodiment, the material of the second functional layer 240 is TiAl.
In this embodiment, in the step of forming the second functional layer 240, the second functional layer 240 further covers the first functional layer 230, and the second functional layer 240 on the first functional layer 230 is remained.
Since the second functional layer 240 has little influence on the threshold voltage of the pull-up transistor, by retaining the second functional layer 240 on the first functional layer 230, the use of a photomask can be reduced after the second functional layer 240 is formed, and the process steps and the process cost can be reduced. Accordingly, the gate electrode layer 250 is formed on the second functional layer 240.
Specifically, the step of forming the gate electrode layer 250 includes: filling a conductive material into the gate opening in the interlayer dielectric layer, wherein the conductive material also covers the top of the interlayer dielectric layer; and grinding to remove the conductive material higher than the top of the interlayer dielectric layer, and keeping the conductive material in the gate opening as the gate electrode layer 250.
In this embodiment, the material of the gate electrode layer 250 is W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.
In this embodiment, the gate dielectric layer (not labeled), the first functional layer 230, the second functional layer 240 and the gate electrode layer 250 of the first device region I are used to form a metal gate structure of the first device region I, and the gate dielectric layer, the second functional layer 240 and the gate electrode layer 250 of the second device region II are used to form a metal gate structure of the second device region II.
It should be noted that, in this embodiment, the first device region I is taken as a PMOS region, and the second device region II is taken as an NMOS region for example. In other embodiments, when the first device region is an NMOS region and the second device region is a PMOS region, the second functional layer is correspondingly a P-type work function layer.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown. The semiconductor structure includes:
a substrate (not labeled) including a first device region I and a second device region II adjacent to each other; a functional layer 530 on the substrate; an organic mask layer 600 on the functional layer 530 of the first device region I; and the sacrificial layer 610 is at least positioned on the side wall of the organic mask layer 600 close to one side of the second device area II.
In the present embodiment, the semiconductor structure has a fin structure, that is, the semiconductor device is a fin field effect transistor, and therefore the substrate includes a substrate 400 and a discrete fin 410 located on the substrate 400. In other embodiments, the semiconductor structure may also be a planar structure, and correspondingly, the base is a planar substrate.
In this embodiment, the top dimension of the fin 410 may be smaller than the bottom dimension, i.e., the sidewall of the fin 410 is a slope. In other embodiments, the top dimension of the fin may be equal to the bottom dimension, i.e., the sidewalls of the fin are perpendicular to the substrate surface.
In this embodiment, the first device region I is a PMOS region, and the second device region II is an NMOS region. In other embodiments, the first device region is an NMOS region and the second device region is a PMOS region.
In some embodiments, the substrate is used to form an SRAM, and thus, the first device region I is used to form pull-up transistors, the second device region II includes a pull-down region 111N used to form pull-down transistors, and a pass-gate region 121N used to form pass-gate transistors, and the pull-down region 111N is adjacent to the first device region I.
It should be noted that the substrate 400 at the boundary between the first device region I and the second device region II further has a dummy fin portion 415 thereon. The dummy fin portion 415 is formed by forming the fin portions 410 with equal spacing first and then etching the fin portions 410 at the junction of the first device region I and the second device region II, so that the etching load effect can be avoided in the process of forming the fin portions 410 by etching in a mode of increasing the spacing between the adjacent fin portions 410 of the first device region I and the second device region II.
For a detailed description of the substrate, please refer to the corresponding description in the foregoing embodiments, which is not repeated herein.
In addition, the semiconductor structure further includes: and the isolation structures 401 are positioned on the substrate 400, the isolation structures 401 cover part of the side walls of the fin portion 410, and the tops of the isolation structures 401 are lower than the tops of the fin portion 410.
The isolation structure 401 serves as an isolation structure of a semiconductor device and is used for isolating adjacent devices or adjacent fins 410. In this embodiment, the isolation structure 401 is made of silicon oxide.
In this embodiment, the isolation structure 401 covers the dummy fin 415, so as to prevent the dummy fin 415 from being used for forming a device.
The functional layer 530 is used as part of the semiconductor structure to adjust the electrical parameters of the device being formed.
In this embodiment, the functional layer 530 is a work function layer, and is used to adjust the threshold voltage of the formed device. Therefore, the material of the functional layer 530 may be one or more of Ta, TiN, TaN, TaSiN, TiSiN, TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN.
Specifically, the first device region I is a PMOS region, and the second device region II is an NMOS region, so that the functional layer 530 is a P-type work function layer, and the functional layer 530 is used for adjusting the threshold voltage of the formed pull-up transistor. In other embodiments, for example, when the first device region is an NMOS region and the second device region is a PMOS region, the functional layer is an N-type work function layer. In this embodiment, the functional layer 530 is made of TiN.
The thickness of the functional layer 530 depends on the threshold voltage of the formed device and the material of the functional layer 530. In this embodiment, the functional layer 530 has a thickness of
To
In addition, the semiconductor structure further includes: a gate dielectric layer (not labeled) between the functional layer 530 and the substrate, the gate dielectric layer crossing the fin 410 and covering a portion of the top and a portion of the sidewall surface of the fin 410.
The gate dielectric layer is used for realizing the electric isolation between the metal gate structure of the semiconductor structure and the channel in the substrate. In this embodiment, the gate dielectric layer includes an interface layer 510 and a high-k gate dielectric layer 520 located on the surface of the interface layer 510; the interface layer 510 covers part of the top and part of the sidewall surface of the fin 410, and the high-k gate dielectric layer 520 is located between the functional layer 530 and the interface layer 510 and is also located between the functional layer 530 and the isolation structure 401.
In this embodiment, the interface layer 510 is made of silicon oxide or silicon oxynitride, and the high-k gate dielectric layer 520 is made of HfO2. In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
A capping layer (not shown) is also provided between the high-k gate dielectric layer 520 and the functional layer 230. The cap layer is used for protecting the high-k gate dielectric layer 220; in addition, the method is also used for preventing oxygen ions in the high-k gate dielectric layer 220 from diffusing into the first functional layer 230 or other functional layers, so as to avoid the problem of increasing the oxygen vacancy content of the high-k gate dielectric layer 220.
In this embodiment, the capping layer is made of TiN. In other embodiments, the material of the cap layer may also be TiSiN or TaSiN.
For a detailed description of the gate dielectric layer and the cap layer, please refer to the corresponding description in the foregoing embodiments, which is not repeated herein.
The organic mask layer 600 is used as an etching mask for etching the functional layer 530.
In this embodiment, the organic mask layer 300 is a photoresist layer. In other embodiments, the organic mask layer may also be an organic dielectric layer, a bottom anti-reflection coating layer, or a deep ultraviolet light absorption layer.
The organic mask layer 600 is made of an organic material, so that the organic mask layer 600 is a porous material, when the functional layer 530 of the second device region II is removed by etching through a wet etching process, an etching solution easily permeates into the organic mask layer 600 through the top of the organic mask layer 600, and under a severe condition, the etching solution permeates into the organic mask layer 600 and contacts the functional layer 530 of the first device region I, so that etching loss is caused to the functional layer 530 of the first device region I, and performance of a formed semiconductor structure is easily reduced.
Therefore, in this embodiment, compared with the thickness of the commonly used organic mask layer, the thickness of the organic mask layer 600 is appropriately increased to increase the path length of the etching solution contacting the functional layer 530 in the first device region I through the top of the organic mask layer 600, so as to reduce the probability of the etching loss of the etching solution to the functional layer 530 in the first device region I.
The larger the thickness of the organic mask layer 600 is, the better the effect of preventing the functional layer 530 of the first device region I from being subjected to the etching loss is, but the thickness of the organic mask layer 600 is not too large, otherwise, in the process of forming the organic mask layer 600, the problem that the organic mask layer 600 is easily collapsed (such as PR Peeling) is caused, the process risk and the process difficulty are high, and the waste of the process cost is caused under the condition that the effect of preventing the functional layer 530 of the first device region I from being subjected to the etching loss is good. Therefore, in this embodiment, while the functional layer 530 in the first device region I is prevented from being etched and lost, and side effects are avoided, the thickness of the organic mask layer 600 is set to be 90nm to 300 nm.
The etching solution is also easy to permeate into the organic mask layer 600 through the sidewall of the organic mask layer 600, so that etching loss is easily caused to the functional layer 530 in the first device region I, especially to the functional layer 530 in the first device region I near the second device region II; the sacrificial layer 610 is used for protecting the side wall of the organic mask layer 600, and effectively reduces the probability that the etching solution penetrates into the organic mask layer 600 through the side wall of the organic mask layer 600, so that the probability that the etching solution causes etching loss on the functional layer 530 of the first device region I is reduced, and the performance of the formed semiconductor structure is improved.
Specifically, the functional layer 530 is a work function layer, so that the threshold voltage and performance of the device formed in the first device region I can be prevented from being adversely affected.
In this embodiment, the material of the sacrificial layer 610 is silicon oxide. In other embodiments, the material of the sacrificial layer may also be amorphous silicon, amorphous carbon, or silicon nitride.
It should be noted that the thickness of the sacrificial layer 610 should not be too small, and should not be too large. If the thickness of the sacrificial layer 610 is too small, it is difficult to protect the sidewalls of the organic mask layer 600, and it is easy to cause a problem that the sacrificial layer 610 is completely removed before the etching of the first device region I functional layer 530 is not completed, thereby easily causing the etching loss of the first device region I functional layer 530; if the thickness of the sacrificial layer 610 is too large, the sacrificial layer 610 may easily cover the functional layer 530 in the second device region II too much, so that after the wet etching process, the functional layer 530 in the second device region II remains too much, and thus the electrical properties of the formed pull-down transistor and the pass-gate transistor are easily affected, and accordingly the performance of the formed semiconductor structure is reduced.
For this reason, in the present embodiment, the thickness of the sacrificial layer 610 is 2nm to 10 nm. That is, the sacrificial layer 610 has a size of 2nm to 10nm in a direction perpendicular to the sidewalls of the organic mask layer 600.
In other embodiments, the sacrificial layer also covers a top portion of the organic mask layer. Correspondingly, the sacrificial layer not only has a protection effect on the side wall of the organic mask layer, but also has a protection effect on the top of the organic mask layer, so that the probability that the etching solution penetrates into the organic mask layer through the top of the organic mask layer is reduced, and the probability that the etching solution causes etching loss on the functional layer of the first device area can be further reduced.
For a detailed description of the organic mask layer 600 and the sacrificial layer 610, please refer to the corresponding description in the foregoing embodiments, which is not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first device area and a second device area which are adjacent;
forming a functional layer on the substrate;
forming an organic mask layer on the functional layer of the first device area, wherein the thickness of the organic mask layer is 90nm to 300 nm;
forming a sacrificial layer on the side wall of the organic mask layer close to one side of the second device area, wherein the step of forming the sacrificial layer comprises the following steps: forming a sacrificial film which conformally covers the organic mask layer and the functional layer; etching and removing the top of the organic mask layer and the sacrificial film on the functional layer by adopting a maskless etching process, and reserving the sacrificial film positioned on the side wall of the organic mask layer as the sacrificial layer;
taking the organic mask layer and the sacrificial layer as masks, and etching and removing the functional layer of the second device area by adopting a wet etching process;
and removing the organic mask layer and the sacrificial layer.
2. The method of claim 1, wherein the sacrificial layer is made of silicon oxide, amorphous silicon, amorphous carbon, or silicon nitride.
3. The method of forming a semiconductor structure of claim 1, wherein the sacrificial layer has a thickness of 2nm to 10 nm.
4. The method of claim 1, wherein the process of forming the sacrificial layer is an atomic layer deposition process, a low temperature oxidation process, or a plasma enhanced chemical vapor deposition process.
5. The method of forming a semiconductor structure of claim 1, wherein the sacrificial layer further covers a top portion of the organic mask layer.
6. The method of forming a semiconductor structure of claim 1, wherein the step of forming the sacrificial layer comprises:
forming a sacrificial film covering the organic mask layer and the functional layer;
forming a pattern layer on the sacrificial film on the top of the organic mask layer, wherein the projections of the sacrificial film on the top and the side wall of the organic mask layer on the substrate are overlapped with the projection of the pattern layer on the substrate;
etching the sacrificial film by taking the graphic layer as a mask, and reserving the sacrificial film positioned at the top and the side wall of the organic mask layer as the sacrificial layer;
and removing the graph layer.
7. The method of claim 1, wherein the organic mask layer is a photoresist layer, an organic dielectric layer, a bottom anti-reflective coating, or a deep ultraviolet light absorbing layer.
8. The method of forming a semiconductor structure of claim 1, wherein the first device region is a PMOS region, the second device region is an NMOS region, and the functional layer is a P-type work function layer;
alternatively, the first and second electrodes may be,
the first device region is an NMOS region, the second device region is a PMOS region, and the functional layer is an N-type work function layer.
9. The method of claim 1, wherein the functional layer is TiN and the wet etching process uses NH as an etching solution4OH、H2O2And water, or NH4、H2O2Mixed solution of HCl and H2O2And water.
10. The method of claim 1, wherein the base comprises a substrate and discrete fins on the substrate;
before forming the functional layer on the substrate, the method further comprises the steps of: and forming a gate dielectric layer crossing the fin part, wherein the gate dielectric layer covers part of the top and part of the side wall surface of the fin part.
11. A semiconductor structure, comprising:
a substrate including a first device region and a second device region adjacent to each other;
a functional layer on the substrate;
the organic mask layer is positioned on the functional layer of the first device area, and the thickness of the organic mask layer is 90nm to 300 nm;
and the sacrificial layer is positioned on the side wall of the organic mask layer close to one side of the second device area and is formed by etching through a maskless etching process.
12. The semiconductor structure of claim 11, wherein the material of the sacrificial layer is silicon oxide, amorphous silicon, amorphous carbon, or silicon nitride.
13. The semiconductor structure of claim 11, wherein the sacrificial layer has a thickness of 2nm to 10 nm.
14. The semiconductor structure of claim 11, wherein the sacrificial layer also covers a top portion of the organic mask layer.
15. The semiconductor structure of claim 11, wherein the organic mask layer is a photoresist layer, an organic dielectric layer, a bottom anti-reflective coating, or a deep ultraviolet light absorbing layer.
16. The semiconductor structure of claim 11, wherein the first device region is a PMOS region, the second device region is an NMOS region, and the functional layer is a P-type work function layer;
alternatively, the first and second electrodes may be,
the first device region is an NMOS region, the second device region is a PMOS region, and the functional layer is an N-type work function layer.
17. The semiconductor structure of claim 11, wherein the base comprises a substrate, and a discrete fin on the substrate;
the semiconductor structure further includes: and the gate dielectric layer is positioned between the functional layer and the substrate, crosses the fin part, and covers part of the top and part of the side wall surface of the fin part.
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