CN106847874A - The forming method of the semiconductor devices with different threshold voltages - Google Patents
The forming method of the semiconductor devices with different threshold voltages Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of forming method of the semiconductor devices with different threshold voltages, including：Offer includes the substrate of first area and second area, and first area is identical with the area type of second area；First threshold voltage regulation doping treatment is carried out to first area substrate；Gate dielectric layer is formed in first area and second area substrate surface；First work-function layer on the gate dielectric layer surface of covering first area and second area is formed, the first work-function layer has first thickness；The first work-function layer to first area carries out reduction processing so that the first work-function layer of first area has second thickness；First gate electrode layer is formed on the first work-function layer surface with second thickness；The second gate electrode layer is formed on the first work-function layer surface of second area.The threshold voltage difference of the metal-oxide-semiconductor formed with second area invention increases the metal-oxide-semiconductor that first area is formed, so that the threshold voltage difference of semiconductor devices is worth to improve, meets the demand of device performance.
Description
Technical field
The present invention relates to semiconductor fabrication techniques field, more particularly to a kind of with different threshold voltages half
The forming method of conductor device.
Background technology
The main semiconductor devices of integrated circuit especially super large-scale integration is metal-oxide-partly lead
Body FET (MOS transistor).With continuing to develop for production of integrated circuits technology, semiconductor device
Part technology node constantly reduces, and the physical dimension of semiconductor structure follows Moore's Law and constantly reduces.When half
Conductor structure is reduced in size to when to a certain degree, what the various physics limits because of semiconductor structure were brought
Second-order effect occurs in succession, and the characteristic size of semiconductor structure is scaled to become more and more difficult.Its
In, in field of semiconductor fabrication, most challenge is how to solve that semiconductor structure leakage current is big to ask
Topic.The leakage current of semiconductor structure is big, mainly caused by traditional gate dielectric layer thickness constantly reduction.
The current solution for proposing is to replace traditional silicon dioxide gate dielectric using high-k gate dielectric material
Material, and use metal as gate electrode, there is Fermi's energy with conventional gate electrodes material to avoid high-g value
Level pinning effect and boron osmotic effect.The introducing of high-k/metal gate, reduces the leakage current of semiconductor structure.
Threshold voltage (Vt) is one of important parameter of MOS transistor, in the prior art to different MOS
The threshold voltage of transistor has different requirements.However, in the semiconductor devices of prior art formation,
The threshold voltage difference of different metal-oxide-semiconductors is smaller, and the threshold voltage difference scope in semiconductor devices is not enough to
Meet the demand of device.
Although the introducing of high-k/metal gate can to a certain extent improve the electric property of semiconductor structure,
But the electric property of the semiconductor structure that prior art is formed still has much room for improvement.
The content of the invention
The problem that the present invention is solved is to provide a kind of formation side of the semiconductor devices with different threshold voltages
Method, increases the threshold voltage difference of the device that first area and second area are formed, thus obtain with compared with
The semiconductor devices of big threshold voltage difference.
To solve the above problems, the present invention provides a kind of shape of the semiconductor devices with different threshold voltages
Into method, including：Substrate is provided, the substrate includes first area and second area, firstth area
Domain is identical with the area type of second area；Substrate to the first area carries out first threshold voltage tune
Section doping treatment；Gate dielectric layer is formed in the first area and second area substrate surface；Formation is covered
Cover first work-function layer on the gate dielectric layer surface of the first area and second area, first work content
Several layers have first thickness；The first work-function layer to the first area carries out reduction processing so that the
First work-function layer in one region has second thickness；In first work-function layer with second thickness
Surface forms first gate electrode layer；Second gate electricity is formed on the first work-function layer surface of the second area
Pole layer.
Optionally, before first work-function layer is formed, block is formed on the gate dielectric layer surface
Layer；Etching stop layer is formed in the block layer surface.
Optionally, using dry etch process, the first work-function layer of the first area is carried out thinning
Treatment.
Optionally, the processing step for carrying out the reduction processing includes：In the first work(of the second area
Function layer surface forms graph layer；With the graph layer as mask, to the first work content of the first area
Several layers carry out dry etch process；Remove the graph layer.
Optionally, the first area is PMOS area；The second area is PMOS area；Institute
The Doped ions for stating first threshold voltage regulation doping treatment are N-type ion；First work-function layer
Material is p-type work function material.
Optionally, the Doped ions of the first threshold voltage regulation doping treatment are P or As；Described
The material of one work-function layer is one or more in Ta, TiN, TaSiN or TiSiN.
Optionally, the first area is NMOS area；The second area is NMOS area；Institute
The Doped ions for stating threshold voltage adjustments doping treatment are p-type ion；The material of first work-function layer
It is N-type work function material.
Optionally, the Doped ions of the threshold voltage adjustments doping treatment are B, Ga or In；Described
The material of one work-function layer is in TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN or AlN
One or more.
Optionally, the first thickness is 30 angstroms to 60 angstroms；The second thickness is 15 angstroms to 30 angstroms.
Optionally, the first area also includes some sub-regions, wherein, to described several sub-districts
The substrate in domain carries out first threshold voltage regulation doping treatment, and substrate to some sub-regions is entered
The doping concentration of capable first threshold voltage regulation doping treatment is different.
Optionally, some sub-regions include pull up transistor region, input and output transistor area,
Standard threshold voltage region and low threshold region；The second area is ultralow threshold value voltage regime.
Optionally, some sub-regions include pull-down transistor region, input and output transistor area,
Transmission gate transistor area, standard threshold voltage region and low threshold region；The second area is
Ultralow threshold value voltage regime.
Optionally, in the gate dielectric layer of some sub-regions substrate surfaces, positioned at the input and output
The thickness of the gate dielectric layer of transistor area substrate surface is most thick.
Optionally, the gate dielectric layer of the input and output transistor area includes oxide layer and positioned at oxidation
The high-k gate dielectric layer of layer surface；Gate medium in the first area outside input and output transistor area
Layer includes boundary layer and the high-k gate dielectric layer positioned at interface layer surfaces, wherein, the thickness of the oxide layer
Thickness of the degree more than boundary layer.
Optionally, the first work-function layer to some sub-regions of the first area carries out reduction processing
Thickness thinning it is identical；Or, the first work-function layer to some sub-regions of the first area is entered
The thickness thinning of row reduction processing is differed.
Optionally, the substrate also includes the 3rd region and the 4th region, the 3rd region and the 4th area
The area type in domain is identical, and the 3rd region, the 4th region and first area and second area region class
Type is different；Also include step：Substrate to the 3rd region is carried out at second threshold voltage regulation doping
Reason；The gate dielectric layer is also located at the 3rd region and the 4th substrate areas surface；Form the covering grid
Second work-function layer of dielectric layer, second work-function layer has the 3rd thickness；To the 3rd region
The second work-function layer carry out reduction processing so that second work-function layer in the 3rd region have the 4th thickness；
The 3rd gate electrode layer is formed on the second work-function layer surface with the 4th thickness；In the 4th area
The second work-function layer surface in domain forms the 4th gate electrode layer.
Optionally, the first area and second area are PMOS area；3rd region and the 4th
Region is NMOS area；Wherein, the first area includes some sub-regions, if first area
Dry sub-regions include pull up transistor region, the first input and output transistor area, the first level threshold value
Voltage regime and the first low threshold region；The second area is the first ultralow threshold value voltage regime；
3rd region includes some sub-regions, and some sub-regions in the 3rd region include lower crystal pulling
Body area under control domain, the second input and output transistor area, transmission gate transistor area, the second level threshold value electricity
Intermediate pressure section and the second low threshold region；4th region is the second ultralow threshold value voltage regime.
Optionally, the substrate to some sub-regions of the first area carries out first threshold voltage regulation
Doping treatment, and the first threshold voltage carried out to the substrate of some sub-regions of the first area adjusts
The doping concentration for saving doping treatment is different；Substrate to some sub-regions in the 3rd region is entered
Row second threshold voltage adjusts doping treatment, and substrate to some sub-regions in the 3rd region is entered
The doping concentration of capable second threshold voltage regulation doping treatment is different.
Optionally, the substrate includes substrate and the discrete fin positioned at substrate surface.
Compared with prior art, technical scheme has advantages below：
The technical scheme of the forming method of the semiconductor devices with different threshold voltages that the present invention is provided
In, the substrate to first area carries out first threshold voltage regulation doping treatment；In first area and
The substrate surface in two regions forms gate dielectric layer；Form the gate dielectric layer of covering first area and second area
First work-function layer on surface, first work-function layer has first thickness；Then, to first area
The first work-function layer carry out reduction processing so that the first work-function layer of first area has second thickness；
Then first gate electrode layer is formed on the first work-function layer surface with second thickness, in second area
First work-function layer surface forms the second gate electrode layer.Because first area both experienced first threshold voltage
Regulation doping treatment, and first area first work-function layer of the first work-function layer thickness compared with second area
Thickness is small, therefore work function between the metal and semi-conducting material of first area is than second area
Difference between metal and semi-conducting material is big, therefore the threshold voltage ratio of metal-oxide-semiconductor that first area is formed
High many of threshold voltage of the metal-oxide-semiconductor that second area is formed, so that in the semiconductor devices of formation not
Threshold voltage difference with metal-oxide-semiconductor is larger, meets device performance requirements.
Further, the first area also includes some sub-regions, to the base of some sub-regions
Bottom carries out first threshold voltage regulation doping treatment, and the carried out to the substrate of some sub-regions
The doping concentration of one threshold voltage adjustments doping treatment is different, so that formed in first area
Each metal-oxide-semiconductor also has different threshold voltages.
Further, the first work-function layer to some sub-regions of first area carries out subtracting for reduction processing
Minimal thickness is differed, so that each metal-oxide-semiconductor formed in first area has different threshold voltages.
Further, the substrate that the present invention is provided also includes the region of area type identical the 3rd and the 4th area
Domain, and the 3rd region and four-range area type and first area and second area area type not
Together, the substrate to the 3rd region carries out second threshold voltage regulation doping treatment；Form covering gate dielectric layer
The second work-function layer；The second work-function layer to the 3rd region carries out reduction processing so that the 3rd region
The second work-function layer thickness the 4th thickness is reduced to by the 3rd thickness；Have the of the 4th thickness described
Two work-function layer surfaces form the 3rd gate electrode layer；In the second work-function layer of four-range surface shape
Into the 4th gate electrode layer.Likewise, the threshold value of the device that the present invention is formed in the 3rd region and the 4th region
Voltage difference is larger.
Brief description of the drawings
Fig. 1 to Figure 25 shows for the cross-section structure of the semiconductor devices forming process that one embodiment of the invention is provided
It is intended to.
Specific embodiment
Threshold voltage difference in the semiconductor devices formed from background technology, prior art is smaller,
It is difficult to meet device requirement.
It has been investigated that, in the semiconductor devices with different threshold voltages that prior art is formed, threshold value
The difference between maxima and minima in voltage in 150mV or so, but with the development of technology,
The difference of the threshold voltage in semiconductor devices is typically greater than 200mV, therefore, offer is provided badly
A kind of forming method of new semiconductor devices, the difference in increase threshold voltage between maxima and minima
Value, so as to meet the demand of device.
To solve the above problems, the present invention provides a kind of shape of the semiconductor devices with different threshold voltages
Into method, including：Substrate is provided, the substrate at least includes first area and second area, described the
One region is identical with the area type of second area；Substrate to the first area carries out first threshold electricity
Pressure regulation doping treatment；Gate dielectric layer is formed in the first area and second area substrate surface；Shape
Into first work-function layer on the gate dielectric layer surface for covering the first area and second area, described first
Work-function layer has first thickness；The first work-function layer to the first area carries out reduction processing, makes
The first work-function layer for obtaining first area has second thickness；In first work content with second thickness
Number layer surface forms first gate electrode layer；Second is formed on the first work-function layer surface of the second area
Gate electrode layer.Substrate in the present invention both to first area carries out first threshold voltage regulation doping treatment,
The first work-function layer also to first area carries out reduction processing so that the first work-function layer of first area
Thickness second thickness is reduced to by first thickness, therefore, first area formed device threshold voltage
High many of threshold voltage numerical value of the device that numeric ratio second area is formed, so that in improving semiconductor devices
The threshold voltage difference of metal-oxide-semiconductor, meets the performance requirement of device.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.
The semiconductor devices with different threshold voltages that Fig. 1 to Figure 25 is provided for one embodiment of the invention
Forming method.
With reference to Fig. 1, there is provided substrate, the substrate at least includes first area (sign) and second area
II。
The follow-up device in first area and each self-formings of second area II has different threshold voltages.Institute
State first area identical with the area type of second area II.The first area is PMOS area, institute
Second area II is stated for PMOS area；Or, the first area is NMOS area, described second
Region II is NMOS area.
The first area also includes some sub-regions, is subsequently each formed in some sub-regions
Device also have different threshold voltages.The second area II be ultralow threshold value voltage (ULVT,
Ultra-low VT) region.In another embodiment, the first area can also only include a sub-district
Domain.
In one embodiment, when the first area is PMOS area, some sub-regions bags
Include pull-up (PU, Pull Up) transistor area, input and output transistor (IO, Input Output) area
Domain, standard threshold voltage (SVT, Standard VT) region and low threshold voltage (LVT, Low VT)
Region.In another embodiment, when the first area is NMOS area, in the first area
Some sub-regions include drop-down (PD, Pull Down) transistor area, input and output transistor area,
Transmission gate (PG, Pass Gate) transistor area, standard threshold voltage region and low threshold region.
In one embodiment, the semiconductor devices of formation only includes NMOS tube.In another embodiment,
The semiconductor devices of formation only includes PMOS.
In the present embodiment, the semiconductor devices of formation includes NMOS tube and PMOS, wherein, no
Differed with the threshold voltage of NMOS tube, the threshold voltage of different PMOSs is differed.The substrate
Also include the area of the 3rd region (sign) and the 4th region IV, the 3rd region and the 4th region IV
Field type is identical, and the 3rd region, the 4th region IV and first area and second area II area type
It is different.In the present embodiment, the first area and second area II are PMOS area, the 3rd area
Domain and the 4th region IV are NMOS area.Wherein, the first area includes some sub-regions,
Some sub-regions of first area include the first low threshold region 11, the first standard threshold voltage area
Domain 12, pull up transistor the input and output transistor area 14 of region 13 and first；The second area II
It is the first ultralow threshold value voltage regime；3rd region includes some sub-regions, if the 3rd region
Dry sub-regions include the second low threshold region 21, the second standard threshold voltage region 22, lower crystal pulling
Body area under control domain 23, the input and output transistor area 25 of transmission gate transistor area 24 and second；4th area
Domain is the second ultralow threshold value voltage regime.In other embodiments, additionally it is possible to be first area and the secondth area
Domain is NMOS area, and the 3rd region and the 4th region are PMOS area.
So that the semiconductor devices for being formed is fin field effect pipe as an example, the substrate includes substrate to the present embodiment
101st, positioned at the discrete fin 102 on the surface of substrate 101.
In another embodiment, the semiconductor devices is planar transistor, and the substrate is planar substrates,
The planar substrates are silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, silicon-on-insulator substrate
Or germanium substrate on insulator, glass substrate or III-V substrate (such as gallium nitride substrate or arsenic
Gallium substrate etc.), grid structure is formed at the plane.
The material of the substrate 101 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate on insulator or the germanium substrate on insulator to state substrate 101；The fin 102
Material include silicon, germanium, SiGe, carborundum, GaAs or gallium indium.It is described in the present embodiment
Substrate 101 is silicon substrate, and the material of the fin 102 is silicon.
In the present embodiment, forming the substrate 101, the processing step of fin 102 includes：Initial lining is provided
Bottom；Patterned hard mask layer 103 is formed in the initial substrate surface；It is with the hard mask layer 103
Initial substrate described in mask etching, the initial substrate after etching as substrate 101, positioned at the surface of substrate 101
Projection as fin 102.
In one embodiment, the processing step for forming the hard mask layer 103 includes：It is initially formed just
Begin hard mask；Patterned photoresist layer is formed in the initial hard mask surface；With described patterned
Photoresist layer is initial hard mask described in mask etching, and hard mask layer 103 is formed in initial substrate surface；Go
Except the patterned photoresist layer.In other embodiments, the formation process of the hard mask layer can also
Enough include：Self-alignment duplex pattern (SADP, Self-aligned Double Patterned) technique, from
Triple graphical (the Self-aligned Triple Patterned) techniques of alignment or autoregistration quadruple are graphical
(Self-aligned Double Double Patterned) technique.The Dual graphing technique includes LELE
(Litho-Etch-Litho-Etch) technique or LLE (Litho-Litho-Etch) technique.
In the present embodiment, after the fin 102 is formed, retain positioned at the top surface of fin 102
Hard mask layer 103.The material of the hard mask layer 103 is silicon nitride, subsequently when flatening process is carried out,
The top surface of the hard mask layer 103 can play protection fin as the stop position of flatening process
The effect at 102 tops.In the present embodiment, the top dimension of the fin 102 is less than bottom size.At it
In his embodiment, the side wall of the fin can also be perpendicular with substrate surface, i.e. the top dimension of fin
Equal to bottom size.
With reference to Fig. 2, the barrier film 104 on the covering surface of substrate 101 and the surface of fin 102 is formed,
The top of the barrier film 104 is higher than the top of hard mask layer 103.
Before the barrier film 104 is formed, also including step：To the substrate 101 and fin 102
Oxidation processes are carried out, liner oxidation layer is formed on the surface of the substrate 101 and the surface of fin 102.
The barrier film 104 provides Process ba- sis to be subsequently formed separation layer；The material of the barrier film 104
Expect to be insulating materials, for example, silica, silicon nitride or silicon oxynitride.In the present embodiment, the isolation
The material of film 104 is silica.
Filling perforation (gap-filling) ability that the technique of barrier film 104 is formed to improve, using mobility
Vapour deposition (FCVD, Flowable CVD) or vertical width high are learned than chemical vapor deposition method (HARP
CVD), the barrier film 104 is formed.
After the barrier film 104 is formed, also including step：The barrier film 104 is annealed
Treatment, improves the consistency of the barrier film 104.
With reference to Fig. 3, the barrier film 104 (referring to Fig. 2) for removing segment thickness forms separation layer 114, institute
Separation layer 114 is stated positioned at the surface of substrate 101 and covering fin 102 partial sidewall surface, the separation layer
114 tops are less than the top of fin 102.
The material of the separation layer 114 is silica, silicon nitride or silicon oxynitride.In the present embodiment, institute
The material for stating separation layer 114 is silica.
In one embodiment, using dry etch process, the barrier film 104 of etching removal segment thickness.
In another embodiment, using wet-etching technology, the barrier film 104 of etching removal segment thickness.
Also include step：The etching removal hard mask layer 103 (referring to Fig. 2).Step can also be included：
Screen layer, the screen are formed at the top of the fin 102 and sidewall surfaces and the surface of separation layer 114
The material of layer is covered for silica or silicon oxynitride, its role is to：During follow-up doping treatment,
The screen layer can reduce the lattice damage that doping treatment is caused to fin 102.
With reference to Fig. 4, the substrate to the first area and second area II carries out the first well region doping treatment,
The first well region (not shown) is formed in the substrate of the first area and second area II.
In the present embodiment, the first well region is carried out to the substrate 101 of the first area and second area II and is mixed
Live together reason.The first area and second area II are PMOS area, the first well region doping treatment
Doped ions be N-type ion, N-type ion be P, As or Sb.
The processing step for carrying out the first well region doping treatment includes：In the 3rd region and the 4th area
The surface of separation layer 114 of domain IV and the surface of fin 102 form the first graph layer 105, first figure
The top of shape layer 105 is higher than the top of fin 102；With first graph layer 105 as mask, to described
The substrate 101 of one region and second area II carries out the first well region doping treatment；Then, described the is removed
One graph layer 105.
The material of first graph layer 105 is hard mask material or Other substrate materials.
With reference to Fig. 5, the substrate to the 3rd region and the 4th region IV carries out the second well region doping treatment,
The second well region (not shown) is formed in the substrate of the 3rd region and the 4th region IV.
In the present embodiment, the second well region is carried out to the substrate 101 in the 3rd region and the 4th region IV and is mixed
Live together reason.3rd region and the 4th region IV are NMOS area, at the second well region doping
The Doped ions of reason are p-type ion, and p-type ion is B, Ga or In.
The processing step for carrying out the second well region doping treatment includes：In the first area and the secondth area
The surface of separation layer 114 of domain II and the surface of fin 102 form second graph layer 106, the second graph
The top of layer 106 is higher than the top of fin 102；With second graph layer 106 as mask, to the described 3rd
The substrate 101 of region and the 4th region IV carries out the second well region doping treatment；Then, described second is removed
Graph layer 106.
The material of the second graph layer 106 is hard mask material or Other substrate materials.
Follow-up also to include step, the substrate to the first area carries out first threshold voltage regulation treatment,
Because first area also includes some sub-regions, therefore the is carried out to the substrate of some sub-regions
One threshold voltage adjustments doping treatment, and the first threshold electricity carried out to the substrate of some sub-regions
The doping concentration of pressure regulation doping treatment is different.It is described in detail below with reference to accompanying drawing, it is described
First threshold voltage regulation doping treatment is actually that fin 102 is carried out.
With reference to Fig. 6, the substrate to the first low threshold region 11 in the first area carries out first
Threshold voltage adjustments doping treatment.
When the first area is PMOS area, the first threshold voltage adjusts the doping of doping treatment
Ion is N-type ion, and the Doped ions of the first threshold voltage regulation doping treatment are P or As；Institute
When stating first area for NMOS area, the Doped ions of the first threshold voltage regulation doping treatment are
P-type ion, the Doped ions of the first threshold voltage regulation doping treatment are B or Ga.
In the present embodiment, the first area is PMOS area, to first low threshold region
11 processing steps for carrying out first threshold voltage regulation doping treatment include：In the second area II,
Region in three regions, the 4th region IV and first area in addition to the first low threshold region 11
The surface of separation layer 114 and the surface of fin 102 formed the 3rd graph layer 107；With the 3rd graph layer
107 is mask, and N-type ion implanting is carried out to first low threshold region 11；Then, remove
3rd graph layer 107.
In the present embodiment, according to the threshold value electricity needed for the device that first low threshold region 11 is formed
Pressure scope, it is determined that carrying out the doping concentration that first threshold voltage adjusts doping treatment to it.
With reference to Fig. 7, the substrate to the first standard threshold voltage region 12 in the first area carries out
One threshold voltage adjustments doping treatment.
In the present embodiment, the first area is PMOS area, the first threshold voltage regulation doping
The Doped ions for the treatment of are N-type ion.
Substrate to the first standard threshold voltage region 12 carries out first threshold voltage regulation doping treatment
Processing step include：In the second area II, the 3rd region, the 4th region IV and the firstth area
The surface of separation layer 114 in the region in domain in addition to the first standard threshold voltage region 12 and fin 102
Surface forms the 4th graph layer 108；With the 4th graph layer 108 as mask, to the first standard threshold
Threshold voltage region 12 carries out N-type ion implanting；Then, the 4th graph layer 108 is removed.
The threshold voltage ranges needed for device according to the first standard threshold voltage region 12 formation, really
It is fixed that the doping concentration that first threshold voltage adjusts doping treatment is carried out to it.In the present embodiment, to described
The first threshold voltage that one standard threshold voltage region 12 and the first low threshold region 11 are carried out is adjusted
The doping concentration for saving doping treatment is differed.
With reference to Fig. 8, to the first area in the substrate in the region 13 that pulls up transistor carry out first threshold
Voltage-regulation doping treatment.
In the present embodiment, the first area is PMOS area, the first threshold voltage regulation doping
The Doped ions for the treatment of are N-type ion.
Substrate to the region 13 that pulls up transistor carries out the technique that first threshold voltage adjusts doping treatment
Step includes：Removed in the second area II, the 3rd region, the 4th region IV and first area
The surface of separation layer 114 and the surface of fin 102 in the region pulled up transistor outside region 13 form the 5th
Graph layer 109；With the 5th graph layer 109 as mask, the region 13 that pulls up transistor is carried out
N-type ion implanting；Then, the 5th graph layer 109 is removed.
The threshold voltage ranges needed for device according to the formation of region 13 that pulls up transistor, it is determined that to it
Carry out the doping concentration that first threshold voltage adjusts doping treatment.In the present embodiment, to the upper crystal pulling
Area under control domain 13, the first standard threshold voltage region 12 and the first low threshold region 11 carry out
The doping concentration of one threshold voltage adjustments doping treatment is differed.
With reference to Fig. 9, the substrate to the first input and output transistor area 14 in the first area is carried out
First threshold voltage adjusts doping treatment.
In the present embodiment, the first area is PMOS area, the first threshold voltage regulation doping
The Doped ions for the treatment of are N-type ion.
Substrate to the first input and output transistor area 14 is carried out at first threshold voltage regulation doping
The processing step of reason includes：To the second area II, the 3rd region, the 4th region IV and first
The surface of separation layer 114 in the region in region in addition to the first input and output transistor area 14 and fin
102 surfaces form the 6th graph layer 110；It is defeated to described first with the 6th graph layer 110 as mask
Entering output transistor region 14 carries out N-type ion implanting；Then, the 6th graph layer 110 is removed.
According to the threshold voltage ranges needed for the device that the first input and output transistor area 14 is formed,
It is determined that carrying out the doping concentration that first threshold voltage adjusts doping treatment to it.In the present embodiment, to described
First input and output transistor area 14, the region 13 that pulls up transistor, the first standard threshold voltage region 12
And first low threshold region 11 carry out first threshold voltage regulation doping treatment doping concentration not
It is identical.
By adjusting the Doped ions concentration in first area in the substrate of all subregion so that be correspondingly formed
Device threshold voltage numerical value it is different.General, Doped ions concentration is smaller in the substrate of subregion,
The threshold voltage numerical value of the device being correspondingly formed is smaller.
Subsequently also include, the substrate to the 3rd region carries out second threshold voltage regulation treatment, due to
3rd region includes some sub-regions, thus follow-up some sub-regions to the 3rd region base
Bottom carries out second threshold voltage regulation treatment, and substrate to some sub-regions in the 3rd region is entered
The doping concentration of capable second threshold voltage regulation doping treatment is different.Carried out below with reference to accompanying drawing
Describe in detail, doping treatment is actual that fin 102 is carried out for second threshold voltage regulation.
With reference to Figure 10, the substrate to the second low threshold region 21 in the 3rd region carries out second
Threshold voltage adjustments doping treatment.
When 3rd region is PMOS area, the second threshold voltage adjusts the doping of doping treatment
Ion is N-type ion, and the Doped ions of the second threshold voltage regulation doping treatment are P or As；Institute
When stating the 3rd region for NMOS area, the Doped ions of the second threshold voltage regulation doping treatment are
P-type ion, the Doped ions of the second threshold voltage regulation doping treatment are B or Ga.
In the present embodiment, the 3rd region is NMOS area, to second low threshold region
The processing step that 21 substrate carries out second threshold voltage regulation doping treatment includes：The first area,
Region in second area II, the 4th region IV, the 3rd region in addition to the second low threshold region 21
The surface of separation layer 114 and the surface of fin 102 formed the 7th graph layer 111；With the 7th graph layer
111 is mask, and p-type ion implanting is carried out to second low threshold region 21；Then, remove
7th graph layer 111.
According to the threshold voltage ranges needed for the device that second low threshold region 21 is formed, it is determined that
The doping concentration that second threshold voltage adjusts doping treatment is carried out to it.
With reference to Figure 11, the substrate to the second standard threshold voltage region 22 in the 3rd region carries out
Two threshold voltage adjustments doping treatments.
In the present embodiment, the 3rd region is NMOS area, the second threshold voltage regulation doping
The Doped ions for the treatment of are p-type ion.
Substrate to the second standard threshold voltage region 22 carries out second threshold voltage regulation doping treatment
Processing step include：In the first area, second area II, the 4th region IV, the 3rd region
The surface of separation layer 114 and the surface of fin 102 in the region in addition to the second standard threshold voltage region 22
Form the 8th graph layer 112；With the 8th graph layer 112 as mask, to second level threshold value electricity
Intermediate pressure section 22 carries out p-type ion implanting；Then, the 8th graph layer 112 is removed.
The threshold voltage ranges needed for device according to the second standard threshold voltage region 22 formation, really
It is fixed that the doping concentration that second threshold voltage adjusts doping treatment is carried out to it.In the present embodiment, to described
The second threshold voltage that two standard threshold voltage regions 22 and the second low threshold region 21 are carried out is adjusted
The doping concentration for saving doping treatment is differed.
With reference to Figure 12, the substrate to the pull-down transistor region 23 in the 3rd region carries out Second Threshold
Voltage-regulation doping treatment.
In the present embodiment, the 3rd region is NMOS area, the second threshold voltage regulation doping
The Doped ions for the treatment of are p-type ion.
Substrate to the pull-down transistor region 23 carries out the technique that second threshold voltage adjusts doping treatment
Step includes：Removed in the first area, second area II, the 4th region IV and the 3rd region
The surface of separation layer 114 in the region outside pull-down transistor region 23 and the surface of fin 102 form the 9th
Graph layer 113；With the 9th graph layer 113 as mask, the pull-down transistor region 23 is carried out
P-type ion implanting；Then, the 9th graph layer 113 is removed.
According to the threshold voltage ranges needed for the device that the pull-down transistor region 23 is formed, it is determined that to it
Carry out the doping concentration that second threshold voltage adjusts doping treatment.In the present embodiment, to the lower crystal pulling
Area under control domain 23, the second standard threshold voltage region 22 and the second low threshold region 21 carry out
The doping concentration of two threshold voltage adjustments doping treatments is differed.
With reference to Figure 13, the substrate to the transmission gate transistor area 24 in the 3rd region carries out the second threshold
Threshold voltage adjusts doping treatment.
In the present embodiment, the 3rd region is NMOS area, the second threshold voltage regulation doping
The Doped ions for the treatment of are p-type ion.
Substrate to the transmission gate transistor area 24 carries out the work that second threshold voltage adjusts doping treatment
Skill step includes：In the first area, second area II, the 4th region IV and the 3rd region
The surface of separation layer 114 and the surface of fin 102 in the region in addition to transmission gate transistor area 24 are formed
Tenth graph layer 115；With the tenth graph layer 115 as mask, to the transmission gate transistor area
24 carry out p-type ion implanting；Then, the tenth graph layer 115 is removed.
According to the threshold voltage ranges needed for the device that the transmission gate transistor area 24 is formed, it is right to determine
It carries out the doping concentration that second threshold voltage adjusts doping treatment.In the present embodiment, to the transmission gate
Transistor area 24, pull-down transistor region 23, the second standard threshold voltage region 22 and second are low
The doping concentration of the second threshold voltage regulation doping treatment that threshold voltage regions 21 are carried out is differed.
With reference to Figure 14, the substrate to the second input and output transistor area 25 in the 3rd region is carried out
Second threshold voltage adjusts doping treatment.
In the present embodiment, the 3rd region is NMOS area, the second threshold voltage regulation doping
The Doped ions for the treatment of are p-type ion.
Substrate to the second input and output transistor area 25 is carried out at second threshold voltage regulation doping
The processing step of reason includes：In the first area, second area II, the 4th region IV and the 3rd
The surface of separation layer 114 in the region in region in addition to the second input and output transistor area 25 and fin
102 surfaces form the first mask layer 116；With first mask layer 116 as mask, to the transmission gate
Transistor area 24 carries out p-type ion implanting；Then, first mask layer 116 is removed.
According to the threshold voltage ranges needed for the device that the second input and output transistor area 25 is formed,
It is determined that carrying out the doping concentration that second threshold voltage adjusts doping treatment to it.In the present embodiment, to described
Second input and output transistor area 25, transmission gate transistor area 24, pull-down transistor region 23,
The second threshold voltage that two standard threshold voltage regions 22 and the second low threshold region 21 are carried out is adjusted
The doping concentration for saving doping treatment is differed.
By adjusting the Doped ions concentration in the 3rd region in the substrate of all subregion so that be correspondingly formed
Device threshold voltage numerical value it is different.General, Doped ions concentration is smaller in the substrate of subregion,
The threshold voltage numerical value of the device being correspondingly formed is smaller.
It is follow-up also to include step：First grid structure is formed in the first area substrate surface；Described
Second area substrate surface forms second grid structure；The 3rd grid are formed on the 3rd substrate areas surface
Pole structure；The 4th grid structure is formed on the 4th substrate areas surface.Specifically, subsequently also including
Step：Gate dielectric layer is formed in the first area and second area substrate surface；Form covering described
First work-function layer on the gate dielectric layer surface of first area and second area, the first work-function layer tool
There is first thickness；The first work-function layer to the first area carries out reduction processing so that first area
The first work-function layer there is second thickness；The gate dielectric layer is also located at the 3rd region and the 4th region base
Basal surface；Second work-function layer on covering the 3rd region and four-range gate dielectric layer surface is formed,
Second work-function layer has the 3rd thickness；Second work-function layer in the 3rd region is carried out thinning
Treatment so that second work-function layer in the 3rd region has the 4th thickness；Described with second thickness
First work-function layer surface forms first gate electrode layer；On the first work-function layer surface of the second area
Form the second gate electrode layer；The 3rd grid electricity is formed on the second work-function layer surface with the 4th thickness
Pole layer；The 4th gate electrode layer is formed on the second work-function layer of four-range surface.
Wherein, first grid structure, second grid structure, the 3rd grid structure or the 4th grid structure be both
Can be made using first grid technique (gate first), additionally it is possible to made using rear grid technique (gate last).
In the present embodiment, in the gate dielectric layer of some sub-regions substrate surfaces of the first area, positioned at institute
The thickness for stating the gate dielectric layer of the first input and output transistor area substrate surface is most thick.3rd region
Some sub-regions substrate surfaces gate dielectric layer in, positioned at the second input and output transistor area
The thickness of the gate dielectric layer of substrate surface is most thick.
Below with reference to accompanying drawing to first grid structure.Second grid structure, the 3rd grid structure and the 4th
The formation process of grid structure is described in detail, as a example by using rear grid technique.
With reference to Figure 15, in the first area, second area II, the 3rd region and the 4th region IV substrates
Surface forms oxide-film；Pseudo- grid film is formed on the oxide-film surface；The graphical pseudo- grid film and oxygen
Change film, formed and be located at first area, second area II, the 3rd region and the 4th region IV part of substrate tables
The oxide layer 201 in face, forms the pseudo- gate layer 202 positioned at the surface of oxide layer 201.
The pseudo- gate layer 202 occupies first grid structure, second grid structure, the 3rd grid being subsequently formed
The locus of pole structure and the 4th grid structure.
The material of the oxide layer 201 is silica or silicon oxynitride.In the present embodiment, the oxide layer
201 thickness is thicker, follow-up to retain positioned at the first input and output transistor area 14 and the second input
The oxide layer 201 in output transistor region 25, and then cause the first input in all subregion of first area
The gate dielectric layer thickness in output transistor region 14 is most thick, and the second input is defeated in all subregion in the 3rd region
The thickness for going out the gate dielectric layer of transistor area 25 is most thick.
The material of the pseudo- gate layer 202 is polysilicon, non-crystalline silicon or amorphous carbon.In the present embodiment, institute
The material for stating pseudo- gate layer 202 is polysilicon.
Also include step：Offset side wall is formed in the sidewall surfaces of pseudo- gate layer 202；To the pseudo- gate layer
The first area fin 102 of 202 both sides carries out that treatment is lightly doped, and forms the first LDD region domain, this implementation
In example, including the fin 102 of all subregion in first area is carried out that treatment is lightly doped；To the pseudo- grid
The second area II fins 102 of 202 both sides of layer carry out that treatment is lightly doped, and form the second LDD region domain；It is right
3rd region fin 102 of the both sides of pseudo- gate layer 202 carries out that treatment is lightly doped, and forms the 3rd LDD region
Domain, in the present embodiment, including to the fin 102 of all subregion in the 3rd region carries out that treatment is lightly doped；
The 4th region IV fin 102 to the both sides of pseudo- gate layer 202 carries out that treatment is lightly doped, and forms the 4th
LDD region domain.
Also include step：Master wall is formed in the offset side wall sidewall surfaces；To the pseudo- gate layer 202
The first area fin 102 of both sides carries out heavy doping treatment, forms a S/D regions, in the present embodiment,
Heavy doping treatment is carried out including the fin 102 to all subregion in first area；To the pseudo- gate layer 202
The second area II fins 102 of both sides carry out heavy doping treatment, form the 2nd S/D regions；To the puppet
3rd region fin 102 of the both sides of gate layer 202 carries out heavy doping treatment, forms the 3rd S/D regions, this
In embodiment, including heavy doping treatment is carried out to the fin 102 of all subregion in the 3rd region；To described
4th region IV fin 102 of the both sides of pseudo- gate layer 202 carries out heavy doping treatment, forms the 4th S/D regions.
With reference to Figure 16, the pseudo- gate layer 202 (referring to Figure 15) is removed.
Before the pseudo- gate layer 202 is removed, also including step：Interlayer is formed in the substrate surface to be situated between
Matter layer (not shown), the sidewall surfaces of the pseudo- gate layer 202 of interlayer dielectric layer covering.
Using dry etch process, wet-etching technology or SiCoNi etching systems, the etching removal puppet
Gate layer 202.
With reference to Figure 17, etching removal is located at the first input and output transistor area 14, the second input and output crystalline substance
Oxide layer 201 outside body area under control domain 25.
In the present embodiment, in the first input and output transistor area 14, the second input and output transistor
The surface of oxide layer 201 in region 25 forms the 3rd mask layer 203, exposes second area II, the 4th area
Domain IV, the first low threshold region 11, the first standard threshold voltage region 12, pull up transistor region
13rd, the second low threshold region 21, the second standard threshold voltage region 22, pull-down transistor region 23
And the surface of oxide layer 201 of transmission gate transistor area 24；With the 3rd mask layer 203 as mask,
The oxide layer 201 that etching removal the 3rd mask layer 203 exposes；Then, the 3rd mask is removed
Layer 203.
With reference to Figure 18, the second area II, the 4th region IV, the first low threshold region 11,
First standard threshold voltage region 12, the region 13 that pulls up transistor, the second low threshold region 21,
The base of two standard threshold voltage regions 22, pull-down transistor region 23 and transmission gate transistor area 24
Basal surface forms boundary layer 204.
The material of the boundary layer 204 is silica or silicon oxynitride.In the present embodiment, using oxidation work
Skill forms the boundary layer 204, and the oxidation technology is dry-oxygen oxidation, wet-oxygen oxidation or steam oxidation, shape
Into boundary layer 204 be only located at the top surface of fin 102 and sidewall surfaces that expose, the boundary layer
Thickness of 204 thickness less than oxide layer 202.The boundary layer 204 and oxide layer 202 are gate medium
A part for layer；Due to the thickness of the thickness more than boundary layer 204 of oxide layer 202 so that follow-up first
The thickness of the gate dielectric layer of the input and output transistor area 25 of input and output transistor area 14 and second compared with
The thickness of the gate dielectric layer in other regions is thicker.
In other embodiments, the boundary layer is formed using depositing operation, the depositing operation is chemistry
Vapour deposition, physical vapour deposition (PVD) or ald, the boundary layer of formation are also located at aoxidizing layer surface.
Likewise, the gate medium of follow-up first input and output transistor area and the second input and output transistor area
The thickness of layer is thicker compared with the thickness of the gate dielectric layer in other regions.
With reference to Figure 19, high-k gate dielectric is formed on the surface of the boundary layer 204 and the surface of oxide layer 202
Layer 205.
The material of the high-k gate dielectric layer 205 is high-k gate dielectric material, wherein, high-k gate dielectric material
Material refers to gate dielectric material of the relative dielectric constant more than silica relative dielectric constant, the k high
The material of gate dielectric layer 205 is HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2
Or Al2O3。
The k grid high are formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process to be situated between
Matter layer 205.In the present embodiment, the material of the high-k gate dielectric layer 205 is HfO2, the k grid high
The thickness of dielectric layer 205 is 5 angstroms to 15 angstroms, and the high-k gate dielectric is formed using atom layer deposition process
Layer 205.
For the first input and output transistor area 14 and the second input and output transistor area 25,
The gate dielectric layer includes：Oxide layer 202 and the high-k gate dielectric layer 205 positioned at the surface of oxide layer 202.
For the area in addition to the first input and output transistor area 14 and the second input and output transistor area 25
For domain, the gate dielectric layer includes：Boundary layer 204 and the k grid high positioned at the surface of boundary layer 204
Dielectric layer 205.From Such analysis, in all subregion of first area, the first input and output transistor area
The thickness of the gate dielectric layer in domain 14 is most thick；In 3rd region all subregion, the second input and output transistor area
The thickness of the gate dielectric layer in domain 25 is most thick.
With continued reference to Figure 19, the gate dielectric layer surface of the covering first area and second area II is formed
First work-function layer 208.
Before first work-function layer 208 is formed, also including step：In the high-k gate dielectric layer
205 surfaces form cap 206；Etching stop layer (not shown) is formed on the surface of the cap 206.
The cap 206 plays a part of to protect high-k gate dielectric layer 205, prevents follow-up etching work
Skill causes unnecessary etching to lose high-k gate dielectric layer 205, and the cap 206 also helps resistance
Gear metal ion spreads in high-k gate dielectric layer 205.
The material of the cap 206 is TiN；Using chemical vapor deposition method, physical vapour deposition (PVD) work
Skill or atom layer deposition process form the cap 206.
The etching stop layer is with the first work-function layer and the material of the second work-function layer being subsequently formed not
Together, so that the etching technics of the work-function layer of subsequent etching first is small to the etch rate of etching stop layer,
The etching technics of the work-function layer of subsequent etching second is small to the etch rate of etching stop layer, right so as to avoid
High-k gate dielectric layer 205 causes etching injury.In the present embodiment, the material of the etching stop layer is TaN,
The etching stop layer is formed using atom layer deposition process.
In the present embodiment, first work-function layer 208 is located at first area, second area II, the 3rd
Region and the 4th region IV, the removal of rear extended meeting etching is positioned at the 3rd region and first work content of the 4th region IV
Several layers 208.First work-function layer 208 is located at the etching stopping layer surface.
The first area and second area II are PMOS area, the material of first work-function layer 208
Expect to be p-type work function material, the material of first work-function layer 208 for Ta, TiN, TaSiN or
One or more in TiSiN.Using chemical vapor deposition method, physical gas-phase deposition or atomic layer
Depositing operation forms first work-function layer 208.
In the present embodiment, the material of first work-function layer 208 is TiN, first work-function layer
208 have first thickness, and the first thickness is 30 angstroms to 60 angstroms.
With reference to Figure 20, the first work-function layer 208 to the first area carries out reduction processing so that the
First work-function layer 208 in one region has second thickness.
The thickness of first work-function layer 208 is thinner, the region of the first work-function layer 208
Work function between metal and semi-conducting material is bigger, the threshold value of the device that corresponding region is formed
Voltage value is bigger.
In the present embodiment, because second area II is ultralow threshold value voltage regime, the second area II shapes
Into device threshold voltage numerical value very little, and in order to meet semiconductor devices demand, second area II shapes
Into device threshold voltage and first area formed device threshold voltage between difference it is larger, it is preceding
The first threshold voltage regulation doping treatment that stating is carried out is difficult to obtain the threshold voltage of larger difference.Therefore,
The present embodiment further carries out reduction processing to the first work-function layer 208 of first area so that the firstth area
The threshold voltage numerical value of the device that domain is formed further increases, so that the device that second area II is formed
Threshold voltage and first area formed device threshold voltage between difference it is larger.
In the present embodiment, the second thickness is 15 angstroms to 30 angstroms.Using dry etch process, wet method
Etching technics or SiCoNi etching systems, the first work-function layer of etching removal first area segment thickness
208.Specifically, in first work function of the second area II, the 3rd region and the 4th region IV
208 surface of layer form the 4th mask layer 209；With the 4th mask layer 209 as mask, etching removal the
First work-function layer 208 of the segment thickness in one region, makes the thickness of the first work-function layer 208 of first area
Degree is thinned to second thickness by first thickness.In the present embodiment, the 4th mask layer 209 also covers
The surface of first work-function layer 208 of one input and output transistor area 14.
In the present embodiment, the first work-function layer 208 of all subregion of the first area is carried out thinning
The thickness thinning for the treatment of is identical, i.e. the second thickness of the first work-function layer 208 of first area all subregion
It is identical.In other embodiments, the first work-function layer to all subregion in first area carries out thinning place
The thickness thinning of reason can also be different, i.e., the of the first work-function layer of all subregion in first area
Two thickness are different.
With reference to Figure 21, removal is positioned at the 3rd region and first work-function layer 208 of the 4th region IV.
Specifically, forming the on the surface of the first work-function layer 208 of the first area and second area II
Five mask layers 210；With the 5th mask layer 210 as mask, etching removal is located at the 3rd region and the 4th
First work-function layer 208 of region IV；Then, the 5th mask layer 210 is removed.
In other embodiments, additionally it is possible to which first removal is located at the 3rd region and the work function of four-range first
Layer, then the first work-function layer to first area carries out reduction processing.
With reference to Figure 22, the second work-function layer 211 of the covering gate dielectric layer is formed.
In the present embodiment, second work-function layer 211 is located at first area, second area II, the 3rd area
Domain and the 4th region IV, second work-function layer 211 are located at the first of first area and second area II
The surface of work-function layer 208, is also located at the etching stopping layer surface of the 3rd region and the 4th region IV.Subsequently
Removal can be etched positioned at first area and second work-function layer 211 of second area II.
3rd region and the 4th region IV are NMOS area, second work-function layer 211
Material is N-type work function material, the material of second work-function layer 211 is TiAl, TiAlC, TaAlN,
One or more in TiAlN, MoN, TaCN or AlN.Using chemical vapor deposition method, physics
Gas-phase deposition or atom layer deposition process form second work-function layer 211.
In the present embodiment, the material of second work-function layer 211 is TiAlC, second work-function layer
211 have the 3rd thickness, and the 3rd thickness is 30 angstroms to 60 angstroms.
With reference to Figure 23, the second work-function layer 211 to the 3rd region carries out reduction processing so that the
Second work-function layer 211 in three regions has the 4th thickness.
The thickness of second work-function layer 211 is thinner, the region of the second work-function layer 211
Work function between metal and semi-conducting material is bigger, the threshold value of the device that corresponding region is formed
Voltage value is bigger.
In the present embodiment, because the 4th region IV is ultralow threshold value voltage regime, the 4th region IV
The threshold voltage numerical value very little of the device of formation, and in order to meet semiconductor devices demand, the 4th region IV
Difference between the threshold voltage of the device that the threshold voltage of the device of formation and the 3rd region are formed is larger,
The foregoing second threshold voltage regulation doping treatment for carrying out is difficult to obtain the threshold voltage of larger difference.Therefore,
The present embodiment further carries out reduction processing to second work-function layer 211 in the 3rd region so that the 3rd area
The threshold voltage numerical value of the device that domain is formed further increases, so that the device that the 4th region IV is formed
Threshold voltage and the 3rd region formed device threshold voltage between difference it is larger.
In the present embodiment, the 4th thickness is 15 angstroms to 30 angstroms.Using dry etch process, wet method
Etching technics or SiCoNi etching systems, the second work-function layer of etching the 3rd region segment thickness of removal
211.Specifically, in the second work function of the first area, second area II and the 4th region IV
211 surface of layer form the 5th mask layer 212；With the 5th mask layer 212 as mask, etching removal the
Second work-function layer 211 of the segment thickness in three regions, makes the thickness of second work-function layer 211 in the 3rd region
Degree is thinned to the 4th thickness by the 3rd thickness.In the present embodiment, the 5th mask layer 212 also covers biography
Send the input and output transistor area 25 of a transistor area 23 and second.
In the present embodiment, the second work-function layer 211 of all subregion in the 3rd region is carried out thinning
The thickness thinning for the treatment of is identical, i.e. the 4th thickness of the second work-function layer 211 of the 3rd region all subregion
It is identical.In other embodiments, the second work-function layer to all subregion in the 3rd region subtracts
The thickness thinning of thin treatment can also be different, i.e., the second work content of all subregion in described 3rd region
Several layers of the 4th thickness is different.
With reference to Figure 24, removal is positioned at first area and second work-function layer 211 of second area II.
Specifically, forming the on the surface of the second work-function layer 211 of the 3rd region and the 4th region IV
Six mask layers 213；With the 6th mask layer 213 as mask, etching removal is located at first area and second
Second work-function layer 211 of region II；Then, the 6th mask layer 213 is removed.
In other embodiments, additionally it is possible to which first removal is positioned at first area and the second work function of second area
Layer, then the second work-function layer to the 3rd region carries out reduction processing.
In other embodiments, first area and second area are PMOS area, the 3rd region and the 4th
When region is NMOS area, additionally it is possible to retain the second work-function layer positioned at first area and second area,
Positioned at the MOS that the second work-function layer of first area and second area is formed to first area and second area
The threshold voltage influence of pipe is smaller.
With reference to Figure 25, first grid electricity is formed on the surface of the first work-function layer 208 with second thickness
Pole layer 302；The second gate electrode layer 301 is formed on the surface of the first work-function layer 208 of the second area II；
The 3rd gate electrode layer 304 is formed on the surface of the second work-function layer 211 with the 4th thickness；Described
The surface of second work-function layer 211 of the 4th region IV forms the 4th gate electrode layer 303.
The material of the first gate electrode layer 302 includes Al, Cu, Ag, Au, Pt, Ni, Ti or W
In one or more；The material of second gate electrode layer 301 include Al, Cu, Ag, Au, Pt,
One or more in Ni, Ti or W；The material of the 3rd gate electrode layer 304 include Al, Cu,
One or more in Ag, Au, Pt, Ni, Ti or W；The material bag of the 4th gate electrode layer 303
Include one or more in Al, Cu, Ag, Au, Pt, Ni, Ti or W.
In the present embodiment, the 302, second gate electrode layer 301 of the first gate electrode layer, the 3rd gate electrode layer
304 and the 4th gate electrode layer 303 material it is identical.The first grid is formed in the processing step along with
Electrode layer 302, the second gate electrode layer 301, the 3rd gate electrode layer 304 and the 4th gate electrode layer 303.
Formed the 302, second gate electrode layer 301 of first gate electrode layer, the 3rd gate electrode layer 304 and
The processing step of the 4th gate electrode layer 303 includes：On the surface of the first work-function layer 208 and second
The surface of work-function layer 211 forms gate electrode film, and the gate electrode film top is higher than interlayer dielectric layer top table
Face；Grinding removal higher than the gate electrode film at the top of interlayer dielectric layer, be correspondingly formed the first gate electrode layer 302,
Second gate electrode layer 301, the 3rd gate electrode layer 304 and the 4th gate electrode layer 303.
Because the substrate of second area II does not carry out first threshold voltage regulation doping treatment, and second not only
The thickness of first work-function layer 208 of region II is more than the thickness of the first work-function layer 208 of first area,
So that the threshold voltage of the device of second area II formation is lower than the threshold voltage of the device that first area is formed
It is many, therefore the device that the second area II device and the first area that are formed are formed has larger threshold
Threshold voltage difference, so as to meet semiconductor device performance requirements.Likewise, due to the base of the 4th region IV
Bottom do not carry out not only second threshold voltage regulation doping treatment, and the 4th region IV the second work-function layer 211
Thickness more than the 3rd region the second work-function layer 211 thickness so that the 4th region IV formed device
Much lower than the threshold voltage of the device that the 3rd region is formed of the threshold voltage of part, therefore the 4th region
The device that the device and the 3rd region that IV is formed are formed has larger threshold voltage difference, so as to meet half
Conductor device performance requirement.
It should be noted that in other embodiments, additionally it is possible to using first grid technique, have described in formation
First work-function layer of first thickness, the first work-function layer with second thickness, with the 3rd thickness
Second work-function layer and the second work-function layer with the 4th thickness.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (20)
1. it is a kind of have different threshold voltages semiconductor devices forming method, it is characterised in that including：
Substrate is provided, the substrate includes first area and second area, the first area and the secondth area
The area type in domain is identical；
Substrate to the first area carries out first threshold voltage regulation doping treatment；
Gate dielectric layer is formed in the first area and second area substrate surface；
Form first work-function layer on the gate dielectric layer surface of the covering first area and second area, institute
Stating the first work-function layer has first thickness；
The first work-function layer to the first area carries out reduction processing so that the first work(of first area
Function layer has second thickness；
First gate electrode layer is formed on the first work-function layer surface with second thickness；
The second gate electrode layer is formed on the first work-function layer surface of the second area.
2. forming method as claimed in claim 1, it is characterised in that carry out the technique step of the reduction processing
Suddenly include：Mask layer is formed on the first work-function layer surface of the second area；With the mask layer
It is mask, the first work-function layer to the first area carries out dry etch process；Covered described in removal
Film layer.
3. forming method as claimed in claim 1, it is characterised in that the first area is PMOS area；
The second area is PMOS area；The first threshold voltage adjusts the Doped ions of doping treatment
It is N-type ion；The material of first work-function layer is p-type work function material.
4. forming method as claimed in claim 3, it is characterised in that the first threshold voltage regulation doping
The Doped ions for the treatment of are P or As；The material of first work-function layer is Ta, TiN, TaSiN
Or one or more in TiSiN.
5. forming method as claimed in claim 1, it is characterised in that the first area is NMOS area；
The second area is NMOS area；The Doped ions of the threshold voltage adjustments doping treatment are P
Type ion；The material of first work-function layer is N-type work function material.
6. forming method as claimed in claim 5, it is characterised in that the threshold voltage adjustments doping treatment
Doped ions be B, Ga or In；The material of first work-function layer be TiAl, TiAlC, TaAlN,
One or more in TiAlN, MoN, TaCN or AlN.
7. forming method as claimed in claim 1, it is characterised in that the first thickness is 30 angstroms to 60
Angstrom；The second thickness is 15 angstroms to 30 angstroms.
8. forming method as claimed in claim 1, it is characterised in that the first area also includes several
Subregion, wherein, the substrate to some sub-regions is carried out at first threshold voltage regulation doping
Reason, and the first threshold voltage regulation doping treatment that is carried out to the substrate of some sub-regions mixes
Miscellaneous concentration is different.
9. forming method as claimed in claim 8, it is characterised in that some sub-regions include pull-up
Transistor area, input and output transistor area, standard threshold voltage region and low threshold region；
The second area is ultralow threshold value voltage regime；Or, some sub-regions include lower crystal pulling
Body area under control domain, input and output transistor area, transmission gate transistor area, standard threshold voltage region
And low threshold region；The second area is ultralow threshold value voltage regime.
10. forming method as claimed in claim 9, it is characterised in that some sub-regions substrate surfaces
Gate dielectric layer in, positioned at the thickness of the gate dielectric layer of the input and output transistor area substrate surface
It is most thick.
11. forming methods as claimed in claim 9, it is characterised in that the input and output transistor area
Gate dielectric layer includes oxide layer and the high-k gate dielectric layer positioned at oxidation layer surface；The first area
Gate dielectric layer outside middle input and output transistor area includes boundary layer and positioned at interface layer surfaces
High-k gate dielectric layer, wherein, the thickness of the thickness more than boundary layer of the oxide layer.
12. forming methods as claimed in claim 8, it is characterised in that to some height of the first area
The thickness thinning that first work-function layer in region carries out reduction processing is identical；Or, to firstth area
The thickness thinning that first work-function layer of some sub-regions in domain carries out reduction processing is differed.
13. forming methods as claimed in claim 1, it is characterised in that formed first work-function layer it
Before, form cap on the gate dielectric layer surface；Etching stop layer is formed in the block layer surface.
14. forming methods as claimed in claim 13, it is characterised in that the material of the cap is TiN；
The material of the etching stop layer is TaN.
15. forming methods as claimed in claim 1, it is characterised in that the substrate also include the 3rd region and
4th region, the 3rd region is identical with four-range area type, and the 3rd region, the 4th
Region is different from the area type of first area and second area；Also include step：To the 3rd area
The substrate in domain carries out second threshold voltage regulation doping treatment；The gate dielectric layer is also located at the 3rd region
And the 4th substrate areas surface；Form the second work-function layer of the covering gate dielectric layer, described the
Two work-function layers have the 3rd thickness；The second work-function layer to the 3rd region carries out reduction processing,
So that second work-function layer in the 3rd region has the 4th thickness；Have the second of the 4th thickness described
Work-function layer surface forms the 3rd gate electrode layer；In the second work-function layer of four-range surface shape
Into the 4th gate electrode layer.
16. forming methods as claimed in claim 15, it is characterised in that first work-function layer is also located at
Three regions and the 4th region, before second work-function layer is formed, removal be located at the 3rd region and
The work-function layer of four-range first；Second work-function layer is also located at first area and second area,
Before the first gate electrode layer is formed, removal is positioned at first area and the second work content of second area
Several layers.
17. forming methods as claimed in claim 15, it is characterised in that the first area and second area are
PMOS area；3rd region and the 4th region are NMOS area；Wherein, firstth area
Domain includes some sub-regions, and some sub-regions of first area include pulling up transistor region, the
One input and output transistor area, the first standard threshold voltage region and the first low threshold region；
The second area is the first ultralow threshold value voltage regime；3rd region includes some sub-regions,
Some sub-regions in the 3rd region include pull-down transistor region, the second input and output transistor
Region, transmission gate transistor area, the second standard threshold voltage region and the second low threshold region；
4th region is the second ultralow threshold value voltage regime.
18. forming methods as claimed in claim 17, it is characterised in that the material of first work-function layer is
P-type work function material；The material of second work-function layer is N-type work function material.
19. forming methods as claimed in claim 17, it is characterised in that to some height of the first area
The substrate in region carries out first threshold voltage regulation doping treatment, and several to the first area
The doping concentration of the first threshold voltage regulation doping treatment that the substrate of subregion is carried out is different；It is right
The substrate of some sub-regions in the 3rd region carries out second threshold voltage regulation doping treatment, and
The second threshold voltage regulation doping treatment carried out to the substrate of some sub-regions in the 3rd region
Doping concentration it is different.
20. forming methods as claimed in claim 1, it is characterised in that the substrate includes substrate and is located at
The discrete fin of substrate surface.
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| CN110120418A (en) * | 2019-05-07 | 2019-08-13 | 芯盟科技有限公司 | Vertical nanowire transistor and forming method thereof |
| CN112802898A (en) * | 2020-12-31 | 2021-05-14 | 泉芯集成电路制造(济南)有限公司 | Fin type field effect transistor and manufacturing method thereof |
| TWI741768B (en) * | 2019-09-05 | 2021-10-01 | 台灣積體電路製造股份有限公司 | Method of manufacturing semiconductor devices and semiconductor devices |
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| US20140363960A1 (en) * | 2013-06-05 | 2014-12-11 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
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| CN109427663A (en) * | 2017-08-22 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110120418A (en) * | 2019-05-07 | 2019-08-13 | 芯盟科技有限公司 | Vertical nanowire transistor and forming method thereof |
| CN110120418B (en) * | 2019-05-07 | 2023-03-24 | 芯盟科技有限公司 | Vertical nanowire transistor and method of forming the same |
| TWI741768B (en) * | 2019-09-05 | 2021-10-01 | 台灣積體電路製造股份有限公司 | Method of manufacturing semiconductor devices and semiconductor devices |
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| CN112802898A (en) * | 2020-12-31 | 2021-05-14 | 泉芯集成电路制造(济南)有限公司 | Fin type field effect transistor and manufacturing method thereof |
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