CN110120418A - Vertical nanowire transistor and forming method thereof - Google Patents

Vertical nanowire transistor and forming method thereof Download PDF

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CN110120418A
CN110120418A CN201910375145.2A CN201910375145A CN110120418A CN 110120418 A CN110120418 A CN 110120418A CN 201910375145 A CN201910375145 A CN 201910375145A CN 110120418 A CN110120418 A CN 110120418A
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CN110120418B (en
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周华
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ICLeague Technology Co Ltd
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Abstract

A kind of vertical nanowire transistor and forming method thereof.Forming method therein includes: offer substrate, the surface of the substrate has multiple channel columns, the multiple channel column is each perpendicular to the substrate surface, there is several first channel columns and several second channel columns in the multiple channel column, the first channel column and the second channel column are used to form the transistor of the first conduction type, there is the first channel region in the first channel column, and there is the second channel region in the second channel column；The first gate dielectric layer is formed in the sidewall surfaces of the first channel region of the first channel column；The second gate dielectric layer is formed in the sidewall surfaces of the second channel region of the second channel column；The first work content table structure is formed in the first grid dielectric layer surface；The second work content table structure is formed in the second gate dielectric layer surface, and the work function of the second work content table structure is different from the work function of the first work content table structure.Vertical nanowire transistor is formed by with multi-Vt.

Description

Vertical nanowire transistor and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of vertical nanowire transistor and its formation sides Method.
Background technique
With the rapid development of semiconductor processing technology, semiconductor devices is towards higher component density and higher The direction of integrated level is developed.Transistor is just being widely used at present as most basic semiconductor devices, therefore with semiconductor The raising of the component density and integrated level of device, the grid size of planar transistor is also shorter and shorter, traditional planar transistor It dies down to the control ability of channel current, generates short-channel effect, generate leakage current, the final electrical property for influencing semiconductor devices Energy.
In order to overcome the short-channel effect of transistor, inhibit leakage current, the prior art proposes a kind of vertical nano-wire crystal Pipe, such as all-around-gate vertical nanowire transistor.All-around-gate nano-wire transistor can preferably inhibit short-channel effect, Compared to having higher integrated level for two-dimensional surface transistor, and because its all-around-gate structure can effectively inhibit turning Effect, so that grid has preferable control ability, gate electrode preferably can form electrostatic control to channel region from multiple directions System.
However, the difficulty for forming multi-Vt transistor increases for vertical nanowire transistor.
Summary of the invention
Problems solved by the invention is to provide a kind of vertical nanowire transistor and forming method thereof, be used to form have it is more The vertical nanowire transistor of threshold voltage.
To solve the above problems, the present invention provides a kind of forming method of vertical nanowire transistor, comprising: provide lining The surface at bottom, the substrate has multiple channel columns, and the multiple channel column is each perpendicular to the substrate surface, the multiple ditch There is several first channel columns and several second channel columns, the first channel column and the second channel column are used to form the in road column The transistor of one conduction type, the first channel column is interior to have the first channel region, and has second in the second channel column Channel region；The first gate dielectric layer is formed in the sidewall surfaces of the first channel region of the first channel column；In second channel The sidewall surfaces of second channel region of column form the second gate dielectric layer；The first work function is formed in the first grid dielectric layer surface Structure；The second gate dielectric layer surface formed the second work content table structure, and the work function of the second work content table structure with The work function of first work content table structure is different；First grid layer is formed in the first work function body structure surface；Described second Work function body structure surface forms second grid layer.
Optionally, first conductivity type of transistor is P-type transistor；The first channel column is used to form the first P Transistor npn npn；The second channel column is used to form the second P-type transistor, and the threshold voltage of second P-type transistor is greater than The threshold voltage of first P-type transistor.
Optionally, the first work content table structure includes: the first work-function layer and positioned at the first work-function layer surface Second work-function layer；The second work content table structure includes the first work-function layer；The material of first work-function layer is p-type function Function material；The material of second work-function layer is p-type work function material.
Optionally, the material of first work-function layer and the material of the second work-function layer are identical or different；Described first The material of work-function layer is TiN or TaN；The material of second work-function layer is TiN or TaN.
Optionally, first work-function layer with a thickness of 8 angstroms~12 angstroms；Second work-function layer with a thickness of 13 angstroms ~18 angstroms.
Optionally, when the material of second work-function layer is TiN, the thickness of second work-function layer is every to increase 10 Angstrom, the threshold voltage of second P-type transistor increases 80 millivolts~120 millivolts compared with the threshold voltage of the first P-type transistor.
Optionally, the first work content table structure and the second work content table structure are single layer structure, first work function Structure is identical with the material of the second work content table structure, and the thickness of the first work content table structure is greater than the thickness of the second work content table structure Degree；The material of the first work content table structure and the second work content table structure is TiN or TaN.
Optionally, when the material of the first work content table structure and the material of the second work content table structure are TiN, described the The thickness of the thickness of two work content table structures the first work content table structure is every to increase 10 angstroms, the threshold of second N-type transistor Threshold voltage reduces by 80 millivolts~120 millivolts compared with the threshold voltage of the first N-type transistor.
Optionally, also there is several third channel columns and several 4th channel columns, the third in the multiple channel column Channel column and the 4th channel column are used to form the transistor of the second conduction type, have third channel in the third channel column Area, and there is the 4th channel region in the 4th channel column；The forming method further include: in the third of the third channel column The sidewall surfaces of channel region form third gate dielectric layer；The is formed in the sidewall surfaces of the 4th channel region of the 4th channel column Four gate dielectric layers；Third work content table structure is formed on third gate dielectric layer surface；In the 4th gate dielectric layer surface shape At the 4th work content table structure, and the work function of the 4th work content table structure is different from the work function of third work content table structure；? The third work function body structure surface forms third grid layer；The 4th grid layer is formed in the 4th work function body structure surface.
Optionally, second conductivity type of transistor is N-type transistor；The third channel column is used to form the first N Transistor npn npn；The 4th channel column is used to form the second N-type transistor, and the threshold voltage of second N-type transistor is greater than The threshold voltage of first N-type transistor.
Optionally, the 4th work content table structure includes: third work-function layer；The material of the third work-function layer is P Type work-function layer material.
Optionally, the first work content table structure includes: the first work-function layer, positioned at the second of the first work-function layer surface Work-function layer and third work-function layer positioned at the second work-function layer surface；The second work content table structure includes the first work content Several layers and the third work-function layer positioned at the first work-function layer surface；The material of first work-function layer is p-type work function Material；The material of second work-function layer is p-type work function material.
Optionally, the material of the third work-function layer is TiN or TaN；The third work-function layer with a thickness of 8 angstroms~ 12 angstroms.
Optionally, when the material of the third work-function layer is TiN, the thickness of the third work-function layer is every to increase 10 Angstrom, the threshold voltage of second N-type transistor increases 18 millivolts~22 millivolts compared with the threshold voltage of the first N-type transistor.
Optionally, the third work content table structure includes: the 4th work-function layer；The 4th work content table structure includes: position The 4th work-function layer in third work-function layer surface；The material of 4th work-function layer is N-type work function material；Institute Stating N-type work function material includes TiAl.
Optionally, first conductivity type of transistor is N-type transistor；The first channel column is used to form the first N Transistor npn npn；The second channel column is used to form the second N-type transistor, and the threshold voltage of second N-type transistor is greater than The threshold voltage of first N-type transistor.
Optionally, the first work content table structure includes: the first work-function layer and positioned at the first work-function layer surface Second work-function layer；The second work content table structure includes the first work-function layer.The material of first work-function layer is N-type function Function material；The material of second work-function layer is N-type work function material.
Optionally, the material of first work-function layer is TiAl；The material of second work-function layer is TiAl；It is described First work-function layer with a thickness of 8 angstroms~12 angstroms；Second work-function layer with a thickness of 13 angstroms~18 angstroms.
Optionally, when the material of second work-function layer is TiAl, the every increase of thickness of second work-function layer 10 angstroms, the threshold voltage of second N-type transistor increases 80 millivolts~120 millivolts compared with the threshold voltage of the first N-type transistor.
Optionally, also there is several third channel columns and several 4th channel columns, the third in the multiple channel column Channel column and the 4th channel column are used to form the transistor of the second conduction type, have third channel in the third channel column Area, and there is the 4th channel region in the 4th channel column；The forming method further include: in the third of the third channel column The sidewall surfaces of channel region form third gate dielectric layer；The is formed in the sidewall surfaces of the 4th channel region of the 4th channel column Four gate dielectric layers；Third work content table structure is formed on third gate dielectric layer surface；In the 4th gate dielectric layer surface shape At the 4th work content table structure, and the work function of the 4th work content table structure is different from the work function of third work content table structure；? The third work function body structure surface forms third grid layer；The 4th grid layer is formed in the 4th work function body structure surface.
Optionally, second conductivity type of transistor is P-type transistor；The third channel column is used to form the first P Transistor npn npn；The 4th channel column is used to form the second P-type transistor, the threshold voltage of second P-type transistor and The threshold voltage of one P-type transistor is different.
Optionally, before forming the third gate dielectric layer and the 4th gate dielectric layer, further includes: in the third channel It is respectively formed third doped region in column and in the 4th channel column, the third doped region is located at third channel region bottom With the 4th channel region bottom；The 4th doped region is respectively formed in the third channel column and in the 4th channel column, the described 4th Doped region is located at the top of the third channel region and at the top of the 4th channel region, the third doped region and the 4th doped region Conduction type is identical.
Optionally, before forming first gate dielectric layer and the second gate dielectric layer, further includes: in first channel It is respectively formed the first doped region in column and in the second channel column, first doped region is located at first channel region bottom With the second channel region bottom；The second doped region is respectively formed in the first channel column and in the second channel column, described second Doped region is located at the top of first channel region and at the top of the second channel region, first doped region and the second doped region Conduction type is identical.
Optionally, the forming method of first doped region include: over the substrate, the side wall of the multiple channel column Surface forms the first mask layer, and first mask layer exposes the partial sidewall surface of first channel column bottom, and institute State the partial sidewall surface that the first mask layer exposes second channel column bottom；Using first mask layer as exposure mask, It adulterates in the first channel column and in the second channel column and forms the first doped region.
Optionally, the forming method of second doped region includes: to form the second mask layer over the substrate, and described Two mask layers expose the top surface of the first channel column and the top surface of the second channel column；It is covered with described second Film layer is exposure mask, and doping forms the second doped region in the first channel column and in the second channel column.
Optionally, before forming the first gate dielectric layer and the second gate dielectric layer, further includes: form the over the substrate One dielectric layer, the first medium layer surround the multiple channel column；In the first conductive layer of the first medium layer surface, institute It states the first conductive layer and surrounds the multiple channel column, and first conductive layer is located at the first doped region sidewall surfaces；? First conductive layer surface forms second dielectric layer；First gate dielectric layer is also located at the second medium layer surface；Institute It states the second gate dielectric layer and is also located at the second medium layer surface.
Optionally, before forming the first gate dielectric layer and the second gate dielectric layer, further includes: in the second dielectric layer table Face forms sacrificial layer, and the surface of the sacrificial layer is lower than the top surface of the multiple channel column, described in the sacrificial layer surrounds Multiple channel columns, and the sacrificial layer is located at the side wall of first channel region and the side wall of second channel region；Institute It states sacrificial layer surface and forms third dielectric layer, the third dielectric layer surrounds the multiple channel column, third dielectric layer position In the sidewall surfaces that the multiple channel column exposes, and the third dielectric layer exposes the part sacrificial layer；Removal institute Sacrificial layer is stated, is formed between the third dielectric layer and second dielectric layer and exposes gate openings, the gate openings exposure The side wall of the side wall of first channel region and second channel region out；In the first channel that the gate openings expose The sidewall surfaces in area form first gate dielectric layer and are located at；In the side wall table for the second channel region that the gate openings expose Face forms second gate dielectric layer and is located at.
Optionally, further includes: the 4th dielectric layer is formed in the first grid layer surface and second grid layer surface, it is described 4th dielectric layer is also located at the sidewall surfaces of the third dielectric layer.
Optionally, further includes: before forming the first work content table structure and the second work content table structure, described first Gate dielectric layer and second gate dielectric layer surface form barrier layer.
Optionally, further includes: form stop-layer in the barrier layer surface.
Optionally, the material of the stop-layer is different with the material of the first work function body structure surface contacted, and described The material of stop-layer is different with the material of the second work function body structure surface contacted.
Optionally, the material of the stop-layer is TaN.
Optionally, the material on the barrier layer is TiN or TaN.
Optionally, before forming first grid layer, the first coating is formed in the first work function body structure surface；? It is formed before second grid layer, forms the second coating in the second work function body structure surface.
Optionally, the material of first coating includes TaN or TiN；The material of second coating include TaN or TiN。
The forming method of vertical nanowire transistor as described in claim 1, which is characterized in that the week of the channel column A length of 30 nanometers~40 nanometers.
Optionally, size of the first grid layer on the direction perpendicular to substrate surface is 28 nanometers~32 nanometers； Size of the second grid layer on the direction perpendicular to substrate surface is 28 nanometers~32 nanometers.
Optionally, the material of first gate dielectric layer and the second gate dielectric layer includes high K dielectric material；The first grid The material of pole layer and second grid layer includes metal.
Correspondingly, being formed by vertical nanowire transistor using the above method the present invention also provides a kind of, comprising: lining The surface at bottom, the substrate has multiple channel columns, and the multiple channel column is each perpendicular to the substrate surface, the multiple ditch There is several first channel columns and several second channel columns, the first channel column and the second channel column are used to form the in road column The transistor of one conduction type, the first channel column is interior to have the first channel region, and has second in the second channel column Channel region；Positioned at the first gate dielectric layer of the sidewall surfaces of the first channel region of the first channel column；Positioned at second ditch Second gate dielectric layer of the sidewall surfaces of the second channel region of road column；Positioned at the first work function of the first grid dielectric layer surface Structure；Positioned at the second work content table structure of the second gate dielectric layer surface, and the work function of the second work content table structure with The work function of first work content table structure is different；Positioned at the first grid layer of the first work function body structure surface；Positioned at described The second grid layer of two work function body structure surfaces.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method of technical solution of the present invention, the first channel column and the second channel column are used to form the first conduction type Transistor forms the second work content in the second channel column side wall by the first work content table structure formed in the first channel column side wall Table structure, and the first work content table structure is different from the work function of the second work content table structure, makes the first channel cylindricality with this At the first conductivity type of transistor threshold voltage and the second channel column formed the first conductivity type of transistor threshold value electricity Pressure is different.To can be formed to the first channel column by the material or thickness that adjust the first work content table structure first The threshold voltage of conductivity type of transistor is adjusted；Correspondingly, passing through the material or thickness that adjust the second work content table structure The threshold voltage for the first conductivity type of transistor that degree can be formed the second channel column is adjusted.Therefore, multi-threshold is formed The technology difficulty of the vertical nanowire transistor of voltage declines.
In the structure of technical solution of the present invention, by the work content for making the first work content table structure Yu the second work content table structure Number is different.Specifically, the material or thickness by adjusting the first work content table structure the first channel column can be formed the The threshold voltage of one conductivity type of transistor is adjusted；Correspondingly, material by adjusting the second work content table structure or The threshold voltage for the first conductivity type of transistor that thickness can be formed the second channel column is adjusted.Therefore, can be made The first conduction type crystal that the threshold voltage and the second channel column for the first conductivity type of transistor that one channel column is formed are formed The threshold voltage of pipe is different.
Detailed description of the invention
Fig. 1 to Figure 13 is the schematic diagram of the section structure of the forming process of the vertical nanowire transistor of the embodiment of the present invention；
Figure 14 to Figure 22 is that the cross-section structure of the forming process of the vertical nanowire transistor of another embodiment of the application shows It is intended to.
Specific embodiment
As stated in the background art, the prior art formed have multi-Vt vertical nanowire transistor difficulty compared with Greatly.
It finds after study, it, can be by crystal in the embodiment of planar transistor or fin formula field effect transistor The channel region of pipe carries out ion implanting to realize the threshold voltage adjustments of transistor.However, for vertical nanowire transistor For, since the orientation in transistor is perpendicular to substrate surface, traditional use ion implantation technology is caused to adjust The difficulty of threshold voltage is larger, it is difficult to realize to be parallel to channel region of the direction to vertical nanowire transistor of substrate surface Carry out ion implanting.
To solve the above-mentioned problems, the present invention provides a kind of vertical nanowire transistor.By in the first channel column side wall The first work-function layer is formed, forms the second work-function layer, and the work content of the second work content table structure in the second channel column side wall Number is different from the work function of the first work content table structure, so as to form the crystal of the first conduction type with different threshold voltages Pipe.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.
Specification is needed, in embodiments of the present invention, so-called " surface " is used to show the position between different structure Relationship does not need directly to contact between limiting structure.
Fig. 1 to Figure 13 is the schematic diagram of the section structure of the forming process of the vertical nanowire transistor of the embodiment of the present invention.
Fig. 1 and Fig. 2 are please referred to, Fig. 2 is the schematic diagram of the section structure of the Fig. 1 along the direction AA ', provides substrate 100, the substrate 100 surface has multiple channel columns 110, and the multiple channel column 110 is each perpendicular to 100 surface of substrate, the multiple There is several first channel columns 111 and several second channel columns 112, the first channel column 111 and the second ditch in channel column 110 Road column 112 is used to form the transistor of the first conduction type, has the first channel region 121, and institute in the first channel column 111 Stating in the second channel column 112 has the second channel region 122.
The multiple channel column 110 is used for vertical nanowire transistor, the channel length of the vertical nanowire transistor Direction is perpendicular to the substrate surface, to reduce each transistor the space occupied area, so as to improve the integrated of transistor Degree.
In the present embodiment, the forming method of the substrate 110 and channel column 111 includes: offer initial substrate；Described Initial substrate surface forms several the first mutually discrete patterned layers 101, and first patterned layer 101 defines described more The corresponding position and shape of a channel column 110；It is exposure mask with first patterned layer 101, etches the initial substrate, is formed The substrate 100 and multiple channel columns 110 positioned at 100 surface of substrate.
The initial substrate is planar substrates；The initial substrate is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, insulation Silicon (SOI) substrate on body, germanium on insulator (GOI) substrate, glass substrate or III-V compound substrate (such as silicon nitride or GaAs etc.).
The technique for etching the initial substrate is anisotropic dry etch process.
In the present embodiment, first patterned layer 101 is single layer structure；The material of first patterned layer 101 For silicon nitride；In other embodiments, the material of the first patterned layer 101 of the single layer structure can also be silica, nitrogen Silica, agraphitic carbon or silicon carbide.
In another embodiment, first patterned layer 101 is laminated construction, and the stacking direction of the laminated construction Perpendicular to 100 surface of substrate；The material of the stepped construction includes silica, silicon oxynitride, agraphitic carbon and silicon carbide One of or multiple combinations.
The forming method of first patterned layer 101 includes: to form initial first figure in the initial substrate surface Change layer 101；Patterned photoresist layer is formed on 101 surface of the first patterned layer, the patterned photoresist layer defines The corresponding position and shape of the multiple channel column；Using the patterned photoresist layer as exposure mask, etching described initial first Patterned layer forms first patterned layer up to exposing the initial substrate surface.
The technique for etching initial first patterned layer is anisotropic dry etch process.
In other embodiments, first patterned layer can also be patterned photoresist layer.
In the present embodiment, first conductivity type of transistor is P-type transistor；The first channel column 111 is used for Form the first P-type transistor；The second channel column 112 is used to form the second P-type transistor, second P-type transistor Threshold voltage is greater than the threshold voltage of the first P-type transistor.
The quantity of the first channel column 111 is one or more；The quantity of the second channel column 112 is 1 or more It is a.
In another embodiment, first conductivity type of transistor is N-type transistor；The first channel column 111 is used In forming the first N-type transistor；The second channel column 112 is used to form the second N-type transistor, second N-type transistor Threshold voltage be greater than the first N-type transistor threshold voltage.
30 nanometers~40 nanometers of the Zhou Changwei of each channel column 110.The perimeter of the channel column 110, which determines, to be formed by The channel width (channel width) of vertical nanowire transistor.And the channel width determines vertical nano-wire crystal The channel current size of pipe；On the one hand, the perimeter should not be too large, and the area that otherwise will lead to the channel column occupancy is excessive, It is not easy to the microminaturization of device and integrated；On the other hand, the Zhou Changyou is unsuitable too small, otherwise will lead to vertical nano-wire The channel width of transistor is too small, then the channel current of vertical nanowire transistor is too small, then be easy to cause under the performance of device Drop, and it is formed by the problems such as transistor is easy to happen short-channel effect or electric leakage.
In the present embodiment, the channel column 110 is cylindrical body, and 110 top dimension of channel column is less than bottom ruler It is very little；The peripheral extent at 111 top of channel column is 30 nanometers~35 nanometers, and the diameter range at 111 top of channel column is received for 10 Rice~12 nanometers；35 nanometers~40 nanometers of the Zhou Changwei of 111 bottom of channel column, the diameter model of 111 bottom of channel column Enclose is 11 nanometers~14 nanometers.
In another embodiment, 110 top dimension of channel column is identical as bottom size, the week of the channel column 111 A length of 35 nanometers~40 nanometers, the diameter range of the channel column 111 is 11 nanometers~14 nanometers.
It in the present embodiment, further include the substrate 100 around channel column 110 before being subsequently formed first medium layer Well region (not shown) is formed in interior and 110 bottom of channel column substrate 100.By the first channel column 111 in this present embodiment It is used to form P-type transistor with the second channel column 112, then in the substrate 100 around the first channel column 111, second Well region in substrate 100 around channel column 112 and in the substrate 100 of 112 bottom of the first channel column 111 and the second channel column For N-type.
The formation process of the well region is ion implantation technology.
It in one embodiment, further include the side wall in the substrate surface, channel column 110 before forming the well region And protective layer is formed on the top of channel column.It is described protective layer used to be protected in during forming the ion implantation technology of the well region Protect substrate 100 and channel column 110.The protective layer is single layer structure or laminated construction；The material of the protective layer be silica, One of silicon nitride and silicon oxynitride or a variety of stackings.
Referring to FIG. 3, Fig. 3 is consistent with the profile direction of Fig. 2, first medium layer 102, institute are formed on the substrate 100 It states first medium layer 102 and surrounds the multiple channel column 110；After forming the first medium layer 102, in first ditch The first doped region 104 is respectively formed in road column 111 and in the second channel column 112, first doped region 104 is located at described 122 bottom of first channel region, 121 bottom and the second channel region.
The first medium layer 102 be used between the first conductive layer and the substrate 100 being subsequently formed carry out electricity every From.The material of the first medium layer 102 includes silica, silica, silicon oxynitride, (dielectric constant is less than low k dielectric materials And one of ultra-low k dielectric material (dielectric constant is less than 2.5) or multiple combinations 3.9).
First doped region 104 is used to be formed by the first conduction as the first channel column 111 and the second channel column 112 The source electrode of the transistor of type or drain electrode.In the present embodiment, first doped region 104 is used for as drain electrode.
In the present embodiment, first conductivity type of transistor is P-type transistor, then in first doped region 104 Doped ions be P-type ion；The P-type ion includes boron ion or indium ion.In other embodiments, described first is conductive Type of transistor is N-type transistor, then the Doped ions in first doped region 104 are N-type ion, the N-type ion packet Include phosphonium ion or arsenic ion.
In the present embodiment, the forming method of first doped region 104 include: on the substrate 100, it is the multiple The sidewall surfaces of channel column 110 form the first mask layer 103, and first mask layer 103 exposes the first channel column 111 The partial sidewall surface of bottom, and first mask layer 103 exposes the partial sidewall table of 112 bottom of the second channel column Face；On the substrate 100, the sidewall surfaces of the multiple channel column 110 the first mask layer 103 of formation, first exposure mask The partial sidewall surface that layer 103 exposes 111 bottom of the first channel column, and first mask layer 103 expose it is described The partial sidewall surface of second channel column, 112 bottom；It is exposure mask with first mask layer 103, in the first channel column 111 Doping forms the first doped region in interior and the second channel column 112.
In the present embodiment, the forming method of first mask layer 103 include: before forming first medium layer 102, Initial first mask layer is formed in the side wall and top of 100 surface of substrate and channel column 110；It is covered described initial first Film surface forms initial first medium layer, and the surface of the initial first medium layer is lower than the top of the channel column 110；? The second graphical layer for being located at 110 side wall of channel column and top, the second graphical are formed on the initial first medium layer Layer is located at the initial first exposure mask layer surface；The initial first medium layer is thinned, forms the first medium layer 102, and Between the first medium layer 102 and the second graphical layer, initial first mask layer in part is exposed；With second figure Shape layer and first medium layer 102 are exposure mask, etch initial first mask layer until exposing the multiple channel column 110 Sidewall surfaces, form first mask layer 103；After forming first mask layer 103, the second graph is removed Change layer.
The material of first mask layer 103 includes: one of silica, silicon nitride and silicon oxynitride or a variety of groups It closes.In the present embodiment, first mask layer 103 includes positioned at the silicon oxide layer on 110 surface of channel column and positioned at oxidation The silicon nitride layer of silicon surface.The formation process of initial first mask layer 103 is chemical vapor deposition process or atomic layer Depositing operation.
The forming method of the initial first medium layer includes: to form first medium in the initial first exposure mask layer surface Material membrane, the surface of the first medium material membrane are higher than the top of the channel column 110；Planarizing the first medium material After expecting film, it is etched back to the first medium material membrane, forms the initial first medium layer.
The technique that the initial first medium layer is thinned is anisotropic dry etch process, isotropic dry method quarter Etching technique or wet-etching technology.
In the first channel column 111 and the second channel column 112 in doping formed the first doped region technique include from Sub- injection technology or solid-source doping technique.
In the present embodiment, first doped region 104 includes the first lightly doped district and the first source and drain doping area；First is light Doping concentration in doped region is less than the doping concentration in the first source and drain doping area.
Referring to FIG. 4, the first conductive layer 105 on 102 surface of first medium layer, first conductive layer 102 is wrapped The multiple channel column 110 is enclosed, and first conductive layer 105 is located at 104 sidewall surfaces of the first doped region.
First conductive layer 105 with the first doped region 104 for being electrically connected.The material of first conductive layer includes gold Belong to；The material of first conductive layer includes one of copper, tungsten, aluminium, titanium nitride or tantalum nitride or multiple combinations.
In the present embodiment, first conductive layer 105 includes being located at 110 side wall of channel column and first medium layer First barrier layer on 102 surfaces and the first conductive material layer positioned at the first barrier layer surface.The material on first barrier layer Material is that one or both of titanium nitride and tantalum nitride combine；The material of first conductive material layer is copper, tungsten or aluminium.
The forming method of first conductive layer 105 includes: in 102 surface of first medium layer and channel column 110 Side wall and top formed the first barrier material film；The first conductive material membrane is formed in the first barrier material film surface；It carves Etching off removes the first conductive material membrane and the first barrier material film of 110 side wall of channel column and top, forms described first and leads Material layer and the first barrier layer.
Referring to FIG. 5, forming second dielectric layer 106 on 105 surface of the first conductive layer；In the second dielectric layer 106 surfaces form sacrificial layer 107, and the surface of the sacrificial layer 107 is lower than the top surface of the multiple channel column 110, described Sacrificial layer 107 surrounds the multiple channel column 110 (as shown in Figure 1), and the sacrificial layer 107 is located at first channel region The side wall of 121 side wall and second channel region 122；Initial third dielectric layer is formed on 107 surface of sacrificial layer 108, the initial third dielectric layer 108 surrounds the multiple channel column 110.
The second dielectric layer 106 is used to carry out electricity between the first grid layer being subsequently formed and the first conductive layer 105 Isolation.The material of the second dielectric layer 106 includes silica, silica, silicon oxynitride, (dielectric constant is small for low k dielectric materials 3.9) and one of ultra-low k dielectric material (dielectric constant is less than 2.5) or multiple combinations in.The second dielectric layer 106 Formation process includes being etched back to technique after flatening process and flatening process after depositing operation, depositing operation.
The sacrificial layer 107 for taking up space position for the first grid layer that is subsequently formed and second grid layer, and And the position for defining the initial third dielectric layer 108 being subsequently formed.The material and the second medium of the sacrificial layer 107 The material of layer 106 or the initial third dielectric layer 108 being subsequently formed is different.The material of the sacrificial layer 107 includes silica, oxygen (dielectric constant is small for SiClx, silicon oxynitride, agraphitic carbon, low k dielectric materials (dielectric constant is less than 3.9) and ultra-low k dielectric material One of 2.5) or multiple combinations in.The formation process of the sacrificial layer 107 includes flat after depositing operation, depositing operation Technique is etched back to after smooth chemical industry skill and flatening process.
The material of the initial third dielectric layer 108 includes silica, silica, silicon oxynitride, low k dielectric materials (Jie 3.9) and one of ultra-low k dielectric material (dielectric constant is less than 2.5) or multiple combinations electric constant is less than.The initial third After the formation process of dielectric layer 108 includes flatening process and flatening process after depositing operation, depositing operation It is etched back to technique.
In the present embodiment, after forming the initial third dielectric layer 108, etching removes first patterned layer 101。
Referring to FIG. 6, after forming the initial third dielectric layer 108, in the first channel column 111 and second The second doped region 109 is respectively formed in channel column 112, second doped region 109 is located at first channel region 121 and pushes up 122 top of portion and the second channel region, first doped region 104 are identical with the conduction type of the second doped region 109.
Second doped region 109 is used to be formed by the first conduction as the first channel column 111 and the second channel column 112 The source electrode of the transistor of type or drain electrode.In the present embodiment, second doped region 109 is used to be used as source electrode.
In the present embodiment, first conductivity type of transistor is P-type transistor, then in second doped region 109 Doped ions be P-type ion；The P-type ion includes boron ion or indium ion.In other embodiments, described first is conductive Type of transistor is N-type transistor, then the Doped ions in second doped region 109 are N-type ion, the N-type ion packet Include phosphonium ion or arsenic ion.
The forming method of second doped region 109 includes: that the second mask layer 113 is formed on the substrate 100, described Second mask layer 113 exposes the top surface of the first channel column 111 and the top surface of the second channel column 112； It is exposure mask with second mask layer 113, doping forms second in the first channel column 121 and in the second channel column 122 Doped region 109.
In the present embodiment, the technique for forming second doped region 109 is ion implantation technology.
In the present embodiment, second doped region 109 includes the second lightly doped district and the second source and drain doping area；Second is light Doping concentration in doped region is less than the doping concentration in the second source and drain doping area.
In the present embodiment, second mask layer 113 is located at initial 108 surface of third dielectric layer.
The forming method of second mask layer 113 includes: in initial 108 surface of third dielectric layer and the ditch The top surface of road column 110 forms initial second mask layer；Part initial second mask layer is removed, and exposes described the One channel column, 111 top surface and 112 top surface of the second channel column form second mask layer 113.
The material of second mask layer 113 includes one of silica, silicon nitride and silicon oxynitride or multiple combinations.
It further include removal second mask layer 113 after forming second doped region 109.
Referring to FIG. 7, after forming second doped region 109, the initial third dielectric layer 108 in removal part and exposure The part sacrificial layer 107 out forms the third dielectric layer 114 for being located at the sidewall surfaces that the multiple channel column 110 exposes.
The third dielectric layer 114 determines be subsequently formed perpendicular to the size in the channel column sidewall surfaces direction The gate height (gate height) of one grid layer and second grid layer.
The forming method of the third dielectric layer 114 includes: in initial third dielectric layer 108 (as shown in Figure 6) table Face forms several third patterned layers, and each third patterned layer is located at the top surface and the channel column of a channel column 110 Initial 108 surface of third dielectric layer in part around 110；Using the patterned layer as exposure mask, the initial third medium is etched Layer 108, until exposing 107 surface of sacrificial layer, forms the third dielectric layer 114.
The material of the third patterned layer include one of silica, silicon nitride, silicon oxynitride Other substrate materials or Multiple combinations.
Referring to FIG. 8, the sacrificial layer 107 (as shown in Figure 7) is removed, in the third dielectric layer 114 and second medium Formed between layer 106 and expose gate openings 115, the gate openings 115 expose the side wall of first channel region 121 with And the side wall of second channel region 122.
The technique for removing the sacrificial layer 107 includes isotropic dry etch process or wet-etching technology.
The gate openings 115 are used to form gate structure.
Referring to FIG. 9, the sidewall surfaces in the first channel region 121 of the first channel column 111 form the first gate medium Layer 116；The second gate dielectric layer 117 is formed in the sidewall surfaces of the second channel region 122 of the second channel column 112.
In the present embodiment, first gate dielectric layer 116 and the second gate dielectric layer 117 are formed simultaneously.The first grid Dielectric layer 116 is also located at 106 surface of second dielectric layer；Second gate dielectric layer 117 is also located at the second dielectric layer 106 surfaces；First gate dielectric layer 116 and the second gate dielectric layer 117 are also located at 114 surface of third dielectric layer.
First gate dielectric layer is formed in the sidewall surfaces for the first channel region 121 that the gate openings 115 expose 116；Second gate dielectric layer 117 is formed in the sidewall surfaces for the second channel region 122 that the gate openings 115 expose.
The material of first gate dielectric layer 116 is high K medium material (dielectric constant is greater than 3.9)；Second gate dielectric layer 117 material is high K medium material.The high K medium material includes La2O3、Al2O3、BaZrO、HfZrO4、HfZrON、 HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3Or Si3N4.First gate dielectric layer 116 and second gate dielectric layer 117 with a thickness ofFirst gate dielectric layer 116 and the second gate dielectric layer 117 Formation process includes chemical vapor deposition process, physical gas-phase deposition or atom layer deposition process.
In the present embodiment, before forming first gate dielectric layer 116 and the second gate dielectric layer 117, further include The sidewall surfaces for the first channel region 121 that the gate openings 115 expose and the sidewall surfaces of the second channel region 122 form oxygen Change layer；First gate dielectric layer 116 and the second gate dielectric layer 117 are located at the oxidation layer surface.
Figure 10 and Figure 11 are please referred to, Figure 11 is the enlarged fragmentary cross section of region A and region B in Figure 10, described first 116 surface of gate dielectric layer forms the first work content table structure 118；The second work function is formed on 117 surface of the second gate dielectric layer Structure 119, and the work function of the second work content table structure 119 is different from the work function of the first work content table structure 118.
In the present embodiment, the first kind transistor is P-type transistor.The first work content table structure 118 includes: First work-function layer 131 and the second work-function layer 132 positioned at 131 surface of the first work-function layer；The second work function knot Structure 119 includes the first work-function layer 131；The material of first work-function layer 131 is p-type work function material；Second function The material of function layer 132 is p-type work function material.
The material of first work-function layer 131 and the material of the second work-function layer 132 are identical or different；First function The material of function layer 131 is TiN or TaN；The material of second work-function layer 132 is TiN or TaN.First work function The formation process of layer 131 and the second work-function layer 132 includes atom layer deposition process；The atom layer deposition process has good Gradient coating performance, be conducive to form the first work-function layer 131 and the second work function in homogeneous thickness in gate openings 115 Layer 132.
In one embodiment, the formation process of first work-function layer 131 or the second work-function layer 132 can also include Doping process；The doping process includes ion implantation technology or solid-source doping technique；The doping process is used for first Doping work function adjusts ion in work-function layer 131 or the second work-function layer 132, and it includes p-type function that the work function, which adjusts ion, Function ion (such as Ti ion or Ta ion) or N-type work function ion (such as Al ion).
Since the TiN or TaN are p-type work function material, and the overall thickness of the first work content table structure 118 is greater than second The overall thickness of work content table structure 119, then the threshold voltage of first P-type transistor is electric less than the threshold value of the second P-type transistor Pressure.
In the present embodiment, the material of first work-function layer 131 and the second work-function layer 132 is TiN, then described The threshold voltage of first P-type transistor and the second P-type transistor is by adjusting first work-function layer 131 and the second work function The thickness of layer 132 is adjusted.In other embodiments, the material of first work-function layer 131 and the second work-function layer 132 It can also be different.
Since first work-function layer 131 is identical with the material of the second work function 132, then first work-function layer 131 and second work-function layer 132 can be formed using identical formation process.In the vertical nanowire transistor of required formation In the case that size reduction and integrated level improve, the thickness of the first work-function layer 131 and the second work-function layer 132 is easier to control System, it is simpler in the method for this threshold voltage for adjusting the first P-type transistor and the second P-type transistor, and for threshold voltage Control it is more accurate.
Specifically, the thickness of second work-function layer is every to increase 10 when the material of second work-function layer is TiN Angstrom, the threshold voltage of second P-type transistor increases 80 millivolts~120 millivolts compared with the threshold voltage of the first P-type transistor.
In the present embodiment, the thickness range of first work-function layer 131 is 8 angstroms~12 angstroms；Second work function The thickness range of layer 132 is 13 angstroms~18 angstroms.
In the present embodiment, the forming method of the first work content table structure and the second work content table structure includes: described First gate dielectric layer, 116 surface, 117 surface of the second gate dielectric layer form the first work-function layer 131；In first work-function layer 131 surfaces form initial second work-function layer；The 4th patterned layer is formed on the initial second work-function layer surface, described the Four patterned layers expose initial second work-function layer at 112 side wall of the second channel column and top；With the 4th patterned layer For initial second work-function layer described in mask etching until exposing the first work-function layer 131, second work-function layer is formed 132。
In another embodiment, the first work content table structure and the second work content table structure are single layer structure, and described One work content table structure is identical with the material of the second work content table structure, and the thickness of the first work content table structure is greater than the second work function knot The thickness of structure；The material of the first work content table structure and the second work content table structure is TiN or TaN.The first work function knot The thickness range of structure is 8 angstroms~28 angstroms；The thickness range of the second work content table structure is 8 angstroms~28 angstroms.
When the material of the first work content table structure and the material of the second work content table structure are TiN, second work content The thickness of the thickness of table structure the first work content table structure is every to increase 10 angstroms, the threshold voltage of second N-type transistor Threshold voltage compared with the first N-type transistor reduces by 18 millivolts~22 millivolts, is in one embodiment 20 millivolts.
The formation process of first work content table structure and the second work content table structure includes atom layer deposition process；The atomic layer Depositing operation has good gradient coating performance, is conducive to form the first work function in homogeneous thickness in gate openings 115 Structure and the second work content table structure.
The formation process of the first work content table structure and the second work content table structure can also include doping process；It is described to mix General labourer's skill includes ion implantation technology or solid-source doping technique；The doping process is used for the first work content table structure and second Doping work function adjusts ion in work content table structure.
In other embodiments, the first work content table structure is different with the material of the second work content table structure, and the first function The thickness of function structure and the thickness of the second work content table structure are identical or different.
In another embodiment, the first kind transistor is N-type transistor.The first work content table structure includes: First work-function layer and the second work-function layer positioned at the first work-function layer surface；The second work content table structure includes first Work-function layer.The material of first work-function layer is N-type work function material；The material of second work-function layer is N-type function Function material.
In one embodiment, the material of first work-function layer is TiAl；The material of second work-function layer is TiAl；First work-function layer with a thickness of 8 angstroms~12 angstroms；Second work-function layer with a thickness of 13 angstroms~18 angstroms.
When the material of second work-function layer is TiAl, the thickness of second work-function layer is every to increase 10 angstroms, institute The threshold voltage for stating the second N-type transistor reduces by 80 millivolts~120 millivolts compared with the threshold voltage of the first N-type transistor.
The formation process of first work-function layer and the second work-function layer includes atom layer deposition process.First function The formation process of function layer or the second work-function layer can also include doping process；The doping process includes ion implantation technology Or solid-source doping technique；The doping process is used to adulterate work function into the first work-function layer or the second work-function layer and adjust Ion.
In other embodiments, when the first kind transistor be N-type transistor when, the first work content table structure and The equal material of second work content table structure can also be different, and the thickness of the thickness of the first work content table structure and the second work content table structure It is identical or different.
In the present embodiment, before forming the first work content table structure 118 and the second work content table structure 119, also exist First gate dielectric layer and second gate dielectric layer surface form barrier layer 133；Stop-layer is formed on 133 surface of barrier layer 134。
The material of the stop-layer 134 is different with 118 material of the first work content table structure contacted, and the stop-layer 134 is different with 119 material of the second work content table structure contacted.The material of the stop-layer is TaN；The material on the barrier layer For TiN or TaN.The formation process on the barrier layer 133 includes atom layer deposition process；The formation process of the stop-layer includes Atom layer deposition process.
In other embodiments, additionally it is possible to not form the stop-layer.
Figure 12 is please referred to, forms first grid layer 123 on 118 surface of the first work content table structure；In second function 119 surface of function structure forms second grid layer 124.
In the present embodiment, the first grid layer 123 and second grid layer 124 are formed simultaneously；The first grid layer Material with second grid layer includes metal；The metal includes one of copper, tungsten and aluminium or a variety of.
In the present embodiment, size of the first grid layer 123 on the direction perpendicular to substrate surface is 28 nanometers ~32 nanometers；Size of the second grid layer 124 on the direction perpendicular to substrate surface is 28 nanometers~32 nanometers.
Size of the first grid layer 123 on the direction perpendicular to 100 surface of substrate is in conjunction with the first channel column 111 perimeter determines the channel area of first P-type transistor, and the channel area is in conjunction with first work function The thickness of structure 118 determines that the first work content table structure 118 for the control ability of channel carriers, and then determines The threshold voltage size of first P-type transistor.Therefore, in conjunction with the regulation first grid layer 123 perpendicular to 100 table of substrate Size, the perimeter of the first channel column 111 and the thickness of the first work content table structure 118 on the direction in face, can be to The threshold voltage of one P-type transistor carries out accuracy controlling.
Specifically, on the one hand, size of the first grid layer 123 on the direction perpendicular to 100 surface of substrate is unsuitable It is excessive, otherwise channel resistance will be caused to increase, and be unfavorable for improving carrier mobility；On the other hand, the first grid layer 123 Size on the direction perpendicular to 100 surface of substrate is unsuitable too small, otherwise easily causes short-channel effect.
Correspondingly, in conjunction with size on the direction perpendicular to 100 surface of substrate of the second grid layer 124, institute is regulated and controled State the perimeter of the second channel column 112 and the thickness of the second work content table structure 119, can to the second P-type transistor threshold value electricity Pressure carries out accuracy controlling.
In the present embodiment, before forming first grid layer 123, also it is being formed in the first work function body structure surface Form the first coating (not shown)；Before forming second grid layer 124, the is formed in the second work function body structure surface Two coatings (not shown).First coating is for stopping the material of first grid layer 123 into the first gate dielectric layer 116 Diffusion；Second coating is for stopping the material of second grid layer 124 to spread into the second gate dielectric layer 117.
The material of first coating includes TaN or TiN；The material of second coating includes TaN or TiN.? In the present embodiment, the material of first coating and the second coating is identical, and first coating and the second coating It is formed simultaneously；The formation process of first coating and the second coating includes atom layer deposition process.
Figure 13 is please referred to, forms the 4th dielectric layer on 123 surface of first grid layer and 124 surface of second grid layer 125, the 4th dielectric layer 125 is also located at the sidewall surfaces of the third dielectric layer 114.
4th dielectric layer 125 be used for the second conductive layer (not shown) for being subsequently formed and first grid layer 123, with And second be electrically isolated between conductive layer and second grid layer 124.The material of 4th dielectric layer 125 include silica, Silica, silicon oxynitride, low k dielectric materials (dielectric constant is less than 3.9) and ultra-low k dielectric material (dielectric constant is less than 2.5) One of or multiple combinations.
The forming method of 4th dielectric layer 125 includes: on 123 surface of first grid layer, second grid layer 124, the 4th dielectric material film, the surface of the 4th dielectric material film are formed on the top of third dielectric layer 114 and channel column 111 Higher than the top of the channel column 110；After planarizing the 4th dielectric material film, it is etched back to the 4th dielectric material Film forms initial 4th dielectric layer.
In the present embodiment, the surface of the 4th dielectric layer 125 is lower than the top surface of the channel column 110；It is returning While etching the 4th dielectric material film or later, third dielectric layer 114 described in etched portions, and expose described second The partial sidewall and top surface of doped region 109.
In one embodiment, after forming the 4th dielectric layer, further include 125 surface of the 4th dielectric layer with And the surface that second doped region 109 exposes forms the second conductive layer.Second conductive layer with described second for mixing Miscellaneous area 109 is electrically connected.The material of second conductive layer includes metal or metallic compound.
Correspondingly, the embodiment of the present invention also provide it is a kind of vertical nanowire transistor is formed by using the above method, ask Continue to refer to figure 13, comprising:
The surface of substrate 100, the substrate 100 has multiple channel columns, and the multiple channel column is each perpendicular to the lining 100 surface of bottom has several first channel columns 111 and several second channel columns 112, first ditch in the multiple channel column Road column 111 and the second channel column 112 are used to form the transistor of the first conduction type, have the in the first channel column 111 One channel region 121, and there is the second channel region 122 in the second channel column 112；
Positioned at the first gate dielectric layer 116 of the sidewall surfaces of the first channel region 121 of the first channel column 111；
Positioned at the second gate dielectric layer 117 of the sidewall surfaces of the second channel region 122 of the second channel column 112；
The first work content table structure 118 positioned at 116 surface of the first gate dielectric layer；
The second work content table structure 119 positioned at 117 surface of the second gate dielectric layer, and the second work content table structure 119 work function is different from the work function of the first work content table structure 118；
First grid layer 123 positioned at 118 surface of the first work content table structure；
Second grid layer 124 positioned at 119 surface of the second work content table structure.
Figure 14 to Figure 22 is that the cross-section structure of the forming process of the vertical nanowire transistor of another embodiment of the application shows It is intended to.
Figure 14 and Figure 15 are please referred to, Figure 15 is the schematic diagram of the section structure of the Figure 14 along the direction BB ', provides substrate, the lining The surface at bottom 200 has multiple channel columns 240, and the multiple channel column 240 is each perpendicular to 200 surface of substrate, described more There is several first channel columns 241 and several second channel columns 242, the first channel column 241 and second in a channel column 240 Channel column 242 is used to form the transistor of the first conduction type, has the first channel region 221 in the first channel column 241, and There is the second channel region 222 in the second channel column 242.
In the present embodiment, first conductivity type of transistor is P-type transistor；The first channel column 241 is used for Form the first P-type transistor；The second channel column 242 is used to form the second P-type transistor, second P-type transistor Threshold voltage is greater than the threshold voltage of the first P-type transistor.
In the present embodiment, also there is several third channel columns 243 and several 4th channels in the multiple channel column 240 Column 244, the third channel column 243 and the 4th channel column 244 are used to form the transistor of the second conduction type, the third ditch There is third channel region 223 in road column 243, and there is the 4th channel region 224 in the 4th channel column 244.
Second conductivity type of transistor is N-type transistor；The third channel column 243 is used to form the first N-type crystalline substance Body pipe；The 4th channel column 244 is used to form the second N-type transistor, and the threshold voltage of second N-type transistor is greater than the The threshold voltage of one N-type transistor.
The quantity of the third channel column 243 is one or more；The quantity of the 4th channel column 244 is one or more It is a.
In another embodiment, first conductivity type of transistor is N-type transistor；The first channel column is used for shape At the first N-type transistor；The second channel column is used to form the second N-type transistor, the threshold value electricity of second N-type transistor Pressure is greater than the threshold voltage of the first N-type transistor.
In other embodiments, also there is several 5th channel columns, the 5th channel column in the multiple channel column 240 It is used to form the transistor of the first conduction type, there is the 5th channel region in the 5th channel column；The multiple channel column 240 In also there are several 6th channel columns, the 6th channel column is used to form the transistor of the second conduction type, the 6th ditch There is the 6th channel region in road column.
In this embodiment, the 5th channel column is used to form third P-type transistor, and the third P-type transistor Threshold voltage less than the first P-type transistor threshold voltage.The 6th channel column is used to form third N-type transistor, and Threshold voltage of the threshold voltage of the third N-type transistor less than the first N-type transistor.
The related description of the channel column 240 and substrate 200 does not repeat again as described in preamble embodiment.
Figure 16 is please referred to, forms first medium layer 202 over the substrate, the first medium layer 202 surrounds described more A channel column 240；After forming the first medium layer 202, in the first channel column 241 and the second channel column 242 It is inside respectively formed the first doped region 204, first doped region 204 is located at 221 bottom of the first channel region and second 222 bottom of channel region.
The first medium layer 202, the material of the first doped region 204, process and structure are as described in preamble embodiment, herein It does not repeat.
In the present embodiment, third doping is respectively formed also in the third channel column 243 and in the 4th channel column 244 Area 250, the third doped region 250 are located at 223 bottom of third channel region and 224 bottom of the 4th channel region.
In the present embodiment, first conductivity type of transistor is P-type transistor, then in first doped region 204 Doped ions be P-type ion, the Doped ions in the third doped region 250 are N-type ion；The P-type ion includes boron Ion or indium ion；The N-type ion includes phosphonium ion or arsenic ion.
In other embodiments, first conductivity type of transistor is N-type transistor, then in first doped region Doped ions are N-type ion, and the Doped ions in the third doped region are P-type ion.
The forming method of the third doped region 250 includes: on the substrate 200, the side of the multiple channel column 240 Wall surface forms third mask layer, and the third mask layer exposes in the third channel column 243 and 244 bottom of the 4th channel column The partial sidewall surface in portion；Using the third mask layer as exposure mask, in the third channel column 243 and the 4th channel column 244 Interior doping forms third doped region 250.
Forming method, material and the technique of the third mask layer are identical as the first mask layer, and this will not be repeated here.
Please continue to refer to Figure 16, the first conductive layer 205 on 202 surface of first medium layer, first conductive layer 205 surround the multiple channel column 240, and first conductive layer 205 is located at 204 sidewall surfaces of the first doped region；? First conductive layer, 205 surface forms second dielectric layer 206；Sacrificial layer 207 is formed on 206 surface of second dielectric layer, The surface of the sacrificial layer 207 is lower than the top surface of the multiple channel column 204, and the sacrificial layer 207 surrounds the multiple Channel column 240, and the sacrificial layer 207 is located at the side wall of first channel region 221 and the side of second channel region 222 Wall；Initial third dielectric layer 208 is formed on 207 surface of sacrificial layer, the initial third dielectric layer 208 surrounds the multiple Channel column 240.
First conductive layer 205, second dielectric layer 207, sacrificial layer 207 and initial third dielectric layer 208 material, ruler Very little and formation process is as described in preamble embodiment, and this will not be repeated here.
Figure 17 is please referred to, after forming the initial third dielectric layer 208, in the first channel column 241 and the The second doped region 209 is respectively formed in two channel columns 242, second doped region 209 is located at first channel region 221 222 top of top and the second channel region, first doped region 204 are identical with the conduction type of the second doped region 209.
Described in forming method, material and the structure and preamble embodiment of second doped region 209, therefore not to repeat here.
In the present embodiment, the 4th doping is respectively formed also in the third channel column 243 and in the 4th channel column 244 Area 251, the 4th doped region 251 is located at 223 top of third channel region and 224 top of the 4th channel region, described Third doped region 250 is identical with the conduction type of the 4th doped region 251.
The forming method of 4th doped region 251 includes: the 4th mask layer of formation on the substrate 200, and described the Four mask layers expose the top surface of the third channel column 243 and the top surface of the 4th channel column 244；With described 4th mask layer is exposure mask, and doping forms the 4th doped region 251 in the third channel column 243 and in the 4th channel column 244.
4th doped region 251 is used to be formed by the second conduction as third channel column 243 and the 4th channel column 244 The source electrode of the transistor of type or drain electrode.In the present embodiment, the 4th doped region 251 is used to be used as source electrode.
In the present embodiment, second conductivity type of transistor is N-type transistor, then in the 4th doped region 251 Doped ions be N-type ion.In other embodiments, second conductivity type of transistor is P-type transistor, then described the Doped ions in four doped regions 251 are P-type ion.
In the present embodiment, the 4th mask layer is located at initial 208 surface of third dielectric layer.
Forming method, material and the structure of 4th doped region 251 are close with second doped region 209, herein not It repeats.
Figure 18 is please referred to, after forming second doped region 251, the initial third dielectric layer 208 in removal part (is such as schemed Shown in 17) and the part sacrificial layer 207 (as shown in figure 17) is exposed, it is formed and is exposed positioned at the multiple channel column 240 Sidewall surfaces third dielectric layer 214；The sacrificial layer 207 is removed, in the third dielectric layer 214 and second dielectric layer Formed between 206 and expose gate openings 215, the gate openings 215 expose first channel region 221 side wall and The side wall of second channel region 222.
In the present embodiment, after removing the sacrificial layer 207, the gate openings 215 also expose the third The side wall of the side wall of channel region 223 and the 4th channel region 224.
The technique of the third dielectric layer and the removal sacrificial layer 207 is formed as described in preamble embodiment, herein not It repeats.
Figure 19 is please referred to, forms the first gate medium in the sidewall surfaces of the first channel region 221 of the first channel column 241 Layer 216；The second gate dielectric layer 217 is formed in the sidewall surfaces of the second channel region 222 of the second channel column 242.
In the present embodiment, third grid also are formed in the sidewall surfaces of the third channel region 223 of the third channel column 243 Dielectric layer 252；The 4th gate dielectric layer 253 is formed in the sidewall surfaces of the 4th channel region 224 of the 4th channel column 244.Institute State the first gate dielectric layer 216, the second gate dielectric layer 217, third gate dielectric layer 252 and the 4th gate dielectric layer 253 be also located at it is described 206 surface of second dielectric layer
First gate dielectric layer 216, the second gate dielectric layer 217, third gate dielectric layer 252 and the 4th gate dielectric layer 253 Material, thickness, locations of structures it is identical with the first gate dielectric layer in formation process such as preamble embodiment and the second gate dielectric layer, This is not repeated.
The enlarged fragmentary cross section that Figure 20 and Figure 21 is region C, region D, region E and region F in Figure 20 is please referred to, in institute It states 216 surface of the first gate dielectric layer and forms the first work content table structure 218；Second is formed on 217 surface of the second gate dielectric layer Work content table structure 219, and the work function of the second work content table structure 219 is different from the work function of the first work content table structure 218； Third work content table structure 254 is formed on 252 surface of third gate dielectric layer；It is formed on 253 surface of the 4th gate dielectric layer 4th work content table structure 255, and the work function of the work function of the 4th work content table structure 255 and third work content table structure 254 It is different.
In the present embodiment, threshold voltage of the threshold voltage of the first P-type transistor less than the second P-type transistor.It is described First work content table structure 218 includes: the first work-function layer 231, the second work-function layer positioned at 231 surface of the first work-function layer 232 and the third work-function layer 235 positioned at 232 surface of the second work-function layer；The second work content table structure 219 includes first Work-function layer 231 and third work-function layer 235 positioned at 231 surface of the first work-function layer.
In the present embodiment, the material of first work-function layer 231 is p-type work function material；Second work function The material of layer 232 is p-type work function material；The material of the third work-function layer 235 is P-type workfunction layer material；The p-type Work function material includes TiN and TaN.The material and third of the material of first work-function layer 231, the second work-function layer 232 The material of work-function layer is identical or different.
In the present embodiment, the material of first work-function layer 231, the second work-function layer 232 material and third function The material of function layer is identical.The material of first work-function layer 231 is TiN or TaN；The material of second work-function layer 232 Material is TiN or TaN；The material of the third work-function layer 235 is TiN or TaN.The thickness model of first work-function layer 231 Enclose is 8 angstroms~12 angstroms；The thickness range of second work-function layer 232 is 8 angstroms~12 angstroms；The third work-function layer 235 Thickness range is 8 angstroms~12 angstroms.The shape of first work-function layer 231, the second work-function layer 232 and third work-function layer 235 It include atom layer deposition process at technique.
In the present embodiment, the Second Type transistor is N-type transistor, and the threshold value of second N-type transistor Voltage is greater than the threshold voltage of the first N-type transistor, then the 4th work content table structure includes: third work-function layer 235.Due to The material of third work-function layer 235 is P-type workfunction layer material, and the threshold voltage of the second N-type transistor is enabled to be greater than the The threshold voltage of one N-type transistor.
When the material of the third work-function layer 235 is TiN, the thickness of the third work-function layer 235 is every to increase 10 Angstrom, the threshold voltage of second N-type transistor increases 20 millivolts compared with the threshold voltage of the first N-type transistor.
In one embodiment, the third work content table structure 254 can also include: the 4th function on third gate dielectric layer surface Function layer；The 4th work content table structure 255 includes: the 4th work-function layer positioned at 235 surface of third work-function layer；Institute The material for stating the 4th work-function layer is N-type work function material；The N-type work function material includes TiAl.
In another embodiment, the first kind transistor is N-type transistor.Second conductivity type of transistor is P-type transistor；The third channel column is used to form the first P-type transistor；The 4th channel column is used to form the second p-type crystalline substance The threshold voltage of body pipe, second P-type transistor is different from the threshold voltage of the first P-type transistor.
In other embodiments, also there is several 5th channel columns, the 5th channel column in the multiple channel column 240 It is used to form the transistor of the first conduction type, and also there are several 6th channel columns in the multiple channel column 240, described the Six channel columns are used to form the transistor of the second conduction type.It then in this embodiment, further include being exposed in gate openings 5th channel region side wall forms the 5th work content table structure, forms the 6th work content in the 6th channel region side wall that gate openings expose Table structure.
When the 5th channel column is used to form third P-type transistor, and the threshold voltage of the third P-type transistor is small When the threshold voltage of the first P-type transistor, the 5th work content table structure includes: the first work-function layer, is located at the first work content Count the second work-function layer of layer surface, positioned at the third work-function layer on the second work-function layer surface and positioned at third work-function layer 4th work-function layer on surface.The material of 4th work-function layer is P-type workfunction layer material, and the p-type work function material Material includes TiN and TaN.
When the 6th channel column is used to form third N-type transistor, and the threshold voltage of the third N-type transistor is small In the threshold voltage of the first N-type transistor；The 6th work content table structure includes: the 4th function positioned at the 6th gate dielectric layer surface Function layer and the 5th work-function layer positioned at the 4th work-function layer surface.The material of 4th work-function layer and the 5th work-function layer Material is N-type work function material.
In the present embodiment, before forming the first work content table structure and the second work content table structure, described first Gate dielectric layer and second gate dielectric layer surface form barrier layer 233.In one embodiment, it is formed and is stopped in the barrier layer surface Layer 234.In another embodiment, additionally it is possible to not form the stop-layer.
In the present embodiment, the material of the stop-layer is different with the material of the first work function body structure surface contacted, And the material of the stop-layer is different with the material of the second work function body structure surface contacted.The stop-layer and barrier layer are such as Described in preamble embodiment, this will not be repeated here.
Figure 22 is please referred to, forms first grid layer 225 on 218 surface of the first work content table structure；In second function 219 surface of function structure forms second grid layer 226.
In the present embodiment, further includes: form third grid layer 227 on 254 surface of third work content table structure；In the 4th function 255 surface of function structure forms the 4th grid layer 228.
In one embodiment, it before forming first grid layer 225, is formed on 218 surface of the first work content table structure First coating；Before forming second grid layer 226, the second coating is formed on 219 surface of the second work content table structure； Before forming third grid layer 227, third coating is formed on 254 surface of third work content table structure；Forming the 4th Before grid layer 228, the 4th coating is formed on 255 surface of the 4th work content table structure.
In one embodiment, first coating, the second coating, third coating and the 4th coating while shape At.
Size of the first grid layer 225 on the direction perpendicular to substrate surface is 28 nanometers~32 nanometers；It is described Size of the second grid layer 226 on the direction perpendicular to substrate surface is 28 nanometers~32 nanometers；The third grid layer 227 Size on the direction perpendicular to substrate surface is 28 nanometers~32 nanometers；4th grid layer 228 is perpendicular to substrate Size on the direction on surface is 28 nanometers~32 nanometers.
First coating, the second coating, third coating, the 4th coating, first grid layer and second grid layer Material and formation process such as the first coating, the second coating, first grid layer and the second grid layer institute in preamble embodiment It states, therefore not to repeat here.
In the present embodiment, the 4th dielectric layer 229, institute are formed in the first grid layer surface and second grid layer surface State the sidewall surfaces that the 4th dielectric layer 229 is also located at the third dielectric layer 214.The material of 4th dielectric layer such as preamble is real It applies described in example, therefore not to repeat here.
The forming method of 4th dielectric layer 229 includes: in first grid layer 225, second grid layer 226, third grid Pole layer 227,228 surface of the 4th grid layer and 214 surface of third dielectric layer form the 4th dielectric material film, the 4th medium material Expect that the surface of film is higher than the top of the channel column 240；After planarizing the 4th dielectric material film, it is etched back to the described 4th Dielectric material film forms initial 4th dielectric layer.
In the present embodiment, the surface of the 4th dielectric layer 229 is lower than the top surface of the channel column 240；It is returning While etching the 4th dielectric material film or later, third dielectric layer 214 described in etched portions, and expose the channel The partial sidewall and top surface of column 240.
In one embodiment, after forming the 4th dielectric layer, further include 125 surface of the 4th dielectric layer with And the surface that second doped region 109 exposes forms the second conductive layer.Second conductive layer with described second for mixing Miscellaneous area 109 is electrically connected.In the surface shape that 125 surface of the 4th dielectric layer and the 4th doped region 251 expose At third conductive layer.The third conductive layer with the 4th doped region 251 for being electrically connected.Second conductive layer and The material of third conductive layer includes metal or metallic compound.
Correspondingly, the embodiment of the present invention also provide it is a kind of vertical nanowire transistor is formed by using the above method, ask With continued reference to Figure 22, comprising:
The surface of substrate, the substrate 200 has multiple channel columns, and the multiple channel column is each perpendicular to the substrate 200 surfaces have several first channel columns 221, several second channel columns 222, several third channels in the multiple channel column Column 243 and several 4th channel columns 224, the first channel column 242 and the second channel column 243 are used to form the first conduction type Transistor, there is the first channel region 221 in the first channel column 242, and there is the second ditch in the second channel column 243 Road area 222, the third channel column 243 and the 4th channel column 224 are used to form the transistor of the second conduction type, the third There is third channel region 223 in channel column 243, and there is the second channel region 224 in the 4th channel column 224；
Positioned at the first gate dielectric layer 216 of the sidewall surfaces of the first channel region 221 of the first channel column 241；
Positioned at the second gate dielectric layer 217 of the sidewall surfaces of the second channel region 222 of the second channel column 242；
Positioned at the third gate dielectric layer 252 of the sidewall surfaces of the third channel region 223 of the third channel column 243；
Positioned at the 4th gate dielectric layer 253 of the sidewall surfaces of the 4th channel region 224 of the 4th channel column 244；
The first work content table structure 218 positioned at 216 surface of the first gate dielectric layer；
The second work content table structure 219 positioned at 217 surface of the second gate dielectric layer, and the second work content table structure Work function is different from the work function of the first work content table structure；
Third work content table structure 252 positioned at 252 surface of third gate dielectric layer；
The 4th work content table structure 255 positioned at 253 surface of the 4th gate dielectric layer, and the 4th work content table structure Work function is different from the work function of third work content table structure；
First grid layer 225 positioned at 218 surface of the first work content table structure；
Second grid layer 226 positioned at 219 surface of the second work content table structure；
Third grid layer 227 positioned at 252 surface of third work content table structure；
The 4th grid layer 228 positioned at 255 surface of the 4th work content table structure.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (39)

1. a kind of forming method of vertical nanowire transistor characterized by comprising
Substrate is provided, the surface of the substrate has multiple channel columns, and the multiple channel column is each perpendicular to the substrate surface, There is several first channel columns and several second channel columns, the first channel column and the second channel column in the multiple channel column It is used to form the transistor of the first conduction type, there is the first channel region, and the second channel column in the first channel column Inside there is the second channel region；
The first gate dielectric layer is formed in the sidewall surfaces of the first channel region of the first channel column；
The second gate dielectric layer is formed in the sidewall surfaces of the second channel region of the second channel column；
The first work content table structure is formed in the first grid dielectric layer surface；
The second work content table structure, and the work function of the second work content table structure and the are formed in the second gate dielectric layer surface The work function of one work content table structure is different；
First grid layer is formed in the first work function body structure surface；
Second grid layer is formed in the second work function body structure surface.
2. the forming method of vertical nanowire transistor as described in claim 1, which is characterized in that first conduction type Transistor is P-type transistor；The first channel column is used to form the first P-type transistor；The second channel column is used to form Second P-type transistor, the threshold voltage of second P-type transistor are greater than the threshold voltage of the first P-type transistor.
3. the forming method of vertical nanowire transistor as claimed in claim 2, which is characterized in that the first work function knot Structure includes: the first work-function layer and the second work-function layer positioned at the first work-function layer surface；The second work content table structure Including the first work-function layer；The material of first work-function layer is p-type work function material；The material of second work-function layer For p-type work function material.
4. the forming method of vertical nanowire transistor as claimed in claim 3, which is characterized in that first work-function layer Material and the second work-function layer material it is identical or different；The material of first work-function layer is TiN or TaN；Described The material of two work-function layers is TiN or TaN.
5. the forming method of vertical nanowire transistor as described in claim 3 or 4, which is characterized in that first work content Several layers with a thickness of 8 angstroms~12 angstroms；Second work-function layer with a thickness of 13 angstroms~18 angstroms.
6. the forming method of vertical nanowire transistor as claimed in claim 4, which is characterized in that when second work function When the material of layer is TiN, the thickness of second work-function layer is every to increase 10 angstroms, the threshold voltage of second P-type transistor Threshold voltage compared with the first P-type transistor increases 80 millivolts~120 millivolts.
7. the forming method of vertical nanowire transistor as claimed in claim 2, which is characterized in that the first work function knot Structure and the second work content table structure are single layer structure, and the first work content table structure is identical with the material of the second work content table structure, And first work content table structure thickness be greater than the second work content table structure thickness；The first work content table structure and the second work function The material of structure is TiN or TaN.
8. the forming method of vertical nanowire transistor as claimed in claim 7, which is characterized in that when first work function When the material of structure and the material of the second work content table structure are TiN, the thickness of the second work content table structure first function The thickness of function structure is every to increase 10 angstroms, the threshold voltage of the threshold voltage of second N-type transistor compared with the first N-type transistor Reduce by 80 millivolts~120 millivolts.
9. the forming method of vertical nanowire transistor as claimed in claim 2, which is characterized in that in the multiple channel column Also there is several third channel columns and several 4th channel columns, the third channel column and the 4th channel column are used to form second and lead The transistor of electric type, the third channel column is interior to have third channel region, and has the 4th channel in the 4th channel column Area；The forming method further include: form third gate dielectric layer in the sidewall surfaces of the third channel region of the third channel column； The 4th gate dielectric layer is formed in the sidewall surfaces of the 4th channel region of the 4th channel column；On third gate dielectric layer surface Form third work content table structure；The 4th work content table structure, and the 4th work function are formed on the 4th gate dielectric layer surface The work function of structure is different from the work function of third work content table structure；Third grid is formed in the third work function body structure surface Layer；The 4th grid layer is formed in the 4th work function body structure surface.
10. the forming method of vertical nanowire transistor as claimed in claim 9, which is characterized in that second conductive-type Transistor npn npn is N-type transistor；The third channel column is used to form the first N-type transistor；The 4th channel column is used for shape At the second N-type transistor, the threshold voltage of second N-type transistor is greater than the threshold voltage of the first N-type transistor.
11. the forming method of vertical nanowire transistor as claimed in claim 10, which is characterized in that the 4th work function Structure includes: third work-function layer；The material of the third work-function layer is P-type workfunction layer material.
12. the forming method of vertical nanowire transistor as claimed in claim 11, which is characterized in that first work function Structure includes: the first work-function layer, positioned at second work-function layer on the first work-function layer surface and positioned at the second work-function layer The third work-function layer on surface；The second work content table structure is including the first work-function layer and is located at the first work-function layer surface Third work-function layer；The material of first work-function layer is p-type work function material；The material of second work-function layer is P-type work function material.
13. the forming method of the vertical nanowire transistor as described in claim 11 or 12, which is characterized in that the third function The material of function layer is TiN or TaN；The third work-function layer with a thickness of 8 angstroms~12 angstroms.
14. the forming method of vertical nanowire transistor as claimed in claim 13, which is characterized in that when the third work content When several layers of material is TiN, the thickness of the third work-function layer is every to increase 10 angstroms, the threshold value electricity of second N-type transistor The threshold voltage compared with the first N-type transistor is pressed to increase 18 millivolts~22 millivolts.
15. the forming method of vertical nanowire transistor as claimed in claim 11, which is characterized in that the third work function Structure includes: the 4th work-function layer；The 4th work content table structure includes: the 4th function positioned at third work-function layer surface Function layer；The material of 4th work-function layer is N-type work function material；The N-type work function material includes TiAl.
16. the forming method of vertical nanowire transistor as described in claim 1, which is characterized in that first conductive-type Transistor npn npn is N-type transistor；The first channel column is used to form the first N-type transistor；The second channel column is used for shape At the second N-type transistor, the threshold voltage of second N-type transistor is greater than the threshold voltage of the first N-type transistor.
17. the forming method of vertical nanowire transistor as claimed in claim 16, which is characterized in that first work function Structure includes: the first work-function layer and the second work-function layer positioned at the first work-function layer surface；The second work function knot Structure includes the first work-function layer.The material of first work-function layer is N-type work function material；The material of second work-function layer Material is N-type work function material.
18. the forming method of vertical nanowire transistor as claimed in claim 17, which is characterized in that first work function The material of layer is TiAl；The material of second work-function layer is TiAl；First work-function layer with a thickness of 8 angstroms~12 Angstrom；Second work-function layer with a thickness of 13 angstroms~18 angstroms.
19. the forming method of vertical nanowire transistor as claimed in claim 18, which is characterized in that when second work content When several layers of material is TiAl, the thickness of second work-function layer is every to increase 10 angstroms, the threshold value electricity of second N-type transistor The threshold voltage compared with the first N-type transistor is pressed to increase 80 millivolts~120 millivolts.
20. the forming method of vertical nanowire transistor as claimed in claim 16, which is characterized in that the multiple channel column In also have several third channel columns and several 4th channel columns, the third channel column and the 4th channel column are used to form second The transistor of conduction type, the third channel column is interior to have third channel region, and has the 4th ditch in the 4th channel column Road area；The forming method further include: form third gate medium in the sidewall surfaces of the third channel region of the third channel column Layer；The 4th gate dielectric layer is formed in the sidewall surfaces of the 4th channel region of the 4th channel column；In the third gate dielectric layer Surface forms third work content table structure；The 4th work content table structure, and the 4th function are formed on the 4th gate dielectric layer surface The work function of function structure is different from the work function of third work content table structure；Third is formed in the third work function body structure surface Grid layer；The 4th grid layer is formed in the 4th work function body structure surface.
21. the forming method of vertical nanowire transistor as claimed in claim 20, which is characterized in that second conductive-type Transistor npn npn is P-type transistor；The third channel column is used to form the first P-type transistor；The 4th channel column is used for shape At the second P-type transistor, the threshold voltage of second P-type transistor is different from the threshold voltage of the first P-type transistor.
22. the forming method of the vertical nanowire transistor as described in claim 9 or 20, which is characterized in that described in formation Before third gate dielectric layer and the 4th gate dielectric layer, further includes: distinguish shape in the third channel column and in the 4th channel column At third doped region, the third doped region is located at third channel region bottom and the 4th channel region bottom；Described It is respectively formed the 4th doped region in third channel column and in the 4th channel column, the 4th doped region is located at the third ditch At the top of road area and at the top of the 4th channel region, the conduction type of the third doped region and the 4th doped region is identical.
23. the forming method of vertical nanowire transistor as described in claim 1, which is characterized in that forming described first Before gate dielectric layer and the second gate dielectric layer, further includes: be respectively formed the in the first channel column and in the second channel column One doped region, first doped region are located at first channel region bottom and the second channel region bottom；Described first It is respectively formed the second doped region in channel column and in the second channel column, second doped region is located at first channel region At the top of top and the second channel region, the conduction type of first doped region and the second doped region is identical.
24. the forming method of vertical nanowire transistor as claimed in claim 23, which is characterized in that first doped region Forming method include: over the substrate, the sidewall surfaces of the multiple channel column formed the first mask layer, described first covers Film layer exposes the partial sidewall surface of first channel column bottom, and first mask layer exposes second channel The partial sidewall surface of column bottom；Using first mask layer as exposure mask, in the first channel column and in the second channel column Doping forms the first doped region.
25. the forming method of vertical nanowire transistor as claimed in claim 24, which is characterized in that second doped region Forming method include: to form the second mask layer over the substrate, second mask layer exposes the first channel column Top surface and the second channel column top surface；Using second mask layer as exposure mask, in the first channel column Doping forms the second doped region in interior and the second channel column.
26. the forming method of vertical nanowire transistor as claimed in claim 23, which is characterized in that be situated between forming the first grid Before matter layer and the second gate dielectric layer, further includes: form first medium layer over the substrate, the first medium layer surrounds institute State multiple channel columns；In the first conductive layer of the first medium layer surface, first conductive layer surrounds the multiple channel Column, and first conductive layer is located at the first doped region sidewall surfaces；Second is formed in first conductive layer surface to be situated between Matter layer；First gate dielectric layer is also located at the second medium layer surface；Second gate dielectric layer is also located at described second Dielectric layer surface.
27. the forming method of vertical nanowire transistor as claimed in claim 26, which is characterized in that be situated between forming the first grid Before matter layer and the second gate dielectric layer, further includes: form sacrificial layer, the surface of the sacrificial layer in the second medium layer surface Lower than the top surface of the multiple channel column, the sacrificial layer surrounds the multiple channel column, and the sacrificial layer is located at institute State the side wall of the first channel region and the side wall of second channel region；Third dielectric layer, institute are formed in the sacrificial layer surface It states third dielectric layer and surrounds the multiple channel column, the third dielectric layer is located at the side wall table that the multiple channel column exposes Face, and the third dielectric layer exposes the part sacrificial layer；The sacrificial layer is removed, in the third dielectric layer and second It is formed between dielectric layer and exposes gate openings, the gate openings expose the side wall and described the of first channel region The side wall of two channel regions；First gate dielectric layer is formed in the sidewall surfaces for the first channel region that the gate openings expose It is located at；Second gate dielectric layer is formed in the sidewall surfaces for the second channel region that the gate openings expose to be located at.
28. the forming method of vertical nanowire transistor as claimed in claim 27, which is characterized in that further include: described First grid layer surface and second grid layer surface form the 4th dielectric layer, and the 4th dielectric layer is also located at the third medium The sidewall surfaces of layer.
29. the forming method of vertical nanowire transistor as described in claim 1, which is characterized in that further include: forming institute Before stating the first work content table structure and the second work content table structure, formed in first gate dielectric layer and second gate dielectric layer surface Barrier layer.
30. the forming method of vertical nanowire transistor as claimed in claim 29, which is characterized in that further include: described Barrier layer surface forms stop-layer.
31. the forming method of vertical nanowire transistor as claimed in claim 30, which is characterized in that the material of the stop-layer Material and the material of the first work function body structure surface for being contacted difference, and the material of the stop-layer and the second work content for being contacted The material on table structure surface is different.
32. the forming method of vertical nanowire transistor as claimed in claim 30, which is characterized in that the material of the stop-layer Material is TaN.
33. the forming method of vertical nanowire transistor as claimed in claim 30, which is characterized in that the material on the barrier layer Material is TiN or TaN.
34. the forming method of vertical nanowire transistor as described in claim 1, which is characterized in that forming first grid Before layer, the first coating is formed in the first work function body structure surface；Before forming second grid layer, described second Work function body structure surface forms the second coating.
35. the forming method of vertical nanowire transistor as claimed in claim 34, which is characterized in that first coating Material include TaN or TiN；The material of second coating includes TaN or TiN.
36. the forming method of vertical nanowire transistor as described in claim 1, which is characterized in that the week of the channel column A length of 30 nanometers~40 nanometers.
37. the forming method of vertical nanowire transistor as described in claim 1, which is characterized in that the first grid layer Size on the direction perpendicular to substrate surface is 28 nanometers~32 nanometers；The second grid layer is perpendicular to substrate surface Direction on size be 28 nanometers~32 nanometers.
38. the forming method of vertical nanowire transistor as described in claim 1, which is characterized in that first gate medium The material of layer and the second gate dielectric layer includes high K dielectric material；The material of the first grid layer and second grid layer includes gold Belong to.
39. a kind of be formed by vertical nanowire transistor using such as any one of claims 1 to 38 method, which is characterized in that Include:
The surface of substrate, the substrate has multiple channel columns, and the multiple channel column is each perpendicular to the substrate surface, described There is several first channel columns and several second channel columns, the first channel column and the second channel column are used in multiple channel columns The transistor of the first conduction type is formed, there is the first channel region, and tool in the second channel column in the first channel column There is the second channel region；
Positioned at the first gate dielectric layer of the sidewall surfaces of the first channel region of the first channel column；
Positioned at the second gate dielectric layer of the sidewall surfaces of the second channel region of the second channel column；
Positioned at the first work content table structure of the first grid dielectric layer surface；
Positioned at the second work content table structure of the second gate dielectric layer surface, and the work function of the second work content table structure and the The work function of one work content table structure is different；
Positioned at the first grid layer of the first work function body structure surface；
Positioned at the second grid layer of the second work function body structure surface.
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